CN105679826A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN105679826A
CN105679826A CN201510881401.7A CN201510881401A CN105679826A CN 105679826 A CN105679826 A CN 105679826A CN 201510881401 A CN201510881401 A CN 201510881401A CN 105679826 A CN105679826 A CN 105679826A
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CN
China
Prior art keywords
groove
cushion
channel region
semiconductor device
layer
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Granted
Application number
CN201510881401.7A
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Chinese (zh)
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CN105679826B (en
Inventor
李哉勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN105679826A publication Critical patent/CN105679826A/en
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Publication of CN105679826B publication Critical patent/CN105679826B/en
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L29/1025—Channel region of field-effect devices
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

Description

Semiconductor device
Technical field
Present inventive concept relates to the semiconductor device with cushion and the method forming this semiconductor device.
Background technology
Along with transistor is scaled dimensionally, its On current can reduce. The reduction of On current can cause that the speed of operation of transistor reduces.
Summary of the invention
An illustrative embodiments according to present inventive concept, it is provided that a kind of semiconductor device is as follows. Substrate includes NMOS area and PMOS area. First groove and the second groove are arranged in NMOS area. First cushion is arranged in the first groove and the second groove. Stress solid (stressor) is arranged in the first groove and the second groove and is arranged on the first cushion. First channel region is arranged between the first groove and the second groove and arranges in a substrate. First gate electrode is arranged on the first channel region. 3rd groove is arranged in PMOS area. Second cushion is arranged in the 3rd groove. Second channel region is arranged in the 3rd groove, is arranged on the second cushion, and has the semi-conducting material different from substrate. Second gate electrode is arranged on the second channel region.
An illustrative embodiments according to present inventive concept, it is provided that a kind of semiconductor device is as follows. First groove and the second groove are arranged in a substrate. Channel region is arranged between the first groove and the second groove and in a substrate. Gate electrode is arranged on channel region. Cushion is arranged in the first groove and the second groove. Stress solid is arranged in the first groove and the second groove and arranges on the buffer layer.
An illustrative embodiments according to present inventive concept, it is provided that a kind of semiconductor device is as follows. Drain region and source region are arranged in a substrate. Groove is arranged between drain region and source region and arranges in a substrate. Cushion is arranged in the trench. Channel region is arranged in the trench, arranges on the buffer layer, and has the semi-conducting material different from drain region and source region. Gate electrode is arranged on channel region.
An illustrative embodiments according to present inventive concept, it is provided that a kind of method forming semiconductor device is as follows. Form the first groove and the second groove in a substrate. First groove and the second groove form the first cushion. First cushion is formed stress solid. In a substrate and between the first groove and the second groove, form the first channel region. First channel region is formed first gate electrode. Form the 3rd groove in a substrate. 3rd groove forms the second cushion.Second cushion is formed the second channel region. Second channel region includes the semi-conducting material different from substrate. Second channel region is formed second gate electrode.
An illustrative embodiments according to present inventive concept, it is provided that a kind of semiconductor device is as follows. First trap and the second trap are arranged in a substrate. First trap and the second trap are isolated from each other by device isolation layer. First groove and the second groove are arranged in the first trap. First channel region is arranged between the first groove and the second groove and arranges in a substrate. First gate electrode is arranged on the first channel region. 3rd groove is arranged in the second trap. Second channel region is arranged in the 3rd groove. Second channel region is formed by the semi-conducting material different from the second trap. Second gate electrode is arranged on the second channel region.
Accompanying drawing explanation
The illustrative embodiments of present inventive concept is described in detail by referring to accompanying drawing, the these and other feature of present inventive concept will be apparent from, in accompanying drawing:
Fig. 1 to Figure 12 is the sectional view of the semiconductor device of the illustrative embodiments according to present inventive concept;
Figure 13 to Figure 40 is the sectional view of the method forming semiconductor device of the illustrative embodiments according to present inventive concept; And
Figure 41 and Figure 42 is the system block diagram of the electronic equipment of the illustrative embodiments according to present inventive concept.
Although the corresponding flat figure of some sectional views and/or perspective view can not be illustrated, but the sectional view of shown here device architecture be along two different directions (as illustrated in plan view) and/or three different directions (as illustrated in the perspective) extension multiple device architectures provide support. The direction that said two is different can be perpendicular to one another or can not be perpendicular to one another. Described three different directions can include the third direction that can be perpendicular to the different direction of said two. The plurality of device architecture can be integrated in same electronic device. Such as, when illustrating device architecture (such as, memory unit or transistor arrangement) in the sectional views, electronic device can include multiple device architecture (such as, memory unit or transistor arrangement), as by shown by the plane graph of this electronic device. The plurality of device architecture can be arranged to array and/or two-dimensional pattern.
Detailed description of the invention
The illustrative embodiments of present inventive concept is described in detail below with reference to accompanying drawings. But, present inventive concept can be implemented in different forms and should not be construed as limited to the embodiment illustrated here. In the accompanying drawings, in order to clearly, the thickness in layer and region can be exaggerated. It will also be understood that when an element be referred to as " " another element or substrate " on " time, directly on another element described or substrate, or can also there is intervening elements in it. It will also be understood that when an element is referred to as " being connected to " or " being connected to " another element, it can be directly coupled to or be connected to another element described, or can also there is intervening elements. Identical accompanying drawing labelling can refer to identical element in entire disclosure and accompanying drawing.
Fig. 1 to Figure 12 is the sectional view of the semiconductor device of the illustrative embodiments according to present inventive concept.
With reference to Fig. 1, the semiconductor device of the illustrative embodiments according to present inventive concept includes forming the p-well 23 on the substrate 21 comprising NMOS area and PMOS area, N trap 24, device isolation layer 25, first sept 37, first groove 39T1, second groove 39T2, 3rd groove 39T3, first channel region 27, first cushion 46, stress solid 47, ohmic contact layer 49, second cushion 57, second channel region 58, first grid dielectric layer 62, first gate electrode 64, first grid overlay pattern 66, second sept 68, drain region 69D, source region 69S, second gate dielectric layer 74, second gate electrode 77 and second gate overlay pattern 78.First cushion 46 includes cushion 45 on the first bottom breaker 43 and first. Second cushion 57 includes cushion 56 on the second bottom breaker 54 and second.
P-well the 23, first sept the 37, first groove 39T1, the second groove 39T2, first channel region the 27, first cushion 46, stress solid 47, ohmic contact layer 49, second gate dielectric layer 74, second gate electrode 77 and second gate overlay pattern 78 are formed in NMOS area. N trap the 24, the 3rd groove 39T3, second cushion the 57, second channel region 58, first grid dielectric layer 62, first gate electrode 64, first grid overlay pattern the 66, second sept 68, drain region 69D and source region 69S are formed in PMOS area.
Substrate 21 can include Si, Ge, silicon-on-insulator (SOI), sapphire, glass, AlN, SiC, GaAs, InAs, Graphene, CNT (CNT), plastics or its combination. Such as, substrate 21 can be the silicon single crystal wafer comprising p type impurity. First channel region 27 is arranged between the first groove 39T1 and the second groove 39T2. First channel region 27 can include the monocrystal silicon comprising p type impurity. The lower part of the first groove 39T1 and the lower part of the second groove 39T2 are V-arrangements. The sidewall of the first groove 39T1 and the sidewall of the second groove 39T2 are C shapes. Such as, left side wall is "<" shape, right side wall is ">" shape.
Stress solid 47 can be formed on the first cushion 46 in the first groove 39T1 and the second groove 39T2. First cushion 46 is around the bottom of stress solid 47 and side surface. Stress solid 47 can be formed by the material with the lattice paprmeter different from the first channel region 27. Stress solid 47 can include the material with the lattice paprmeter less than the first channel region 27. Such as, stress solid 47 can include GaN. The upper end substantially copline of the upper end of stress solid 47 and the first channel region 27.
First cushion 46 is formed in the first groove 39T1 and the second groove 39T2. The bottom of the first cushion 46 is V-arrangement. The sidewall of the first cushion 46 is C shape (such as, "<" shape or ">" shape). First cushion 46 can include AlxGa1-xN (0 < X≤1) grading structure, wherein the content of Al or doping change make the Al content of the first cushion 46 can near stress solid 47 or up reduce towards stress solid 47. The Al content of the first cushion 46 or doping can increase near the bottom of the first groove 39T1 and the second groove 39T2.
First bottom breaker 43 directly contacts with the inwall of the first groove 39T1 and the second groove 39T2. First bottom breaker 43 also directly contacts with the first channel region 27. The bottom of the first bottom breaker 43 is V-arrangement. The sidewall of the first bottom breaker 43 is C shape (such as, "<" shape or ">" shape). First bottom breaker 43 is plugged between stress solid 47 and the first channel region 27. First bottom breaker 43 directly contacts with the side surface of stress solid 47. Such as, the first bottom breaker 43 can include AlN.
On first, cushion 45 is formed on the first bottom breaker 43 in the first groove 39T1 and the second groove 39T2. On first, cushion 45 directly contacts with the bottom of stress solid 47. On first, cushion 45 can by AlxGa1-xN (0 < X≤1) grading structure is formed. On first, the Al content in cushion 45 can reduce near stress solid 47. On first, the Al content in cushion 45 can increase near the bottom of the first groove 39T1 and the second groove 39T2.
Such as, cushion 45 can include the ground floor of order stacking to layer 6 on first. On first, the ground floor of cushion 45 can be AlxGa1-xN (0.7≤X < 1) layer. On first, the second layer of cushion 45 can be AlxGa1-xN (0.5≤X < 0.7) layer and formation are on the first layer. On first, the third layer of cushion 45 can be AlxGa1-xN (0.3≤X < 0.5) layer and formation are on the second layer. On first, the 4th layer of cushion 45 can be AlxGa1-xN (0.1≤X < 0.3) layer and formation are in third layer. On first, the layer 5 of cushion 45 can be AlxGa1-xN (0.05≤x < 0.1) layer and formation are on the 4th layer. On first, the layer 6 of cushion 45 can be AlxGa1-xN (0 < x < 0.05) layer and formation are on layer 5.
Ohmic contact layer 49 is formed on stress solid 47. The upper end of ohmic contact layer 49 is raised to the horizontal plane higher than the upper end of the first channel region 27. Ohmic contact layer 49 can include InGaN, metal silicide or its combination. Second gate dielectric layer 74, second gate electrode 77 and second gate overlay pattern 78 are formed on the first channel region 27. First sept 37 is formed on the side surface of second gate electrode 77 and the side surface of second gate overlay pattern 78. Stress solid 47 can serve as source/drain.
The bottom of the 3rd groove 39T3 is V-arrangement. The sidewall of the 3rd groove 39T3 is C shape (such as, "<" shape or ">" shape). Second channel region 58 is formed on the second cushion 57 in the 3rd groove 39T3. Second cushion 57 is around the bottom of the second channel region 58 and side surface. Second channel region 58 can include the semi-conducting material different from N trap 24. Second channel region 58 can include the semi-conducting material with hole mobility higher compared with silicon. Such as, N trap 24 can include the monocrystal silicon comprising N-type impurity, and the second channel region 58 can include the Ge layer comprising N-type impurity.
Second cushion 57 is formed in the 3rd groove 39T3. The bottom of the second cushion 57 is V-arrangement. The sidewall of the second cushion 57 is C shape (such as, "<" shape or ">" shape). Second cushion 57 can include SiyGe1-y(0 < y≤1) grading structure. Ge content in second cushion 57 can change so that the Ge content of the second cushion 57 can increase near the second channel region 58. Ge content in second cushion 57 can reduce near the bottom of the 3rd groove 39T3.
Second bottom breaker 54 directly contacts with the inwall of the 3rd groove 39T3. Second bottom breaker 54 directly contacts with N trap 24, drain region 69D and source region 69S. The bottom of the second bottom breaker 54 is V-arrangement. The side surface of the second bottom breaker 54 is C shape (such as, "<" shape or ">" shape). Second bottom breaker 54 is plugged between the second channel region 58 and drain region 69D, between the second channel region 58 and source region 69S, between the second channel region 58 and N trap 24 and on second between cushion 56 and N trap 24. Second bottom breaker 54 directly contacts with the side surface of the second channel region 58. Such as, can include can epitaxially grown Si layer for the second bottom breaker 54.
On second, cushion 56 is formed on the second bottom breaker 54 in the 3rd groove 39T3. On second, cushion 56 directly contacts with the second channel region 58. On second, cushion 56 can include SiyGe1-y(0 < y≤1) grading structure. On second, the Ge content in cushion 56 or doping can change so that on second, the Ge content in cushion 56 or doping can increase near the second channel region 58 or up increase towards the second channel region 58.On second, the Ge content in cushion 56 can reduce near the bottom of the 3rd groove 39T3 or down reduce towards the 3rd groove 39T3.
Such as, cushion 56 can include the ground floor of order stacking to layer 6 on second. On second, the ground floor of cushion 56 can be SiyGe1-y((0.7≤y≤1) layer. On second, the second layer of cushion 56 can be SiyGe1-y(0.5≤y < 0.7) layer and formation are on the first layer. On second, the third layer of cushion 56 can be SiyGe1-y(0.3≤y < 0.5) layer and formation are on the second layer. On second, the 4th layer of cushion 56 can be SiyGe1-y(0.1≤y < 0.3) layer and formation are in third layer. On second, the layer 5 of cushion 56 can be SiyGe1-y(0.05≤y < 0.1) layer and formation are on the 4th layer. On second, the layer 6 of cushion 56 can be SiyGe1-y(0 < y < 0.05) layer and formation are on layer 5.
First grid dielectric layer 62, first gate electrode 64 and first grid overlay pattern 66 are formed on the second channel region 58. It is directed at the center vertical of the center of first gate electrode 64 and the second channel region 58. Second sept 68 is formed on the side surface of first gate electrode 64 and the side surface of first grid overlay pattern 66. Drain region 69D and source region 69S is adjacent to first gate electrode 64 and is formed in N trap 24.
Illustrative embodiments according to present inventive concept, due to the structure of stress solid 47, it is possible to cause tensile stress in the first channel region 27. The tensile stress produced by stress solid 47 can improve the electron mobility of the first channel region 27. First cushion 46 may be used for preventing from producing defect due to the differences between lattice constant between stress solid 47 and p-well 23. First cushion 46 may be used for preventing from cracking in stress solid 47. The V-shape of the first groove 39T1 and the second groove 39T2 may be used for release stress. Structure due to the second channel region 58, it is possible to improve hole mobility. Second cushion 57 may be used for preventing generation crystal growth defect in the second channel region 58.
With reference to Fig. 2, p-well 23, N trap 24, device isolation layer 25, first sept 37, first groove 39T1, second groove 39T2, 3rd groove 39T3, first channel region 27, first cushion 46, stress solid 47, ohmic contact layer 49, second cushion 57, second channel region 58, first grid dielectric layer 62, first gate electrode 64, first grid overlay pattern 66, second sept 68, drain region 69D, source region 69S, second time gate dielectric layer 73, gate dielectric layer 74 on second, second gate electrode 77, second gate overlay pattern 78, lower insulating barrier 71, upper insulating barrier 81 and contact plunger 83 are formed on the substrate 21 including NMOS area and PMOS area. first cushion 46 includes cushion 45 on the first bottom breaker 43 and first. second cushion 57 includes cushion 56 on the second bottom breaker 54 and second. second gate electrode 77 includes lower gate electrode 75 and upper gate electrode 76. second gate electrode 77 can be referred to as replacement gate.
With reference to Fig. 3, on p-well 23, device isolation layer the 25, first sept the 37, first groove 39T1, the second groove 39T2, first channel region the 27, first cushion 46, stress solid 47,49, second time gate dielectric layer 73, second of ohmic contact layer, gate dielectric layer 74, second gate electrode 77, second gate overlay pattern 78, lower insulating barrier 71, upper insulating barrier 81 and contact plunger 83 are formed on the substrate 21 including NMOS area.First cushion 46 includes cushion 45 on the first bottom breaker 43 and first. Second gate electrode 77 includes lower gate electrode 75 and upper gate electrode 76. The upper end of stress solid 47 and the upper end substantially copline of the first channel region 27. On stress solid 47 and first, the interface between cushion 45 is formed by horizontal plane.
The semiconductor device of Fig. 4 is substantially similar to the semiconductor device of Fig. 3, except the V-arrangement interface that the semiconductor device of Fig. 4 includes on stress solid 47 and first between cushion 45.
The semiconductor device of Fig. 5 is substantially similar to the semiconductor device of Fig. 3, except the U-shaped interface that the semiconductor device of Fig. 5 includes on stress solid 47 and first between cushion 45. Present inventive concept is not limited to this. Such as, on stress solid 47 and first, interface between cushion 45 can have the shape of recessed shape or projection.
The semiconductor device of Fig. 6 is substantially similar to the semiconductor device of Fig. 4, except the upper end of the stress solid 47 of Fig. 6 is raised to the horizontal plane higher than the upper end of the first channel region 27.
The semiconductor device of Fig. 7 is substantially similar to the semiconductor device of Fig. 4, except the upper end of the stress solid 47 of Fig. 7 is formed except the horizontal plane place lower than the upper end of the first channel region 27.
Formed on the substrate 21 including PMOS area with reference to Fig. 8, N trap 24, device isolation layer the 25, the 3rd groove 39T3, second cushion the 57, second channel region 58, first grid dielectric layer 62, first gate electrode 64, first grid overlay pattern the 66, second sept 68, drain region 69D, source region 69S, lower insulating barrier 71, upper insulating barrier 81 and contact plunger 83. Second cushion 57 includes cushion 56 on the second bottom breaker 54 and second. The upper end substantially copline of the upper end of the second channel region 58 and the upper end of drain region 69D and source region 69S.
The semiconductor device of Fig. 9 is substantially similar to the semiconductor device of Fig. 8, except interface V-arrangement between cushion 56 on second channel region 58 and second of Fig. 9.
The semiconductor device of Figure 10 is substantially similar to the semiconductor device of Fig. 8, except interface U-shaped between cushion 56 on second channel region 58 and second of Figure 10. Present inventive concept is not limited to this. Such as, on the second channel region 58 and second, interface between cushion 56 can have the shape of recessed shape or projection.
The semiconductor device of Figure 11 is substantially similar to the semiconductor device of Fig. 9, except the upper end of second channel region 58 of Figure 11 is raised to the horizontal plane that the upper end of the upper end than drain region 69D and source region 69S is high.
The semiconductor device of Figure 12 is substantially similar to the semiconductor device of Fig. 9, except the upper end of the second channel region 58 is formed except the horizontal plane place that the upper end of the upper end than drain region 69D and source region 69S is low.
Figure 13 to Figure 16 is the sectional view of the method forming semiconductor device of the illustrative embodiments according to present inventive concept.
With reference to Figure 13, p-well 23, N trap 24 and device isolation layer 25 are formed on the substrate 21 including NMOS area and PMOS area. In some illustrative embodiments, it is convenient to omit p-well 23.
With reference to Figure 14, form multiple groove 39T1,39T2 and 39T3. The plurality of groove 39T1,39T2 and 39T3 include the first groove 39T1, the second groove 39T2 and the three groove 39T3. First groove 39T1 and the second groove 39T2 is formed in p-well 23.First channel region 27 is arranged between the first groove 39T1 and the second groove 39T2. 3rd groove 39T3 is formed in N trap 24.
With reference to Figure 15, the first bottom breaker 43 is formed in the first groove 39T1 and the second groove 39T2. On first, cushion 45 is formed on the first bottom breaker 43. On first bottom breaker 43 and first, cushion 45 constitutes the first cushion 46. Stress solid 47 is formed on the first cushion 46. Ohmic contact layer 49 is formed on stress solid 47.
With reference to Figure 16, the second bottom breaker 54 is formed in the 3rd groove 39T3. On second, cushion 56 is formed on the second bottom breaker 54. On second bottom breaker 54 and second, cushion 56 constitutes the second cushion 57. Second channel region 58 is formed on the second cushion 57.
Referring back to Fig. 1, second gate dielectric layer 74, second gate electrode 77 and second gate overlay pattern 78 are formed on first channel region 27 of Figure 16. First sept 37 is formed on the side surface of second gate electrode 77 and the side surface of second gate overlay pattern 78.
First grid dielectric layer 62, first gate electrode 64 and first grid overlay pattern 66 are formed on second channel region 58 of Figure 16. It is directed at the center vertical of the center of first gate electrode 64 and the second channel region 58. Second sept 68 is formed on the side surface of first gate electrode 64 and the side surface of first grid overlay pattern 66. Drain region 69D and source region 69S is adjacent to first gate electrode 64 and is formed in N trap 24.
Figure 17 to Figure 40 is the sectional view of the method forming semiconductor device for illustrating the illustrative embodiments according to present inventive concept.
With reference to Figure 17, p-well 23, N trap 24 and device isolation layer 25 are formed on the substrate 21 including NMOS area and PMOS area.
Substrate 21 can be the silicon single crystal wafer comprising p type impurity. P-well 23 can include the monocrystal silicon comprising p type impurity. N trap 24 can include the monocrystal silicon comprising N-type impurity. Device isolation layer 25 can utilize shallow trench isolation (STI) method to be formed. Device isolation layer 25 can include insulant, such as Si oxide, silicon nitride, silicon nitrogen oxides or its combination. In other illustrative embodiments, it is convenient to omit p-well 23.
With reference to Figure 18, pad (pad) layer the 31, first mask pattern the 33, second mask pattern 35 and the first sept 37 are formed on the base plate (21.
Bed course 31 can include insulant such as Si oxide. First mask pattern 33 can include the material with the etching selectivity relative to substrate 21. Second mask pattern 35 is formed on the first mask pattern 33. Second mask pattern 35 can include having the material relative to the first mask pattern 33 and the etching selectivity of substrate 21. Such as, the first mask pattern 33 can include polysilicon, and the second mask pattern 35 can include silicon nitride. The technique forming the first mask pattern 33 and the second mask pattern 35 can include film forming technology and Patternized technique. First sept 37 can cover the side surface of the first mask pattern 33 and the side surface of the second mask pattern 35. The technique forming the first sept 37 can include film forming technology and anisotropic etching process. First sept 37 can include silicon nitride, Si oxide, silicon nitrogen oxides or its combination. Such as, the first sept 37 can include silicon nitride.
With reference to Figure 19, by using first mask pattern the 33, second mask pattern 35 and the first sept 37 to remove p-well 23 and N trap 24 as etching masking part, form multiple groove 39T1,39T2 and 39T3.The plurality of groove 39T1,39T2 and 39T3 include the first groove 39T1, the second groove 39T2 and the three groove 39T3. First groove 39T1 and the second groove 39T2 is formed in p-well 23. First channel region 27 is arranged between the first groove 39T1 and the second groove 39T2. 3rd groove 39T3 is formed in N trap 24.
Form the plurality of groove 39T1, the technique of 39T2 and 39T3 can include anisotropic etching process, isotropic etching, directional etch process or its combination. The plurality of groove 39T1,39T2 and 39T3 lower part be V-arrangement. The plurality of groove 39T1,39T2 and 39T3 sidewall be C shape (such as, "<" shape or ">" shape). First channel region 27 is formed in p-well 23. First channel region 27 can include the monocrystal silicon comprising p type impurity. The plurality of groove 39T1,39T2 and 39T3 bottom formed at the horizontal plane place higher than the lower end of device isolation layer 25.
In other illustrative embodiments, the plurality of groove 39T1, each of 39T2 and 39T3 can be U-shapeds.
With reference to Figure 20, formed and cover PMOS area and expose the 3rd mask pattern 42 of NMOS area. First bottom breaker 43 is formed in the first groove 39T1 and the second groove 39T2.
First bottom breaker 43 is formed on the inwall of the first groove 39T1 and the inwall of the second groove 39T2. First bottom breaker 43 can include crystal growth material. First bottom breaker 43 can include the material different from the first channel region 27. Such as, the first bottom breaker 43 can include AlN.
With reference to Figure 21, on first, cushion 45 is formed on the first bottom breaker 43 in the first groove 39T1 and the second groove 39T2. On first bottom breaker 43 and first, cushion 45 constitutes the first cushion 46.
On first, cushion 45 can include crystal growth material. On first, cushion 45 can be optionally formed on the first bottom breaker 43. On first, cushion 45 can include the material different from the first channel region 27. On first, cushion 45 can include AlxGa1-xN (0 < X≤1) grading structure. On first, the Al content in cushion 45 can increase near the bottom of the first groove 39T1 and the second groove 39T2. On first, the upper surface of cushion 45 can be smooth.
Such as, cushion 45 can include the ground floor of order stacking to layer 6 on first. On first, the ground floor of cushion 45 can be AlxGa1-xN (0.7≤x≤1) layer. On first, the second layer of cushion 45 can be AlxGa1-xN (0.5≤X < 0.7) layer and formation are on the first layer. On first, the third layer of cushion 45 can be AlxGa1-xN (0.3≤X < 0.5) layer and formation are on the second layer. On first, the 4th layer of cushion 45 can be AlxGa1-xN (0.1≤X < 0.3) layer and formation are in third layer. On first, the layer 5 of cushion 45 can be AlxGa1-xN (0.05≤x < 0.1) layer and formation are on the 4th layer. On first, the layer 6 of cushion 45 can be AlxGa1-xN (0 < x < 0.05) layer and formation are on layer 5.
With reference to Figure 22, it is shown that the optional structure of cushion 45 on first. In fig. 22, the upper surface of cushion 45 is V-arrangement on first. Process conditions may be controlled so that on first, the upper surface of cushion 45 is V-arrangement.
With reference to Figure 23, it is shown that the optional structure of cushion 45 on first. In fig 23, the upper surface of cushion 45 is U-shaped on first. Process conditions may be controlled so that on first, the upper surface of cushion 45 is U-shaped.Present inventive concept is not limited to this, and on first, the upper surface of cushion 45 can have the shape of recessed shape or projection.
With reference to Figure 24, stress solid 47 can be formed on the first cushion 46 in the first groove 39T1 and the second groove 39T2 of Figure 21. Present inventive concept is not limited to this, and stress solid 47 can be formed on first cushion 46 of Figure 22 to Figure 23.
Stress solid 47 can include crystal growth material. Stress solid 47 can include the material of the lattice paprmeter different from the first channel region 27. Stress solid 47 can include the material with the lattice paprmeter less than the first channel region 27. Such as, stress solid 47 can include GaN. Stress solid 47 is filled up completely with the first groove 39T1 and the second groove 39T2. The upper end substantially copline of the upper end of stress solid 47 and the first channel region 27.
Alternatively, the stress solid of Figure 25 is formed so that stress solid 47 is filled up completely with the upper end of the first groove 39T1 and stress solid 47 and is raised to the horizontal plane higher than the upper end of the first channel region 27.
Alternatively, the stress solid of Figure 26 is formed so that the upper end lower than the first channel region 27, the upper end of stress solid 47.
With reference to Figure 27, ohmic contact layer 49 is formed on the stress solid 47 of Figure 24. Present inventive concept is not limited to this, and ohmic contact layer 49 can be formed on the stress solid 47 of Figure 25 and Figure 26. The upper end of ohmic contact layer 49 is higher than the upper end of the first channel region 27. Ohmic contact layer 49 can include InGaN, metal silicide, Si or its combination. Ohmic contact layer 49 contacts with the side surface of the first sept 37.
With reference to Figure 28, remove the 3rd mask pattern 42, and form the 4th mask pattern 51 covering NMOS area and exposure PMOS area. Second bottom breaker 54 is formed in the 3rd groove 39T3.
Second bottom breaker 54 is formed along the inwall of the 3rd groove 39T3. Second bottom breaker 54 can include crystal growth material. Second bottom breaker 54 can include the material identical with N trap 24. Such as, the second bottom breaker 54 can include the Si layer of crystal growth. The bottom of the second bottom breaker 54 is V-arrangement. The side surface of the second bottom breaker 54 is C shape (such as, "<" shape or ">" shape).
With reference to Figure 29, on second, cushion 56 is formed on the second bottom breaker 54 in the 3rd groove 39T3. On second bottom breaker 54 and second, cushion 56 constitutes the second cushion 57.
On second, cushion 56 can include crystal growth material. On second, cushion 56 can be optionally formed on the second bottom breaker 54. On second, cushion 56 can include the material different from N trap 24. On second, cushion 56 can include SiyGe1-y(0 < y≤1) grading structure. On second, the Ge content in cushion 56 can reduce near the bottom of the 3rd groove 39T3.
Such as, cushion 56 can include the ground floor of order stacking to layer 6 on second. On second, the ground floor of cushion 56 can be SiyGe1-y(0.7≤y < 1) layer. On second, the second layer of cushion 56 can be SiyGe1-y(0.5≤y < 0.7) layer and formation are on the first layer. On second, the third layer of cushion 56 can be SiyGe1-y(0.3≤y < 0.5) layer and formation are on the second layer. On second, the 4th layer of cushion 56 can be SiyGe1-y(0.1≤y < 0.3) layer and formation are in third layer. On second, the layer 5 of cushion 56 can be SiyGe1-y(0.05≤y < 0.1) layer and formation are on the 4th layer. On second, the layer 6 of cushion 56 can be SiyGe1-y(0 < y < 0.05) layer and formation are on layer 5.
Alternatively, on the second of Figure 30, the formation of cushion 56 may be controlled so that on second, the upper surface of cushion 56 can be V-arrangement.
Alternatively, on the second of Figure 31, the formation of cushion 56 may be controlled so that on second, the upper surface of cushion 56 is U-shaped. Present inventive concept is not limited to this, and on second, the upper surface of cushion 56 can have the shape of recessed shape or projection.
With reference to Figure 32, the second channel region 58 is formed on the second cushion 57 in the 3rd groove 39T3 of Figure 29. Second channel region 58 can include the semi-conducting material different from N trap 24. Second channel region 58 can include crystal growth material. Second channel region 58 can include the material with hole mobility higher compared with silicon. Such as, the second channel region 58 can include the Ge layer that comprises N-type impurity. Second channel region 58 can be filled up completely with the 3rd groove 39T3. The upper end of the second channel region 58 and the upper end copline of N trap 24.
Alternatively, second channel region 58 of Figure 33 is formed so that the upper end of the second channel region 58 is raised to the horizontal plane higher than the upper end of N trap 24.
Alternatively, second channel region 58 of Figure 34 is formed so that the upper end lower than N trap 24, the upper end of the second channel region 58.
With reference to Figure 35, it is arranged on bed course the 31, first mask pattern the 33, second mask pattern 35 in the PMOS area of Figure 32 and the first sept 37 is removed. N trap 24 and the second channel region 58 are exposed.
With reference to Figure 36, first grid dielectric layer 62, first gate electrode 64, first grid overlay pattern 66 and the second sept 68 are formed on the second channel region 58. Drain region 69D and source region 69S is formed in N trap 24.
First grid dielectric layer 62 can include silicon nitride, Si oxide, silicon nitrogen oxides, high-k dielectric or its combination. First gate electrode 64 can include metal, metal nitride, metal-oxide, metal silicide, polysilicon, conductive carbon or its combination. First grid overlay pattern 66 can include Si oxide, silicon nitride, silicon nitrogen oxides or its combination. Second sept 68 can include Si oxide, silicon nitride, silicon nitrogen oxides or its combination. Drain region 69D and source region 69S can be formed in N trap 24 by being injected into by p type impurity.
With reference to Figure 37, remove the 4th mask pattern 51, and form the lower insulating barrier 71 covering substrate 21. Lower insulating barrier 71 can include Si oxide, silicon nitride, silicon nitrogen oxides, low K dielectrics or its combination.
With reference to Figure 38, lower insulating barrier 71 is flattened to expose the first mask pattern 33. Second mask pattern 35 is removed.
With reference to Figure 39, the first mask pattern 33 and bed course 31 are removed to form gate trench 72T. First channel region 27 is exposed by gate trench 72T.
With reference to Figure 40, on second time gate dielectric layer 73, second, gate dielectric layer 74, second gate electrode 77 and second gate overlay pattern 78 are formed in gate trench 72T. Second gate electrode 77 includes lower gate electrode 75 and upper gate electrode 76.
Second time gate dielectric layer 73 can include Si oxide. Second time gate dielectric layer 73 can be referred to as interfacial oxide or chemical oxide. Second time gate dielectric layer 73 can pass through H2O2Formed with the chemical reaction of Si. Second time gate dielectric layer 73 can be formed on the first channel region 27. Second time gate dielectric layer 73 contacts with the first channel region 27.On second, gate dielectric layer 74 is around the side surface of second gate electrode 77 and bottom. On second, gate dielectric layer 74 is plugged between second time gate dielectric layer 73 and second gate electrode 77. On second, gate dielectric layer 74 can include Si oxide, silicon nitride, silicon nitrogen oxides, high-k dielectric or its combination.
Lower gate electrode 75 is around the side surface of upper gate electrode 76 and bottom. Lower gate electrode 75 can include conductive layer to adjust work function. Upper gate electrode 76 can include metal, metal nitride, metal-oxide, metal silicide, polysilicon, conductive carbon or its combination. Second gate electrode 77 can be referred to as replacement gate. Second gate overlay pattern 78 can include Si oxide, silicon nitride, silicon nitrogen oxides or its combination. Such as, second gate overlay pattern 78 can include silicon nitride.
Referring back to Fig. 2, upper insulating barrier 81 is formed on the lower insulating barrier 71 of Figure 40. Form the contact plunger 83 through upper insulating barrier 81 and lower insulating barrier 71. Upper insulating barrier 81 can include Si oxide, silicon nitride, silicon nitrogen oxides or its combination. Contact plunger 83 can include metal level, metal nitride layer, metal oxide layer, metal silicide layer, polysilicon layer or its combination.
Figure 41 and Figure 42 is the system block diagram of the electronic system of the illustrative embodiments according to present inventive concept.
With reference to Figure 41, can apply to electronic system 2100 according to the semiconductor device of illustrative embodiments. Electronic system 2100 includes main body 2110, microprocessor 2120, power unit 2130, functional unit 2140 and display controller 2150. Main body 2110 can be the mainboard formed by printed circuit board (PCB) (PCB). Microprocessor 2120, power unit 2130, functional unit 2140 and display controller 2150 may be mounted in main body 2110. Display 2160 can be arranged on main body 2110 interiorly or exteriorly. Such as, display 2160 is arranged on the surface of main body 2110 and shows the image processed by display controller 2150.
Power unit 2130 can receive constant voltage from external cell etc., this voltage division becomes the varying level of required voltage, and those voltages are fed to microprocessor 2120, functional unit 2140 and display controller 2150 etc. Microprocessor 2120 can receive voltage to control functional unit 2140 and display 2160 from power unit 2130. Functional unit 2140 can perform the various functions of electronic system 2100. Such as, when electronic system 2100 is smart mobile phone, functional unit 2140 can have and performs the function of mobile phone by dialling or communicate with external device (ED) 2170 and such as export image and to display 2160 or export the sound several parts to speaker. When being mounted with photographing unit, functional unit 2140 can serve as camera images processor.
If electronic system 2100 is connected to storage card etc. to increase its capacity, then functional unit 2140 can serve as memory card controller. Functional unit 2140 can exchange signal by wired or wireless communication unit 2180 with external device (ED) 2170. Additionally, when electronic system 2100 needs USB (universal serial bus) (USB) etc. thus during extended functionality, functional unit 2140 can serve as interface controller. Additionally, functional unit 2140 can include mass storage device.
Semiconductor device according to illustrative embodiments can apply to functional unit 2140 or microprocessor 2120.Such as, microprocessor 2120 can include first cushion 46 and second cushion 57 of Fig. 1 to Figure 40.
With reference to Figure 42, electronic system 2400 can include the semiconductor device of the illustrative embodiments according to present inventive concept. Electronic system 2400 can be included in mobile device or computer. Such as, electronic system 2400 includes accumulator system 2412, microprocessor 2414, random access memory (RAM) 2416, bus 2420 and user interface 2418. Microprocessor 2414, accumulator system 2412 and user interface 2418 can be connected to each other via bus 2420. User interface 2418 may be used for inputting data into electronic system 2400 or exporting data from electronic system 2400. Microprocessor 2414 can program and control electronic system 2400. RAM2416 can serve as the run memory of microprocessor 2414. Microprocessor 2414, RAM2416 and/or other parts can assembled in a single package. Accumulator system 2412 can store the code for operating microprocessor 2414, microprocessor 2414 data processed or outer input data. Accumulator system 2412 can include controller and memory device.
The semiconductor device of the illustrative embodiments according to present inventive concept can apply to microprocessor 2414, RAM2416 and accumulator system 2412.
Illustrative embodiments according to present inventive concept, stress solid can be formed on the first cushion in NMOS area. Stress solid can apply tensile stress to the first channel region, such that it is able to improve electron mobility. First cushion may be used for preventing from cracking in stress solid. Second channel region can be formed on the second cushion in PMOS area. Second channel region can be subject to compressive stress, such that it is able to improve hole mobility. Second cushion may be used for preventing generation crystal growth defect in the second channel region. According to illustrative embodiments, semiconductor device can due to the mobility of electronics and/or the increase of holoe carrier fast operating.
Although the illustrative embodiments with reference to the present invention illustrate and describes the present invention, but those of ordinary skill in the art be will be apparent from, can wherein carrying out the various changes in form and details without departing from the spirit and scope of the present invention, the scope of the present invention is defined by the claims. Such as, present inventive concept can be applied to finFET (field-effect transistor), nano-wire transistor or three-dimensional transistor with extending.

Claims (25)

1. a semiconductor device pieces, including:
Substrate, including NMOS area and PMOS area;
First groove and the second groove, be arranged in described NMOS area;
First cushion, is arranged in described first groove and described second groove;
Stress solid, is arranged in described first groove and described second groove and is arranged on described first cushion;
First channel region, is arranged between described first groove and described second groove and is arranged in described substrate;
First gate electrode, is arranged on described first channel region;
3rd groove, is arranged in described PMOS area;
Second cushion, is arranged in described 3rd groove;
Second channel region, is arranged in described 3rd groove, is arranged on described second cushion, and has the semi-conducting material different from described substrate; And
Second gate electrode, is arranged on described second channel region.
2. semiconductor device according to claim 1, wherein said stress solid includes the material with the lattice paprmeter less than described first channel region.
3. semiconductor device according to claim 2, wherein said first channel region includes Si and described stress solid includes GaN.
4. semiconductor device according to claim 2, wherein said first cushion includes AlxGa1-xN (0 < x≤1) grading structure, wherein Al content up reduces towards described stress solid.
5. semiconductor device according to claim 4, wherein said first cushion includes:
First bottom breaker; With
Cushion on first, is arranged on described first bottom breaker,
Wherein said first bottom breaker includes AlN.
6. semiconductor device according to claim 5, wherein said stress solid and on described first interface between cushion be level, recessed or projection.
7. semiconductor device according to claim 1, the upper surface of wherein said stress solid higher or lower than the upper surface of described first channel region, or with the upper surface copline of described first channel region.
8. semiconductor device according to claim 1, also includes the ohmic contact layer being arranged on described stress solid.
9. semiconductor device according to claim 8, wherein said ohmic contact layer includes InGaN or metal silicide.
10. semiconductor device according to claim 1, the lower part of wherein said first groove, described second groove and described 3rd groove is V-arrangement.
11. semiconductor device according to claim 1, the sidewall of wherein said first groove, described second groove and described 3rd groove is C shape.
12. semiconductor device according to claim 1, wherein said substrate includes Si and described second channel region includes Ge.
13. semiconductor device according to claim 1, wherein said second cushion includes SiyGe1-y(0 < y≤1) grading structure, wherein Ge content up increases towards described second channel region.
14. semiconductor device according to claim 13, wherein said second cushion includes:
Second bottom breaker; With
Cushion on second, is arranged on described second bottom breaker,
Between the sidewall that wherein said second bottom breaker includes epitaxial si layer and described second bottom breaker is plugged on described second cushion and described 3rd groove.
15. semiconductor device according to claim 14, on wherein said second channel region and described second, the interface between cushion is level, recessed or projection.
16. a semiconductor device, including:
First groove and the second groove, arranged in a substrate;
Channel region, is arranged between described first groove and described second groove and in described substrate;
Gate electrode, is arranged on described channel region;
Cushion, is arranged in described first groove and described second groove; And
Stress solid, is arranged in described first groove and described second groove and is arranged on described cushion.
17. semiconductor device according to claim 16, wherein said stress solid includes the material with the lattice paprmeter less than described channel region.
18. semiconductor device according to claim 16, wherein said cushion includes the element different from described channel region and described stress solid, and
The content of the described different element of described cushion reduces near described stress solid.
19. semiconductor device according to claim 18, wherein said different element includes aluminum (Al).
20. a semiconductor device, including:
Drain region and source region, arranged in a substrate;
Groove, is arranged between described drain region and described source region and is arranged in described substrate;
Cushion, is arranged in the trench;
Channel region, arranges in the trench, is arranged on described cushion, and has the semi-conducting material different from described drain region and described source region; And
Gate electrode, is arranged on described channel region.
21. semiconductor device according to claim 20, wherein said drain region and described source region include Si layer, and described channel region includes Ge.
22. semiconductor device according to claim 20, wherein said cushion includes SiyGe1-y(0 < y≤1) grading structure, wherein Ge content up increases towards described second channel region.
23. a semiconductor device, including:
First trap and the second trap, arranged in a substrate, and wherein said first trap and described second trap are isolated from each other by device isolation layer;
First groove and the second groove, be arranged in described first trap;
First channel region, is arranged between described first groove and described second groove and is arranged in described substrate;
First gate electrode, is arranged on described first channel region;
3rd groove, is arranged in described second trap;
Second channel region, is arranged in described 3rd groove, and wherein said second channel region is formed by the semi-conducting material different from described second trap; And
Second gate electrode, is arranged on described second channel region.
24. semiconductor device according to claim 23, wherein said first trap p type impurity doping, described second trap N-type impurity is adulterated.
25. semiconductor device according to claim 23, also include:
First cushion, is arranged in described first groove and described second groove;
Stress solid, is arranged in described first groove and described second groove and is arranged on described first cushion; And
Second cushion, is arranged in described 3rd groove and below described second channel region,
Wherein said first cushion includes AlxGa1-xN (0 < X≤1), and the Al content of described first cushion up reduces towards described stress solid, and
Wherein said second cushion includes SiyGe1-y(0 < y≤1), and the Ge content of described second cushion up increases towards described second channel region.
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