CN113745346B - Semiconductor device with double-gate structure, manufacturing method thereof and electronic equipment - Google Patents

Semiconductor device with double-gate structure, manufacturing method thereof and electronic equipment Download PDF

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CN113745346B
CN113745346B CN202111000215.XA CN202111000215A CN113745346B CN 113745346 B CN113745346 B CN 113745346B CN 202111000215 A CN202111000215 A CN 202111000215A CN 113745346 B CN113745346 B CN 113745346B
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layer
gate stack
gate
semiconductor device
channel
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CN113745346A (en
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202111000215.XA priority Critical patent/CN113745346B/en
Priority to CN202410508592.1A priority patent/CN118431296A/en
Priority to KR1020247008498A priority patent/KR20240038822A/en
Priority to PCT/CN2021/133509 priority patent/WO2023024299A1/en
Publication of CN113745346A publication Critical patent/CN113745346A/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device having a dual gate structure, a method of manufacturing the same, and an electronic apparatus including the semiconductor device are disclosed. According to an embodiment, a semiconductor device may include: a vertical channel portion on the substrate; source/drain portions at upper and lower ends of the channel portion, respectively, with respect to the substrate; and a first gate stack on a first side of the channel portion in a first direction transverse to the substrate and a second gate stack on a second side of the channel portion opposite the first side in the first direction. The distance between at least one of the upper and lower edges of the first gate stack near the one end of the channel portion in the vertical direction and the corresponding source/drain portion may be smaller than the distance between at least one of the upper and lower edges of the second gate stack near the one end of the channel portion in the vertical direction and the corresponding source/drain portion.

Description

Semiconductor device with double-gate structure, manufacturing method thereof and electronic equipment
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device having a dual gate structure, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
Background
With the continued miniaturization of semiconductor devices, devices of various structures such as fin field effect transistors (finfets), multi-bridge channel field effect transistors (MBCFET), and the like have been proposed. There is still room for improvement in these devices due to device structure limitations in terms of increasing integration density and enhancing device performance.
In addition, it is difficult for vertical nanoplatelet or nanowire devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to control the thickness or diameter of the nanoplatelets or nanowires due to process fluctuations such as photolithography and etching. Also, it is difficult to reduce Gate Induced Drain Leakage (GIDL). For example, for an n-type MOSFET, to reduce leakage current between the source and drain, a negative bias Vgs (< 0) may be applied between the gate and source. However, if |vgs| is too large, GIDL may be caused. Therefore, GIDL becomes a limiting factor for reducing leakage.
Disclosure of Invention
In view of the above, it is an object of the present disclosure, at least in part, to provide a semiconductor device having a dual gate structure, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
According to an aspect of the present disclosure, there is provided a semiconductor device including: a vertical channel portion on the substrate; source/drain portions at upper and lower ends of the channel portion, respectively, with respect to the substrate; and a first gate stack on a first side of the channel portion in a first direction transverse to the substrate and a second gate stack on a second side of the channel portion opposite the first side in the first direction. The distance between at least one of the upper and lower edges of the first gate stack near the one end of the channel portion in the vertical direction and the corresponding source/drain portion may be smaller than the distance between at least one of the upper and lower edges of the second gate stack near the one end of the channel portion in the vertical direction and the corresponding source/drain portion.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a stack of a first material layer, a second material layer and a third material layer on a substrate, the stack having a first side and a second side opposite each other in a first direction transverse to the substrate; recessing the sidewalls of the second material layer in a first direction relative to the sidewalls of the first material layer and the third material layer on the first side and the second side, thereby defining a first recessed portion; further etching the first material layer, the second material layer and the third material layer on the first side and the second side to increase the size of the first concave part in the vertical direction; forming a channel layer in the first recess; forming a first gate stack in the first recess portion in which the channel layer is formed; forming a stripe-shaped opening in the stack extending in a second direction transverse to the substrate, the second direction intersecting the first direction, thereby dividing the stack into two portions at a first side and a second side, respectively; the second material layer is removed through the opening, and a second gate stack is formed in a space released due to the removal of the second material layer, wherein a dimension of the first gate stack in a vertical direction is greater than a dimension of the second gate stack in the vertical direction.
According to another aspect of the present disclosure, there is provided an electronic apparatus including the above semiconductor device.
According to embodiments of the present disclosure, a first gate stack and a second gate stack may be formed on opposite sides of a channel portion, respectively. At least one side in the vertical direction, respective edges of the first gate stack and the second gate stack may be offset with respect to each other to suppress GIDL.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:
Fig. 1 to 21 (b) schematically show some stages in a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure, in which: fig. 5 (a), 6 (a), 21 (a) are plan views, wherein the positions of AA ' and CC ' lines are shown in fig. 5 (a), and the positions of BB ' lines are shown in fig. 6 (a); fig. 1 to 4, 5 (b), 6 (b), 7 to 9, 10 (a), 10 (b), 11 to 14, 15 (a), 16, 17 (a), 18 (a), 20 (a), 21 (b) are sectional views along line AA'; FIG. 6 (c) is a cross-sectional view taken along line BB'; FIGS. 5 (c), 6 (d) are cross-sectional views taken along line CC'; 15 (b), 17 (b), 18 (b), 19, 20 (b) are cross-sectional views taken along line DD 'in the respective cross-sectional views, wherein the location of the DD' line is shown in FIG. 15 (b);
Fig. 22 (a) and 22 (b) show the energy band diagrams of the n-type device according to the comparative example and the n-type device according to the embodiment of the present invention, respectively;
Fig. 23 (a) to 24 (b) schematically illustrate some stages in a process of manufacturing a semiconductor device according to another embodiment of the present disclosure, in which fig. 23 (a), 23 (b), 24 (a) and 24 (b) are each a cross-sectional view along line AA';
Fig. 25 to 26 schematically illustrate some stages in a process of manufacturing a semiconductor device according to another embodiment of the present disclosure, wherein fig. 25 and 26 are each a cross-sectional view along line AA';
fig. 27 (a) and 27 (b) show energy band diagrams of n-type devices according to other embodiments of the present disclosure, respectively.
The same or similar reference numbers will be used throughout the drawings to refer to the same or like parts.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
According to an embodiment of the present disclosure, a vertical semiconductor device is provided having an active region disposed vertically (e.g., in a direction substantially perpendicular to a surface of a substrate) on the substrate. The channel portion may be a vertical nano-sheet or nano-wire, such as a curved nano-sheet or nano-wire having a C-shaped cross-section (e.g., a cross-section perpendicular to the substrate surface), and thus such a device may be referred to as a C-channel field effect transistor (C-CHANNEL FET, i.e., CCFET). As described below, the nanoplatelets or nanowires may be formed by epitaxial growth, and thus may be a unitary monolithic piece, and may have a substantially uniform thickness. The channel portion may have strain or stress in the vertical direction. Due to such strain, the lattice constant of the material of the channel portion is different from the lattice constant of the material when unstrained.
The semiconductor device may further include source/drain portions provided at upper and lower ends of the channel portion, respectively. The source/drain may have some doping. For example, for a p-type device, the source/drain may have p-type doping; for n-type devices, the source/drain may have n-type doping. The channel portion may have some doping to adjust the threshold voltage of the device. Or the semiconductor device may be a junction-free device in which the channel portion and the source/drain portion may have the same conductivity type doping. Or the semiconductor device may be a tunneling device in which source/drain portions at both ends of a channel portion may have doping types opposite to each other.
The source/drain portions may be disposed in the respective semiconductor layers. For example, the source/drain may be doped regions in the respective semiconductor layers. The source/drain may be part or all of the corresponding semiconductor layer. In case the source/drain is part of the respective semiconductor layer, a doping concentration interface may exist between the source/drain and the rest of the respective semiconductor layer. The source/drain portions may be formed by diffusion doping, as described below. In this case, the doping concentration interface may be substantially along a vertical direction with respect to the substrate.
The channel portion may comprise a single crystal semiconductor material. Of course, the source/drain portions or the semiconductor layer in which they are formed may also include a single crystal semiconductor material. For example, they may all be formed by epitaxial growth.
The semiconductor device may further include first and second gate stacks disposed on opposite sides of the channel portion in a lateral direction, respectively. The edges of at least one side of the first gate stack and the second gate stack in the vertical direction may have an offset with respect to each other. For example, a distance between at least one of an upper edge and a lower edge of the first gate stack near the channel portion in the vertical direction and the corresponding source/drain portion is smaller than a distance between at least one of the upper edge and the lower edge of the second gate stack near the channel portion in the vertical direction and the corresponding source/drain portion. This helps to suppress GIDL.
Such a semiconductor device can be manufactured, for example, as follows.
According to an embodiment, a stack of a first material layer, a second material layer and a third material layer may be provided on a substrate. The first material layer may define the location of the lower source/drain, the second material layer may define the location of the gate stack, and the third material layer may define the location of the upper source/drain. The first material layer may be provided by a substrate, for example, an upper portion of the substrate, and the second material layer and the third material layer may be sequentially formed on the first material layer by, for example, epitaxial growth. Alternatively, the first material layer, the second material layer, and the third material layer may be sequentially formed on the substrate by, for example, epitaxial growth.
A semiconductor device may be fabricated based on the stack. The stack may include first and second sides opposite each other in a first direction and third and fourth sides opposite each other in a second direction that intersects (e.g., is perpendicular to) the first direction. For example, the stack may be quadrilateral in plan view, such as rectangular or square.
Sidewalls of the second material layer may be recessed in a first direction relative to sidewalls of the first material layer and the third material layer at the first side and the second side of the stack, thereby defining a first recess to define a space for the first gate stack. The first concave portion may have a curved surface concave toward the inner side of the stack. A channel portion may be formed on a surface of the first concave portion. For example, the first active layer may be formed by epitaxial growth on the exposed surface of the stack, and a portion of the first active layer on the surface of the first concave portion may serve as a channel portion (may also be referred to as a "channel layer"). One device may be formed based on the first active layer on the sidewalls of the first and second sides of the stack, respectively. Thus, two devices can be formed opposite to each other based on a single stack. The first gate stack may be formed in the first recess in which the channel layer is formed.
The first concave portion may be formed such that a dimension of the first concave portion in the vertical direction may be different (e.g., greater) than a thickness of the second material layer in the vertical direction after the first active layer is formed. In this way, the first gate stack and the second gate stack having different gate lengths can be fabricated.
Source/drain portions may be formed in the first material layer and the third material layer. For example, the source/drain portion may be formed by doping the first material layer and the third material layer. Such doping may be achieved by a solid phase dopant source layer. In forming the source/drain portion, a first position maintaining layer may be formed in the first concave portion in which the channel layer is formed, so as not to affect the channel layer.
An opening may be formed in the stack to separate the active regions of the two devices. The opening may extend in the second direction such that the stack is divided into two parts at the first side and the second side, respectively, the two parts having respective channel layers. Through which opening the second material layer may be replaced with a second gate stack.
Before the first concave portion is formed at the first side and the second side, a second concave portion may be similarly formed at the third side and the fourth side and a second position maintaining layer may be formed therein. This helps to improve the topography and dimensional control of the channel layer.
According to the embodiments of the present disclosure, the thickness of the nanoplatelets or nanowires used as the channel portion and the gate length are mainly determined by epitaxial growth, not by etching or photolithography, and thus can have good channel size/thickness and gate length control.
The present disclosure may be presented in various forms, some examples of which are described below. In the following description, reference is made to the selection of various materials. The choice of material takes into account etch selectivity in addition to its function (e.g., semiconductor material for forming the active region, dielectric material for forming the electrical isolation). In the following description, the desired etch selectivity may or may not be indicated. It will be apparent to those skilled in the art that when etching a layer of a material is referred to below, such etching may be selective if other layers are not referred to or are not shown and the layer of material may be etch selective with respect to other layers exposed to the same etch recipe.
Fig. 1 to 21 (b) schematically show some stages in a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.
As shown in fig. 1, a substrate 1001 (an upper portion of which may constitute the first material layer described above) is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, bulk Si substrates are described as an example for convenience of explanation. Here, a silicon wafer is provided as the substrate 1001.
In the substrate 1001, a well region may be formed. The well region may be an n-type well if a p-type device is to be formed; the well region may be a p-type well if an n-type device is to be formed. The well region may be formed, for example, by implanting a corresponding conductivity type dopant (P-type dopant such As B or In, or n-type dopant such As or P) into the substrate 1001 and then performing thermal annealing. There are various ways in the art to provide such well regions, and they are not described in detail herein.
On the substrate 1001, a second material layer 1003 and a third material layer 1005 may be formed by, for example, epitaxial growth. The second material layer 1003 may be used to define the location of the gate stack, for example, to a thickness of about 20nm-50nm. The third material layer 1005 may be used to define the location of the upper source/drain regions, for example, having a thickness of about 20nm-200nm.
Adjacent ones of the above layers formed over and on substrate 1001 may have etch selectivity with respect to each other. For example, where the substrate 1001 is a silicon wafer, the second material layer 1003 may include SiGe (e.g., about 10% -30% Ge atomic percent), and the third material layer 1005 may include Si.
The lateral directions x, z and the vertical direction y are schematically shown in fig. 1. The x, z directions may be parallel to the top surface of the substrate 1001 and may be perpendicular to each other; the y-direction may be substantially perpendicular to the top surface of the substrate 1001. Since the top is not constrained, stress in the y-direction in the second material layer 1003 can be released. The x-direction may be the first direction and the z-direction may be the second direction.
According to an embodiment, a spacer pattern transfer technique is used in the following patterning. To form the partition wall, a mandrel pattern (mandril) may be formed. For example, as shown in fig. 2, a layer 1011 for the mandrel pattern may be formed on the third material layer 1005 by, for example, deposition. For example, the layer 1011 for the mandrel pattern may include amorphous silicon or polycrystalline silicon having a thickness of about 50nm to 150nm. In addition, for better etch control, the etch stop layer 1009 may be formed first, for example, by deposition. For example, the etch stop layer 1009 may comprise an oxide (e.g., silicon oxide) having a thickness of about 1nm-10nm.
On the layer 1011 for the mandrel pattern, a hard mask layer 1013 may be formed by, for example, deposition. For example, the hard mask layer 1013 may comprise nitride (e.g., silicon nitride) having a thickness of about 30nm-100nm.
The layer 1011 for the mandrel pattern may be patterned into the mandrel pattern.
For example, as shown in fig. 3, a photoresist 1007 may be formed on the hard mask layer 1013 and patterned into a stripe extending in the z-direction by photolithography. The photoresist 1007 may be used as an etching mask, and the hard mask layer 1013 and the layer 1011 for the mandrel pattern may be sequentially selectively etched by, for example, reactive Ion Etching (RIE), to transfer the photoresist pattern into the hard mask layer 1013 and the layer 1011 for the mandrel pattern. RIE may be performed in a generally vertical direction and may be stopped at etch stop layer 1009. Thereafter, the photoresist 1007 may be removed.
As shown in fig. 4, partition walls 1017 may be formed on sidewalls of opposite sides of the core pattern 1011 in the x-direction. For example, a layer of nitride having a thickness of about 10nm-100nm may be deposited in a substantially conformal manner, and then the deposited nitride layer may be anisotropically etched in a vertical direction, such as RIE (which may be performed in a substantially vertical direction and may stop at the etch stop layer 1009), to remove the laterally extending portions thereof and leave the vertically extending portions thereof, thereby obtaining the partition walls 1017. The partition 1017 may then be used to define the location of the device active region.
The mandrel pattern formed as described above and the sidewall 1017 formed on the sidewall thereof extend in the z-direction. They may be limited in their extent in the z-direction and thus define the extent of the device active region in the z-direction.
As shown in fig. 5 (a) to 5 (c), a photoresist 1015 may be formed on the structure shown in fig. 4 and patterned by photolithography to occupy a certain range in the z-direction, for example, a stripe extending along the x-direction. Photoresist 1015 may be used as an etch mask to selectively etch the underlying layers in sequence, for example, by RIE. Etching may be performed into the substrate 1001, and in particular the well region therein, thereby forming a recess in the substrate 1001. Isolation, such as Shallow Trench Isolation (STI), may then be formed in the formed recess. Thereafter, the photoresist 1015 may be removed.
As shown in fig. 5 (c), the side wall of the second material layer 1003 in the z-direction is currently exposed to the outside.
According to an embodiment of the present disclosure, to avoid affecting the sidewalls of the second material layer 1003 in the z-direction when the sidewalls in the x-direction are processed (to form recesses and form channel layers in the recesses formed as described below), the sidewalls of the second material layer 1003 in the z-direction may be masked.
For example, as shown in fig. 6 (a) to 6 (d), the second material layer 1003 may be selectively etched so that the side wall thereof in the z direction is relatively recessed to form a recessed portion. To better control the amount of etching, atomic Layer Etching (ALE) may be used. For example, the amount of etching may be about 5nm to 20nm. The sidewalls of the second material layer 1003 after etching may take different shapes depending on the nature of the etching, e.g. the etch selectivity of the second material layer 1003 with respect to the substrate 1001 and the third material layer 1005. In fig. 6 (d), the side wall of the second material layer 1003 after etching is shown to be C-shaped recessed inward. The present disclosure is not limited thereto. For example, where the etch selectivity is good, the sidewalls of the second material layer 1003 may be nearly vertical after etching. The etching can be isotropic, in particular when a large etching quantity is required. In the recess thus formed, a dielectric material may be filled. This filling can be done by deposition and then etch back. For example, a dielectric material, such as an oxide, may be deposited on the substrate sufficient to fill the recess, and then the deposited dielectric material may be etched back, such as by RIE. In this way, the dielectric material may remain in the concave portion to form the first position-maintaining layer 1019. The deposited dielectric material may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) prior to etch back (CMP may be stopped at the hard mask layer 1013).
According to embodiments of the present disclosure, a thickness of dielectric material may be left on the substrate 1001 when etched back to form the protective layer 1021. Here, the protective layer 1021 may be in a groove of the substrate 1001, a top surface of which is lower than a top surface of the substrate 1001. In addition, during the etching back, a portion of the etching stop layer 1009 (in this example, oxide as well) exposed to the outside may also be etched.
The protective layer 1021 may protect the surface of the substrate 1001 in the following process. For example, in this example, the extent of the active region in the z-direction is first defined. Subsequently, the extent of the active region in the x-direction will be defined. The protective layer 1021 can also avoid an influence on the surface of the substrate that is currently exposed to the outside in the groove (see fig. 5 (c)) when the range in the x-direction is defined. In addition, in the case where different types of well regions are formed in the substrate 1001, the protective layer 1021 can protect pn junctions between the different types of well regions from being damaged by etching.
As shown in fig. 7, the third material layer 1005, the second material layer 1003, and the upper portion (first material layer) of the substrate 1001 may be patterned into a ridge structure (in fact, the range of the ridge structure in the z-direction has been defined by the above-described process) using the hard mask layer 1013 and the partition 1017. For example, the hard mask layer 1013 and the partition 1017 may be used as etching masks, and the layers may be sequentially selectively etched by, for example, RIE to transfer a pattern into the underlying layer. Thus, the upper portion of the substrate 1001, the second material layer 1003, and the third material layer 1005 may form a ridge structure. As described above, due to the presence of the protective layer 1021, etching may not affect the portions of the substrate 1001 on both sides of the ridge structure in the z-direction.
Here, etching may be into the well region of the substrate 1001. The extent of etching into the substrate 1001 may be substantially the same or similar to the extent of etching into the substrate 1001 described above in connection with fig. 5 (a) to 5 (c). Likewise, a groove is formed in the substrate 1001. And a protective layer may also be formed in these grooves, for example by depositing, planarizing and then etching back oxide (see 1023 in fig. 8). The protective layer 1023 surrounds the periphery of the ridge structure along with the previous protective layer 1021. In this way, similar processing conditions may be provided around the ridge structure, i.e. both are grooves formed in the substrate 1001, in which grooves the protective layers 1021, 1023 are formed.
Space for the gate stack may be left at both ends of the second material layer in the x-direction. For example, as shown in fig. 8, the second material layer 1003 may be selectively etched so that its sidewalls in the x-direction are relatively recessed to form recesses (spaces for gate stacks may be defined). ALE may be used for better control of the amount of etching. For example, the amount of etching may be about 10nm-40nm. As described above, the sidewall of the second material layer 1003 after etching may take on a C-shape recessed inward. The etching can be isotropic, in particular when a large etching quantity is required. Generally, the C-shaped sidewall of the second material layer 1003 has a larger curvature at the upper and lower ends and a smaller curvature at the waist or middle. Of course, the side walls may also be nearly vertical.
A first active layer may be formed on the sidewalls of the ridge structure to subsequently define the channel portion. In order to offset edges of at least one side in the vertical direction with respect to each other when the gate stack is subsequently formed on both left and right sides of the channel portion, as shown in fig. 9, the ridge structure (specifically, exposed surfaces of the first material layer, the second material layer, and the third material layer) may be etched back, and thus the peripheral side walls thereof may be laterally recessed with respect to the peripheral side walls of the partition walls 1017. ALE may be used to control the etch depth. The etch depth may be, for example, about 10nm-25nm.
Here, the etchant may be selected such that the etching depth in the vertical direction may be substantially the same for the first material layer and the third material layer.
Then, as shown in fig. 10 (a), a first active layer 1025 may be formed on the sidewalls of the ridge structure by, for example, selective epitaxial growth. The first active layer 1025 may not be formed on the surface of the first position maintaining layer 1019 due to the selective epitaxial growth. The first active layer 1025 may then define a channel portion, for example, having a thickness of about 3nm-15nm. The first active layer 1025 (particularly its portion on the sidewall of the second material layer) may be electrically referred to as a (vertical) channel layer since the channel portion (although it may be C-shaped) extends mainly in the vertical direction. According to an embodiment of the present disclosure, the thickness of the first active layer 1025 (which then serves as a channel portion) may be determined by an epitaxial growth process, and thus the thickness of the channel portion may be better controlled. The first active layer 1025 may be doped in situ during epitaxial growth to adjust the threshold voltage of the device.
In fig. 10 (a), the portions of the first active layer 1025 on the sidewalls of the first and third material layers are shown to be relatively thick so that the sidewalls thereof are substantially flush with the sidewalls of the partition 1017 for convenience of illustration only. The grown first active layer 1025 may have a substantially uniform thickness. In addition, the sidewalls of the portions of the first active layer 1025 on the sidewalls of the first and third material layers may be recessed with respect to the sidewalls of the spacer 1017, or may even protrude.
Here, the above-described etching back of the ridge structure may etch the upper and lower ends of the recess upward and downward, respectively, so that after the first active layer 1025 is grown, a height t1 of the recess (corresponding to a gate length of a subsequently formed first gate stack) may be different from a thickness t2 of the second material layer 1003 (corresponding to a gate length of a subsequently formed second gate stack), and in particular, t1 may be greater than t2 in this example. In this way, the first gate stack and the second gate stack, which are subsequently formed on the left and right sides of the first active layer 1025, respectively, may have different gate lengths. The etching recipe may be selected such that the upper and lower ends of the recess are etched up and down by substantially the same amount. Accordingly, the recess having the increased height may be self-aligned to the second material layer 1003, so that the first gate stack and the second gate stack, which are subsequently formed at the left and right sides of the first active layer 1025, respectively, may be self-aligned to each other.
The first active layer 1025 may include various semiconductor materials, for example, an elemental semiconductor material such as Si, ge, etc., or a compound semiconductor material such as SiGe, inP, gaAs, inGaAs, etc. The material of the first active layer 1025 may be appropriately selected according to the performance requirements of the design on the device. In this example, the first active layer 1025 may include Si.
In the example of fig. 10 (a), the first active layers 1025 on opposite sides of the ridge structure in the x-direction may have substantially the same features (e.g., materials, dimensions, doping characteristics, etc.), and may be symmetrically disposed on opposite sides of the second material layer with respect to each other. The present disclosure is not limited thereto. As described below, two devices can be formed opposite each other by a single ridge structure. The first active layer 1025 on opposite sides of the ridge structure may have different characteristics, such as at least one of thickness, material and doping characteristics, depending on the performance requirements of the design for the two devices. This may be achieved by masking one device region while growing the first active layer in the other device region.
According to other embodiments of the present disclosure, to create stress in the channel portion to enhance device performance, the lattice constant of the material of the first active layer 1025 when unstrained may be different from the lattice constant of the material of the second material layer 1003 when unstrained. For example, where the lattice constant of the material of the second material layer 1003 is greater when unstrained than the lattice constant of the material of the first active layer 1025 when unstrained, the first active layer 1025 may have a tensile stress therein (e.g., for an n-type device); and compressive stress may be present in the first active layer 1025 (e.g., for a p-type device) when the lattice constant of the material of the second material layer 1003 when unstrained is less than the lattice constant of the material of the first active layer 1025 when unstrained.
In the case where the first active layer 1025 includes Si, the first active layer 1025 may have a tensile stress in approximately the x-direction, since the second material layer 1003 (in this example, siGe) is relaxed in the y-direction as described above. According to other embodiments of the present disclosure, different kinds and/or different levels of stress may also be achieved by different materials or combinations of materials.
In one example, as shown in fig. 10 (b), an etch stop layer 1025a and a first active layer 1025b may be sequentially formed on the sidewalls of the ridge structure by, for example, selective epitaxial growth. The etch stop layer 1025a may define an etch stop location when the second material layer 1003 is subsequently etched (since in this example both the first active layer 1025b and the second material layer 1003 comprise SiGe, which may affect the first active layer 1025b when etching the second material layer 1003 if no etch stop layer 1025a is provided), for example, to a thickness of about 1nm-5nm. The first active layer 1025b may then define a channel portion as described above, having a thickness of, for example, about 3nm-15nm. In this example, the etch stop layer 1025a may include Si and the first active layer 1025b may include SiGe. To achieve compressive stress, the atomic percent of Ge in the first active layer 1025b may be greater than the atomic percent of Ge in the second material layer 1003.
Of course, other different semiconductor materials, such as III-V compound semiconductor materials, may be grown to achieve the desired strain or stress.
Hereinafter, for convenience, the case of fig. 10 (a) will be described as an example.
In the recess, a first gate stack may then be formed. To prevent the subsequent process from leaving unnecessary material in the recess or affecting the first active layer 1025, a second position-maintaining layer 1027 may be formed in the recess as shown in fig. 11. Likewise, the second position-maintaining layer 1027 may be formed by deposition and then etching back, and may include a material having etching selectivity with respect to the first position-maintaining layer 1019, such as SiC.
In fig. 11 and subsequent figures, portions of the first active layer 1025 adjacent to the third material layer 1005 are shown as being integral with the third material layer 1005 for ease of illustration.
Thereafter, source/drain doping may be performed.
As shown in fig. 12, a solid phase dopant source layer 1029 may be formed on the structure shown in fig. 11 by, for example, deposition. The solid phase dopant source layer 1029 may be formed in a substantially conformal manner. For example, the solid phase dopant source layer 1029 may be an oxide containing dopants with a thickness of about 1nm to 5nm. The dopants contained in the solid phase dopant source layer 1029 may be used to dope the source/drain portions (and optionally the exposed surface of the substrate 1001) and thus may be of the same conductivity type as the source/drain portions that are desired to be formed. For example, for a p-type device, the solid phase dopant source layer 1029 may contain a p-type dopant such as B or In; for n-type devices, the solid phase dopant source layer 1029 may comprise an n-type dopant such As P or As. The concentration of dopants of the solid phase dopant source layer 1029 may be about 0.1% -5%.
In this example, the protective layers 1021, 1023 can be selectively etched by, for example, RIE to expose the surface of the substrate 1001 prior to forming the solid phase dopant source layer 1029. In this way, the exposed surface of substrate 1001 may also be doped to form the respective contact regions for the source/drain S/D at the lower ends of the two devices.
Dopants in the solid phase dopant source layer 1029 may be driven into the first and third material layers by an annealing process to form source/drain S/D (and optionally, may be driven into the exposed surface of the substrate 1001 to form respective contact regions for the source/drain S/D at the lower ends of the two devices), as shown in fig. 13. Thereafter, the solid phase dopant source layer 1029 may be removed.
Since the first material layer and the third material layer may have the same material, and the solid-phase dopant source layer 1029 may be formed on their surfaces in a substantially conformal manner, the degree of driving of dopants from the solid-phase dopant source layer 1029 into the first material layer and the third material layer may be substantially the same. Accordingly, the (doping concentration) interface of the source/drain S/D (with the inner portions of the first material layer, the third material layer) may be substantially parallel to the sidewalls of the first material layer and the third material layer, i.e. may be in a vertical direction, and may be aligned with each other.
In addition, the degree of dopant drive-in the lateral direction may be controlled such that portions of the first material layer, the third material layer, and the second gate stack that are subsequently formed (as shown by the dashed circles) may remain lightly doped (relative to the source/drain portions) or substantially undoped (e.g., dopants from the solid phase dopant source layer 1029 may not substantially enter these portions). This helps to prevent band-to-band tunneling due to gate voltage and/or reduce GIDL.
The portion of the first active layer 1025 on the sidewall of the first material layer is now substantially the same doped (forming the source/drain S/D at the lower end) as the portion of the first material layer therearound, and thus the interface therebetween is not shown in the following figures for convenience of illustration.
In this example, a first material layer is provided through an upper portion of the substrate 1001. The present disclosure is not limited thereto. For example, the first material layer may also be an epitaxial layer on the substrate 1001. In this case, the first material layer and the third material layer may be doped in situ at the time of epitaxy, instead of doping with the solid phase dopant source layer.
In the recess around the ridge structure, an isolation layer 1031, such as a Shallow Trench Isolation (STI), may be formed, as shown in fig. 14. The method of forming the isolation layer may be similar to the method of forming the protection layers 1021, 1023 as described above, and will not be described again.
To this end, the first and second position-maintaining layers 1019 and 1027 (on the outside) and the second material layer 1003 (on the inside) surround a portion of the first active layer 1025. The portion of the first active layer 1025 may serve as a channel portion. The channel portion may be a curved nano-sheet in a C-shape (when the nano-sheet is narrow, for example, the dimension in the direction perpendicular to the paper surface, i.e., the z-direction in fig. 14 is small, it may become a nanowire). Due to the high etch selectivity of etching the second material layer 1003 (SiGe) with respect to the first active layer 1025 (Si), the thickness (thickness, or diameter in the case of nanowires) of the channel portion is substantially determined by the selective growth process of the first active layer 1025. This has a great advantage over techniques that use only etching or photolithography methods to determine thickness, because epitaxial growth processes have much better process control than etching or photolithography. Thus, stress control is also preferred.
Gate stacks may be formed on both sides of the channel portion, respectively.
For example, as shown in fig. 15 (a) and 15 (b), the second position-maintaining layer 1027 (SiC in this example) may be removed by selective etching. The first position-maintaining layer 1019 (in this example, oxide) may remain. Thereby, the space occupied by the second position-maintaining layer 1027 can be released and a portion of the first active layer 1025 can be exposed. In the released space, a first gate stack may be formed. For example, the gate dielectric layer 1037 may be formed in a substantially conformal manner by deposition, and the gate conductor layer 1039 may be formed on the gate dielectric layer 1037. By depositing and then etching back, the gate conductor layer 1039 can substantially occupy the space where the second position-maintaining layer 1027 was previously located. The gate dielectric layer 1037 may also be anisotropically etched, such as by RIE in the vertical direction, to expose the hard mask layer 1013 for subsequent processing.
For example, the gate dielectric layer 1037 may comprise a high-k gate dielectric such as HfO 2, for example, having a thickness of about 2nm to about 10nm. An interfacial layer, such as an oxide formed by an oxidation process or deposition such as Atomic Layer Deposition (ALD), may also be formed to a thickness of about 0.3nm to about 1.5nm prior to forming the high-k gate dielectric. The gate conductor layer 1039 may include a work function adjusting metal such as TiN, taN, tiAlC or the like and a gate conductive metal such as W or the like.
In addition, when the second position maintaining layer 1027 is removed, the first active layer 1025 is maintained by the second material layer 1003 on the inside, so that the stress in it can be suppressed from being released.
Next, the inside of the channel portion may be treated. As shown in fig. 15 (b), when the inside of the channel portion is processed, the first active layer 1025 is held by the gate dielectric layer 1037 and the gate conductor layer 1039 on the outside, and thus stress in the first active layer can be suppressed from being released.
To provide an etch stop layer and to avoid affecting the first gate stack that has been formed on the outside during processing on the inside, an etch stop layer or protective layer 1033 may be formed on the isolation layer 1031, as shown in fig. 16. The etch stop layer or protective layer 1033 may be formed in a substantially conformal manner and may include a material such as SiC having a desired etch selectivity (e.g., relative to the gate stack, isolation layer, first through third material layers, etc., as may be apparent from subsequent selective etching operations).
On the etch stop layer or protective layer 1033, a dielectric material 1035, such as an oxide, may be formed by deposition. The dielectric material 1035 helps to open the process channels to the inside. For example, a planarization process such as CMP may be performed to remove the hard mask layer 1013 to expose the mandrel patterns 1011. The height of the spacer 1017 can be reduced during planarization. Then, the mandrel pattern 1011 may be removed by selective etching such as wet etching using TMAH solution or dry etching using RIE. In this way, a pair of partition walls 1017 extending opposite each other are left on the ridge structure (the height is reduced, the tip morphology may also be changed).
The etching stop layer 1009, the third material layer 1005, the second material layer 1003, and the upper portion of the substrate 1001 may be selectively etched in this order by, for example, RIE using the partition 1017 and the dielectric material 1035 as etching masks. Etching may be performed into the well region of the substrate 1001. Thus, in the space surrounded by the isolation layer 1031, a pair of stacks corresponding to the partition walls 1017 are formed in the third material layer 1005, the second material layer 1003, and the upper portion of the substrate 1001 to define the active region.
Of course, forming the stack for defining the active region is not limited to the partition wall pattern transfer technique, and may be performed by photolithography using a photoresist or the like.
Then, as shown in fig. 17 (a) and 17 (b), the second material layer 1003 (SiGe in this example) may be removed by selective etching with respect to the first active layer 1025, the substrate 1001, and the third material layer 1005 (Si in this example). Thus, the inner side of the channel portion is exposed. At this time, the channel portion is held by the first gate stack at the outside, so that the stress therein can be suppressed from being released.
In the case shown in fig. 10 (b), the selective etching of the second material layer 1003 may be stopped at the etching stop layer 1025a, and the etching stop layer 1025a may be further removed to expose the first active layer 1025b. Alternatively, etch stop layer 1025a may be left, as etch stop layer 1025a of Si helps improve the gate-dielectric interface characteristics.
Similarly, a second gate stack may be formed on the inner side.
An isolation layer may be formed on the inner side before forming the second gate stack. For example, as shown in fig. 17 (a) and 17 (b), the isolation layer may be formed on the inner side by deposition (and planarization) and then etching back. For example, the isolation layer may comprise an oxide and is thus shown as 1031 together with the previous isolation layer 1031 and dielectric material 1035 (also etched back together). The top surface of the isolation layer 1031 may be lower than the top surface of the first material layer (i.e., the top surface of the substrate 1001) or the bottom surface of the second material layer. The gate dielectric layer 1037' may be formed by deposition in a substantially conformal manner and the gate conductor layer 1039' may be formed over the gate dielectric layer 1037 '. By depositing and then etching back, the gate conductor layer 1039' may substantially occupy the space in which the second material layer 1003 was previously located.
Similarly, the gate dielectric layer 1037' may also include a high-k gate dielectric such as HfO 2, for example, having a thickness of about 2nm to about 10nm. An interfacial layer, such as an oxide having a thickness of about 0.3nm to 1.5nm, may also be formed prior to forming the high-k gate dielectric.
To optimize device performance, gate dielectric layer 1037' may have different performance parameters (e.g., materials, thicknesses, etc.) than gate dielectric layer 1037.
Similarly, the gate conductor layer 1039' may include a work function adjusting metal such as TiN, taN, tiAlC or the like and a gate conductive metal such as W or the like. To optimize device performance, the gate conductor layer 1039' may have different performance parameters (e.g., materials, equivalent work functions, etc.) than the gate conductor layer 1039. For example, the gate conductor layer 1039 and the gate conductor layer 1039' may include metal elements different from each other.
According to embodiments of the present disclosure, threshold voltages (Vt) caused by the first gate stack (1037/1039) and the second gate stack (1037 '/1039') may be different from each other. For example, for an n-type device, the Vt of the portion of the channel proximate the first gate stack may be lower than the Vt of the portion of the channel proximate the second gate stack; while for a p-type device, the Vt of the portion of the channel proximate the first gate stack may be higher than the Vt of the portion of the channel proximate the second gate stack.
According to embodiments of the present disclosure, the equivalent work functions of the first gate stack (1037/1039) and the second gate stack (1037 '/1039') may be different from each other. For example, for an n-type device, the equivalent work function of the first gate stack may be less than the equivalent work function of the second gate stack (e.g., the second gate stack comprises Ti, the first gate stack comprises Al); while for a p-type device, the equivalent work function of the first gate stack may be greater than the equivalent work function of the second gate stack (e.g., the second gate stack includes Al, the first gate stack includes Ti).
Thus, the fabrication of the device has been substantially completed. As shown in fig. 17 (a) and 17 (b), the device includes a vertical channel portion, which may be in a curved shape such as a C-shape. On one side of the channel portion in the lateral direction (e.g., x-direction), a first gate stack having a first gate length (t 1) may be formed; and a second gate stack having a second gate length (t 2) may be formed on one side of the channel portion in a lateral direction (e.g., x-direction). As mentioned above, the first gate length and the second gate length may be different, in particular the first gate length may be larger than the second gate length. Thus, a distance between an edge of the first gate stack in a vertical direction (e.g., y-direction) and the source/drain portion may be smaller than a distance between an edge of the second gate stack in a vertical direction (e.g., y-direction) and the source/drain portion. The first gate stack and the second gate stack may be self-aligned with each other, e.g., their respective centers in a vertical direction (e.g., y-direction) may be aligned in a lateral direction (e.g., x-direction).
Here, the first gate stack and the second gate stack are electrically isolated from each other. They may be electrically connected to each other through interconnect structures formed in back-end-of-line (BEOL).
According to another embodiment of the present disclosure, the first gate stack and the second gate stack may be electrically connected in the following manner to save area.
In the state shown in fig. 17 (a) and 17 (b), the gate conductor layer 1039 formed outside is surrounded by other layers (for example, gate dielectric layers 1037, 1037', a protective layer 1033, and a first position holding layer 1019). In order to enable the gate conductor layers on both sides inside and outside the channel portion to be electrically connected to each other, at least a portion of the sidewalls of the gate conductor layer 1039 (particularly in the z direction) may be exposed.
For this purpose, as shown in fig. 18 (a) and 18 (b), the gate dielectric layer 1037', the protective layer 1033, and the gate dielectric layer 1037 may be selectively etched in this order by RIE, for example. Thus, the first position maintaining layer 1019 can be exposed. The first position maintaining layer 1019 may be selectively etched to release a portion of the space it occupies. Conductors may then be formed in the released spaces to electrically connect the first gate stack and the second gate stack. To control the etching amount of the first position maintaining layer 1019, ALE may be used. The remaining first position maintaining layer 1019 may protect the channel portion (particularly, an end portion in the z direction), and thus may be referred to as a protective layer. Thereafter, the gate dielectric layer 1037 'and the gate dielectric layer 1037 may be further selectively etched, such as RIE, to expose at least a portion of sidewalls of the gate conductor layers 1039, 1039' in the z-direction.
On the isolation layer 1031, a conductor layer 1041 can be formed by deposition. The conductor layer 1041 may be subjected to a planarization process such as CMP, which may stop at the partition 1017. Then, the conductor layer 1041 may be etched back so that its top surface is lower than the bottom surface of the upper source/drain portion (or the top surface of the second material layer or the bottom surface of the third material layer) to avoid a short circuit between the conductor layer 1041 and the source/drain portion. The conductor layer 1041 may fill a space that is released due to the selective etching of the first position maintaining layer 1019. The gate conductor layers 1039 and 1039' may be electrically connected to each other through the conductor layer 1041.
Currently, two devices are electrically connected to each other due to the conductor layer 1041. The conductor layer 1041 may be broken between the two devices by, for example, photolithography, and landing pads (LANDING PAD) of the gate contact may also be patterned, depending on the device design.
As shown in fig. 19, a photoresist 1043 may be formed and patterned to mask the area of the landing pad where the gate contact is to be formed, while exposing other areas. Here, the photoresist 1043 may cover a portion of the conductor layer 1041 exposed by the partition wall 1017 at one side (upper side in fig. 19) of the partition wall 1017 in the z direction so that the conductor layer 1041 may continuously extend between the gate conductor layers 1039, 1039' at both sides inside and outside the channel portion at the one side.
Then, as shown in fig. 20 (a) and 20 (b), the conductor layer 1041 may be selectively etched, such as by RIE, with the photoresist 1043 (and the spacer 1017) as a mask. Thereafter, the photoresist 1043 may be removed. Here, the gate conductor layers 1039, 1039' may also be etched by an etchant for etching the conductor layer 1041.
Then, the gate conductor layers 1039, 1039' and the conductor layer 1041 remain substantially and self-aligned under the partition wall 1017, except that the conductor layer 1041 protrudes a part on one side (upper side in fig. 20 (b)) of the partition wall 1017 to serve as landing pads. The conductor layer 1041 is separated between two opposing devices respectively under the opposing partition walls 1017.
As shown in fig. 20 (b), there is a first gate stack (1037/1039) on one side of the channel portion in the x direction; on the opposite side of the channel portion in the x-direction, there is a second gate stack (1037 '/1039'). The first gate stack and the second gate stack may be electrically connected to each other through the conductor layer 1041. Both ends of the channel portion in the z direction are covered with a first position holding layer 1019 (i.e., a protective layer).
In this example, the landing pads of the two devices are on the same side (upper side in fig. 20 (b)) as the opposing spacer 1017. The present disclosure is not limited thereto. For example, the landing pads of the two devices may each be located in a different location.
Subsequently, various contacts, interconnect structures, etc. may be fabricated.
For example, as shown in fig. 21 (a) and 21 (b), a dielectric layer 1043 may be formed on the substrate by, for example, deposition and then planarization. Then, a contact hole may be formed, and a conductive material such as metal may be filled in the contact hole to form the contact 1045. The contact portion 1045 may include a contact portion penetrating the partition 1017 and the etch stop layer 1009 to the upper source/drain portion, a contact portion penetrating the dielectric layer 1043 and the isolation layer 1031 to the contact region of the lower source/drain portion, and a contact portion penetrating the dielectric layer 1043 to the landing pad of the conductor layer 1041.
Fig. 22 (a) and 22 (b) show the energy band diagrams of the n-type device according to the comparative example and the n-type device according to the embodiment of the present invention, respectively.
As shown in fig. 22 (a), in the n-type device according to the comparative example, the source region S and the drain region D may be defined by n-type doping in the active region (the source region S and the drain region D are interchangeable, and thus they may be collectively referred to as source/drain regions). The channel region CH may be formed between the source region S and the drain region D. A first gate stack FG (which may be referred to as a front gate) may be formed on one side of the channel region CH, and a second gate stack BG (which may be referred to as a back gate) may be formed on the other side. In general, the first gate stack FG and the second gate stack BG may have the same gate length and be substantially aligned on opposite sides of the channel region CH. Due to this arrangement, on the drain region D side, the band gap (as indicated by the double-headed arrow in the figure) can be made small, and thus electrons are liable to tunnel, resulting in GIDL.
As shown in fig. 22 (b), in the n-type device according to the embodiment of the present disclosure, the edge of the first gate stack FG is farther from the adjacent source/drain region S or D than the corresponding edge of the second gate stack BG is from the adjacent source/drain region S or D. Due to such positional shift, the band gap can be increased with respect to the case shown in fig. 22 (a), electrons are relatively difficult to tunnel, and thus GIDL can be suppressed.
Fig. 22 (a) and 22 (b) illustrate the principle of GIDL suppression by the disclosed embodiments of the present invention with an n-type device as an example. The same is true for p-type devices.
In the above embodiments, the device has substantially the same or similar configuration on the source region side and the drain region side. The present disclosure is not limited thereto. The concept of the present invention can be applied to the drain region side from the viewpoint of suppressing GIDL.
Fig. 23 (a) to 24 (b) schematically show some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure. The differences between this embodiment and the above-described embodiments are mainly described below.
As shown in fig. 23 (a), a substrate 1001 may be provided as described above, and a well region may be formed therein. On the substrate 1001, a first material layer 1002, a second material layer 1003, and a third material layer 1005 may be formed by, for example, epitaxial growth. The first material layer 1002 may be used to define the location of the lower source/drain, for example, to a thickness of about 20nm-200nm. The first material layer 1002 may be doped in-situ during growth, and the doping concentration may be about 1E19-1E21cm -3.
Adjacent ones of the above layers formed over and on substrate 1001 may have etch selectivity with respect to each other. For example, in the case where the substrate 1001 is a silicon wafer, the first material layer 1002 may include Si.
As for the second material layer 1003 and the third material layer 1005, reference can be made to the description in the above embodiment.
Or as shown in fig. 23 (b), a substrate 1001 may be provided as described above, and a well region may be formed therein. On the substrate 1001, a second material layer 1003 and a third material layer 1005 may be formed by, for example, epitaxial growth. Unlike in the previous embodiments, third material layer 1005 may be doped in situ during growth, and the doping concentration may be about 1E19-1E21cm -3.
Thereafter, the process may be performed as in the above-described embodiments.
Starting from the stack shown in fig. 23 (a), a device as shown in fig. 24 (a) can be obtained. Unlike the case where the portions of the first and third material layers adjacent to the second gate stack in the above embodiments may be lightly doped (with respect to the source/drain portions) or substantially undoped, only the portion of the third material layer adjacent to the second gate stack may be lightly doped or substantially undoped (as shown by the dashed circles), and the portion of the first material layer adjacent to the second gate stack may be heavily doped (and thus may be part of the source/drain portions). In this example, the source/drain portion of the upper end may become the drain.
Further, starting from the stack shown in fig. 23 (b), a device shown in fig. 24 (b) can be obtained. Similarly, only the portion of the first material layer adjacent to the second gate stack may be lightly doped or substantially unintentionally doped (as indicated by the dashed circle in the figure), while the portion of the third material layer adjacent to the second gate stack may be heavily doped (and thus may be part of the source/drain). In this example, the source/drain portion of the lower end may become the drain.
Fig. 27 (a) shows an energy band diagram of the n-type device according to this embodiment. The gate stacks FG and BG of fig. 27 (a) may be the same as that shown in fig. 22 (b), except that on the channel portion side (specifically, the source S side), source/drain doping (n-type heavy doping in the case of an n-type device) may extend to the edge of the second gate stack BG. It can be seen that on the drain side D, the benefits of band gap increase and hence GIDL suppression can still be maintained; meanwhile, on the source S side, external resistance can be reduced and performance can be improved due to the source/drain doping profile.
Fig. 25 to 26 schematically illustrate some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.
In the above embodiment, in the etch-back process described in connection with fig. 9, the depth to which the concave portion is etched back upward and downward may be substantially the same. In contrast, in the present embodiment, as shown in fig. 25, the depth to which the concave portion is etched back upward and downward may be different. This may be achieved by selecting the materials of the first material layer and the third material layer, selecting the etching recipe, etc. Only the case where the depth of the upward etchback is greater than the depth of the downward etchback is shown in fig. 25, but it is also possible that the depth of the downward etchback is greater than the depth of the upward etchback.
Then, as shown in fig. 26, the first active layer 1025' may be formed by, for example, selective epitaxial growth. Similarly, after the first active layer 1025 is grown, the height t1 'of the recess may be different from the thickness t2 of the second material layer 1003, and in particular t1' may be greater than t2. In this example, the distance of the upper end of thickness t1 'relative to the upper end of thickness t2 may be greater than the distance of the lower end of thickness t1' relative to the lower end of thickness t2 (which distance may even be zero). Of course, according to other embodiments, the distance of the lower end of thickness t1 'relative to the lower end of thickness t2 may be greater than the distance of the upper end of thickness t1' relative to the upper end of thickness t2 (which distance may even be zero).
Thereafter, the process may be performed as in the above-described embodiments. In the device thus obtained, at one end of the channel portion in the vertical direction, a distance between an edge of the first gate stack and an adjacent source/drain portion is smaller than a distance between an edge of the second gate stack and an adjacent source/drain portion (the source/drain portion may become a drain); while at the other end of the channel portion in the vertical direction, the edges of the first gate stack and the second gate stack may be relatively close to each other, and may even be aligned in the lateral direction (x-direction).
Fig. 27 (b) shows an energy band diagram of the n-type device according to this embodiment. In this embodiment, the edges of the first gate stack FG and the second gate stack BG on the source S side may each be offset with respect to each other less (may even be aligned with each other) and the edges on the drain D side may be offset with respect to each other more, in particular the doping profile of the edges of the first gate stack FG closer to the drain D than the edges of the second gate stack BG. It can be seen that on the drain side D, the benefits of band gap increase and hence GIDL suppression can still be maintained.
In the above embodiment, the first gate stack and the second gate stack are electrically connected to each other through the conductor layer 1041, and the same electrical signal may be received through a contact portion to the conductor layer 1041. The present disclosure is not limited thereto. For example, the conductor layer 1041 may not be formed to electrically connect them to each other, and the first gate stack and the second gate stack may be applied with different electrical signals, respectively.
In the above embodiment, two devices are formed based on a single ridge structure. This is advantageous in simplifying the manufacture. The present disclosure is not limited thereto. For example, a single device may be formed based on a single ridge structure. In this case, the single ridge structure may be similar to the laminated portion under the above single spacer 1017, and the process for the single ridge structure is similar to the process for the laminated portion, except that the sidewalls of the single ridge structure on the side of the hard mask layer 1013 or the mandrel pattern may be masked with an additional layer of material when the outside of the channel portion is processed.
The semiconductor device according to the embodiments of the present disclosure may be applied to various electronic apparatuses. For example, an Integrated Circuit (IC) may be formed based on such a semiconductor device, and an electronic apparatus may be constructed therefrom. Accordingly, the present disclosure also provides an electronic apparatus including the above semiconductor device. The electronic device may also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Such electronic devices are e.g. smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, etc.
According to an embodiment of the present disclosure, there is also provided a method of manufacturing a system on chip (SoC). The method may include the method described above. In particular, a variety of devices may be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (28)

1. A semiconductor device, comprising:
A vertical channel portion on the substrate;
source/drain portions at upper and lower ends of the channel portion, respectively, with respect to the substrate; and
A first gate stack at a first side of the channel portion in a first direction transverse to the substrate and a second gate stack at a second side of the channel portion opposite the first side in the first direction,
Wherein a distance between at least one of an upper edge and a lower edge of the first gate stack in a vertical direction near one end of the channel portion and the corresponding source/drain portion is smaller than a distance between at least one of an upper edge and a lower edge of the second gate stack in a vertical direction near one end of the channel portion and the corresponding source/drain portion,
Wherein the semiconductor device is an n-type device, a threshold voltage of a portion of the channel portion adjacent to the first gate stack is lower than a threshold voltage of a portion of the channel portion adjacent to the second gate stack; or the semiconductor device is a p-type device, the threshold voltage of the portion of the channel portion adjacent to the first gate stack is higher than the threshold voltage of the portion of the channel portion adjacent to the second gate stack.
2. The semiconductor device of claim 1, wherein a gate length of the first gate stack is greater than a gate length of the second gate stack.
3. The semiconductor device of claim 1, wherein,
The semiconductor device is an n-type device, and an equivalent work function of the first gate stack is smaller than an equivalent work function of the second gate stack; or alternatively
The semiconductor device is a p-type device, and an equivalent work function of the first gate stack is greater than an equivalent work function of the second gate stack.
4. The semiconductor device of claim 1, wherein the gate dielectric layer in the first gate stack and the gate dielectric layer in the second gate stack comprise different materials and/or have different thicknesses.
5. The semiconductor device according to claim 1, wherein the gate conductor layer in the first gate stack and the gate conductor layer in the second gate stack include different metal elements.
6. The semiconductor device of claim 1, wherein the first gate stack and the second gate stack are self-aligned in the first direction.
7. The semiconductor device according to claim 6, wherein an offset of an upper edge of an end of the first gate stack near the channel portion in a vertical direction with respect to an upper edge of an end of the second gate stack near the channel portion in a vertical direction is substantially the same as an offset of a lower edge of an end of the first gate stack near the channel portion in a vertical direction with respect to a lower edge of an end of the second gate stack near the channel portion in a vertical direction.
8. The semiconductor device of claim 1, further comprising:
a first semiconductor layer and a second semiconductor layer spaced apart from each other in a vertical direction; and
A third semiconductor layer extending from a sidewall of the first semiconductor layer to a sidewall of the second semiconductor layer,
Wherein the channel portion is formed in a portion of the third semiconductor layer between the first semiconductor layer and the second semiconductor layer in a vertical direction,
Wherein the source/drain is formed in the first semiconductor layer and the third semiconductor layer on the sidewall thereof and the second semiconductor layer and the third semiconductor layer on the sidewall thereof, respectively.
9. The semiconductor device of claim 8, wherein at least one of the first semiconductor layer and the second semiconductor layer is lightly doped or substantially undoped at a portion proximate the second gate stack.
10. The semiconductor device of claim 1, further comprising:
And a protective layer covering an end of the channel portion in a second direction transverse to the substrate, the second direction intersecting the first direction.
11. The semiconductor device of claim 10, further comprising:
and a conductor layer electrically connecting the first gate stack and the second gate stack to each other, wherein the conductor layer surrounds the protective layer.
12. The semiconductor device according to claim 11, wherein the conductor layer is provided only on opposite sides of the channel portion in the second direction.
13. The semiconductor device of claim 10, wherein,
The first gate stack includes a first gate dielectric layer and a first gate conductor layer, the first gate dielectric layer interposed between the first gate conductor layer and the channel portion and between the first gate conductor layer and the protective layer,
The second gate stack includes a second gate dielectric layer and a second gate conductor layer, the second gate dielectric layer interposed between the second gate conductor layer and the channel portion and between the second gate conductor layer and the protective layer.
14. The semiconductor device of claim 1, wherein the gate dielectric layer in the first gate stack is disposed only on a first side of the channel portion and the gate dielectric layer in the second gate stack is disposed only on a second side of the channel portion.
15. The semiconductor device of claim 1, wherein the channel portion comprises curved nanoplates or nanowires having a C-shaped cross-section.
16. The semiconductor device of claim 15, wherein the curved nanoplatelets or nanowires have a substantially uniform thickness.
17. The semiconductor device according to claim 1, wherein both ends of the channel portion in a second direction transverse to the substrate each have an inwardly recessed C-shape, the second direction intersecting the first direction.
18. The semiconductor device of claim 1, wherein at least one of the channel portion and the source/drain portion comprises a single crystal semiconductor material.
19. The semiconductor device of claim 15, wherein there are a plurality of the semiconductor devices on the substrate, wherein the C-shapes of at least one pair of semiconductor devices are facing away from each other.
20. The semiconductor device of claim 19, wherein the channel portions of each of the pair of semiconductor devices are substantially coplanar.
21. A method of manufacturing a semiconductor device, comprising:
Providing a stack of a first material layer, a second material layer and a third material layer on a substrate, the stack having a first side and a second side opposite each other in a first direction transverse to the substrate;
Recessing sidewalls of the second material layer relative to sidewalls of the first material layer and the third material layer in the first direction at the first side and the second side, thereby defining a first recessed portion;
Further etching the first material layer, the second material layer, and the third material layer at the first side and the second side to increase a size of the first concave portion in a vertical direction;
forming a channel layer in the first recess;
forming a first gate stack in the first recess portion in which the channel layer is formed;
Forming a stripe-shaped opening in the stack extending in a second direction transverse to the substrate, the second direction intersecting the first direction, thereby dividing the stack into two portions at the first and second sides, respectively;
removing the second material layer through the opening, and forming a second gate stack in a space released due to the removal of the second material layer,
Wherein the dimension of the first gate stack in the vertical direction is greater than the dimension of the second gate stack in the vertical direction,
Wherein the semiconductor device is an n-type device, a threshold voltage of a portion of the channel layer adjacent to the first gate stack is lower than a threshold voltage of a portion of the channel layer adjacent to the second gate stack; or the semiconductor device is a p-type device, the threshold voltage of the portion of the channel layer adjacent to the first gate stack being higher than the threshold voltage of the portion of the channel layer adjacent to the second gate stack.
22. The method of claim 21, wherein,
Before defining the first recess, the method further comprises:
Recessing sidewalls of the second material layer in the second direction relative to sidewalls of the first material layer and the third material layer at a third side and a fourth side of the stack opposite each other in the second direction, thereby defining a second recessed portion; and
A first position maintaining layer is formed in the second concave portion,
After forming the channel layer, the method further comprises:
Forming a second position maintaining layer in the first concave portion; and
Forming a dopant source layer on sidewalls of the stack; and
Driving dopants in the dopant source layer into the first material layer and the third material layer to form source/drain portions,
Wherein forming the first gate stack comprises:
removing the second position maintaining layer; and
The first gate stack is formed in a space in the first recess portion released due to the removal of the second position maintaining layer.
23. The method of claim 22, further comprising:
Selectively etching the first position maintaining layer to release a part of the space in the second concave portion while the first position maintaining layer still covers an end of the channel layer in the second direction; and
And forming a conductor layer filling a part of the space released in the second concave portion, and electrically connecting the first gate stack and the second gate stack to each other.
24. The method of claim 22, further comprising:
The extent of the driving of dopants into the first and third material layers is controlled such that the dopants do not substantially reach portions of the first and second material layers proximate the second gate stack.
25. The method of claim 21, wherein the channel layer is formed by selective epitaxial growth.
26. The method of claim 21, wherein a dimension of the first recess that increases downward in a vertical direction is substantially equal to a dimension that increases upward.
27. An electronic device comprising the semiconductor device according to any one of claims 1 to 20.
28. The electronic device of claim 27, comprising a smart phone, a personal computer, a tablet, a wearable smart device, an artificial smart device, a mobile power supply.
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