CN105679826B - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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Publication number
CN105679826B
CN105679826B CN201510881401.7A CN201510881401A CN105679826B CN 105679826 B CN105679826 B CN 105679826B CN 201510881401 A CN201510881401 A CN 201510881401A CN 105679826 B CN105679826 B CN 105679826B
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buffer layer
trench
channel region
disposed
stressor
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CN105679826A (en
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李哉勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
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Abstract

A semiconductor device is provided as follows. The substrate includes an NMOS region and a PMOS region. The first trench and the second trench are disposed in the NMOS region. The first buffer layer is disposed in the first trench and the second trench. The stressor is disposed in the first trench and the second trench and on the first buffer layer. The first channel region is disposed between the first trench and the second trench and in the substrate. The first gate electrode is disposed on the first channel region. The third trench is disposed in the PMOS region. The second buffer layer is disposed in the third trench. The second channel region is disposed in the third trench, disposed on the second buffer layer, and has a semiconductor material different from the substrate. The second gate electrode is disposed on the second channel region.

Description

Semiconductor device with a plurality of transistors
Technical Field
The inventive concept relates to a semiconductor device having a buffer layer and a method of forming the semiconductor device.
Background
As transistors are scaled down in size, their on-current decreases. The reduction in the on-current results in a reduction in the operating speed of the transistor.
Disclosure of Invention
According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device as follows. The substrate includes an NMOS region and a PMOS region. The first trench and the second trench are disposed in the NMOS region. The first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and on the first buffer layer. The first channel region is disposed between the first trench and the second trench and in the substrate. The first gate electrode is disposed on the first channel region. The third trench is disposed in the PMOS region. The second buffer layer is disposed in the third trench. The second channel region is disposed in the third trench, disposed on the second buffer layer, and has a semiconductor material different from the substrate. The second gate electrode is disposed on the second channel region.
According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device as follows. The first trench and the second trench are disposed in the substrate. A channel region is disposed between the first trench and the second trench and in the substrate. A gate electrode is disposed on the channel region. The buffer layer is disposed in the first trench and the second trench. The stressor is disposed in the first trench and the second trench and on the buffer layer.
According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device as follows. The drain region and the source region are disposed in the substrate. A trench is disposed between the drain region and the source region and in the substrate. The buffer layer is disposed in the trench. A channel region is disposed in the trench, disposed on the buffer layer, and having a different semiconductor material than the drain region and the source region. A gate electrode is disposed on the channel region.
According to an exemplary embodiment of the inventive concept, there is provided a method of forming a semiconductor device as follows. A first trench and a second trench are formed in a substrate. A first buffer layer is formed in the first trench and the second trench. A stressor is formed on the first buffer layer. A first channel region is formed in the substrate and between the first trench and the second trench. A first gate electrode is formed on the first channel region. A third trench is formed in the substrate. A second buffer layer is formed in the third trench. A second channel region is formed on the second buffer layer. The second channel region includes a semiconductor material different from the substrate. A second gate electrode is formed on the second channel region.
According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device as follows. The first well and the second well are disposed in the substrate. The first well and the second well are isolated from each other by a device isolation layer. The first trench and the second trench are disposed in the first well. The first channel region is disposed between the first trench and the second trench and in the substrate. The first gate electrode is disposed on the first channel region. The third trench is disposed in the second well. The second channel region is disposed in the third trench. The second channel region is formed of a different semiconductor material than the second well. The second gate electrode is disposed on the second channel region.
Drawings
These and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 to 12 are cross-sectional views of a semiconductor device according to an exemplary embodiment of the inventive concept;
fig. 13 to 40 are cross-sectional views of a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept; and
fig. 41 and 42 are system block diagrams of an electronic device according to an exemplary embodiment of the inventive concept.
Although corresponding plan and/or perspective views of some cross-sectional views may not be shown, the cross-sectional views of the device structures shown herein provide support for multiple device structures extending along two different directions (as may be shown in plan views) and/or in three different directions (as may be shown in perspective views). The two different directions may or may not be perpendicular to each other. The three different directions may include a third direction that may be perpendicular to the two different directions. The multiple device structures may be integrated into the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in a cross-sectional view, an electronic device may include multiple device structures (e.g., memory cell structures or transistor structures), as will be shown by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or a two-dimensional pattern.
Detailed Description
Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions may be exaggerated for clarity. It will also be understood that when an element is referred to as being "on" another element or substrate, it can be directly on the other element or substrate, or intervening elements may also be present. It will also be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may also be present. Like reference numerals may refer to like elements throughout the specification and drawings.
Fig. 1 to 12 are sectional views of a semiconductor device according to an exemplary embodiment of the inventive concept.
Referring to fig. 1, a semiconductor device according to an exemplary embodiment of the inventive concept includes a P-well 23, an N-well 24, a device isolation layer 25, a first spacer 37, a first trench 39T1, a second trench 39T2, a third trench 39T3, a first channel region 27, a first buffer layer 46, a stressor 47, an ohmic contact layer 49, a second buffer layer 57, a second channel region 58, a first gate dielectric layer 62, a first gate electrode 64, a first gate capping pattern 66, a second spacer 68, a drain region 69D, a source region 69S, a second gate dielectric layer 74, a second gate electrode 77, and a second gate capping pattern 78 formed on a substrate 21 including an NMOS region and a PMOS region. The first buffer layer 46 includes a first lower buffer layer 43 and a first upper buffer layer 45. The second buffer layer 57 includes a second lower buffer layer 54 and a second upper buffer layer 56.
The P-well 23, the first spacer 37, the first trench 39T1, the second trench 39T2, the first channel region 27, the first buffer layer 46, the stressor 47, the ohmic contact layer 49, the second gate dielectric layer 74, the second gate electrode 77, and the second gate capping pattern 78 are formed in the NMOS region. The N-well 24, the third trench 39T3, the second buffer layer 57, the second channel region 58, the first gate dielectric layer 62, the first gate electrode 64, the first gate capping pattern 66, the second spacer 68, the drain region 69D, and the source region 69S are formed in the PMOS region.
The substrate 21 may include Si, Ge, Silicon On Insulator (SOI), sapphire, glass, AlN, SiC, GaAs, InAs, graphene, CNT (carbon nanotube), plastic, or a combination thereof. For example, the substrate 21 may be a single crystal silicon wafer containing P-type impurities. The first channel region 27 is disposed between the first trench 39T1 and the second trench 39T 2. The first channel region 27 may include single crystal silicon including P-type impurities. The lower portions of the first grooves 39T1 and the lower portions of the second grooves 39T2 are V-shaped. The sidewalls of the first trench 39T1 and the sidewalls of the second trench 39T2 are C-shaped. For example, the left sidewall is "<" shaped and the right sidewall is ">".
The stressor 47 may be formed on the first buffer layer 46 in the first trench 39T1 and the second trench 39T 2. First buffer layer 46 surrounds the bottom and side surfaces of stressor 47. Stressor 47 may be formed of a material having a different lattice constant than first channel region 27. Stressor 47 may comprise a material having a smaller lattice constant than first channel region 27. For example, stressor 47 may comprise GaN. The upper end of stressor body 47 is substantially coplanar with the upper end of first channel region 27.
The first buffer layer 46 is formed in the first trench 39T1 and the second trench 39T 2. The bottom of the first buffer layer 46 is V-shaped. The sidewalls of the first buffer layer 46 are C-shaped (e.g.) "<'shape or'>"shape"). The first buffer layer 46 may include AlxGa1- xN(0<X ≦ 1) graded structure in which the Al content or doping varies such that the Al content of first buffer layer 46 may decrease close to stressor 47 or upward toward stressor 47. The Al content or doping of the first buffer layer 46 may increase near the bottom of the first and second trenches 39T1 and 39T 2.
The first lower buffer layer 43 is in direct contact with the inner walls of the first and second grooves 39T1 and 39T 2. The first lower buffer layer 43 is also in direct contact with the first channel region 27. The bottom of the first lower buffer layer 43 is V-shaped. The sidewalls of the first lower buffer layer 43 are C-shaped (e.g., "<" or ">"). The first lower buffer layer 43 is interposed between the stressor 47 and the first channel region 27. The first lower buffer layer 43 is in direct contact with the side surface of the stressor 47. For example, the first lower buffer layer 43 may include AlN.
The first upper buffer layer 45 is formed on the first lower buffer layer 43 in the first and second trenches 39T1 and 39T 2. The first upper buffer layer 45 is in direct contact with the bottom of the stressor 47. The first upper buffer layer 45 may be made of AlxGa1-xN(0<X is less than or equal to 1) forming a gradual change structure. The Al content in the first upper buffer layer 45 may decrease near the stressor 47. The Al content in the first upper buffer layer 45 may increase near the bottoms of the first and second trenches 39T1 and 39T 2.
For example, the first upper buffer layer 45 may include first to sixth layers sequentially stacked. The first layer of the first upper buffer layer 45 may be AlxGa1-xN(0.7≤X<1) And (3) a layer. The second layer of the first upper buffer layer 45 may be AlxGa1-xN(0.5≤X<0.7) layer and formed on the first layer. The third layer of the first upper buffer layer 45 may be AlxGa1-xN(0.3≤X<0.5)And is formed on the second layer. The fourth layer of the first upper buffer layer 45 may be AlxGa1-xN(0.1≤X<0.3) layer and formed on the third layer. The fifth layer of the first upper buffer layer 45 may be AlxGa1-xN(0.05≤x<0.1) layer and formed on the fourth layer. The sixth layer of the first upper buffer layer 45 may be AlxGa1-xN(0<x<0.05) layer and formed on the fifth layer.
An ohmic contact layer 49 is formed on stressor 47. The upper end of the ohmic contact layer 49 is raised to a level higher than the upper end of the first channel region 27. The ohmic contact layer 49 may include InGaN, a metal silicide, or a combination thereof. A second gate dielectric layer 74, a second gate electrode 77, and a second gate capping pattern 78 are formed on the first channel region 27. The first spacers 37 are formed on side surfaces of the second gate electrode 77 and side surfaces of the second gate capping pattern 78. Stressor 47 may serve as a source/drain.
The bottom of the third groove 39T3 is V-shaped. The sidewalls of the third trench 39T3 are C-shaped (e.g., "<" or ">"). The second channel region 58 is formed on the second buffer layer 57 in the third trench 39T 3. The second buffer layer 57 surrounds the bottom and side surfaces of the second channel region 58. Second channel region 58 may comprise a different semiconductor material than N-well 24. The second channel region 58 may comprise a semiconductor material having a higher hole mobility than silicon. For example, N-well 24 may include single crystal silicon containing N-type impurities, and second channel region 58 may include a Ge layer containing N-type impurities.
The second buffer layer 57 is formed in the third groove 39T 3. The bottom of the second buffer layer 57 is V-shaped. The sidewalls of the second buffer layer 57 are C-shaped (e.g.,) "<'shape or'>"shape"). The second buffer layer 57 may include SiyGe1-y(0<y is less than or equal to 1) a gradual change structure. The Ge content in the second buffer layer 57 may be varied such that the Ge content of the second buffer layer 57 may be increased near the second channel region 58. The Ge content in the second buffer layer 57 may decrease near the bottom of the third trench 39T 3.
The second lower buffer layer 54 is in direct contact with the inner walls of the third grooves 39T 3. The second lower buffer layer 54 is in direct contact with the N-well 24, the drain region 69D, and the source region 69S. The bottom of the second lower buffer layer 54 is V-shaped. The side surface of the second lower buffer layer 54 is C-shaped (e.g., "<" or ">"). The second lower buffer layer 54 is interposed between the second channel region 58 and the drain region 69D, between the second channel region 58 and the source region 69S, between the second channel region 58 and the N-well 24, and between the second upper buffer layer 56 and the N-well 24. The second lower buffer layer 54 is in direct contact with a side surface of the second channel region 58. For example, the second lower buffer layer 54 may include an epitaxially-grown Si layer.
The second upper buffer layer 56 is formed on the second lower buffer layer 54 in the third groove 39T 3. The second upper buffer layer 56 is in direct contact with the second channel region 58. The second upper buffer layer 56 may include SiyGe1-y(0<y is less than or equal to 1) a gradual change structure. The Ge content or doping in the second upper buffer layer 56 may vary such that the Ge content or doping in the second upper buffer layer 56 may increase near the second channel region 58 or upward toward the second channel region 58. The Ge content in the second upper buffer layer 56 may decrease near the bottom of the third trench 39T3 or downward toward the third trench 39T 3.
For example, the second upper buffer layer 56 may include first to sixth layers sequentially stacked. The first layer of the second upper buffer layer 56 may be SiyGe1-y(0.7. ltoreq. y.ltoreq.1) layer the second layer of the second upper buffer layer 56 may be SiyGe1-y(0.5≤y<0.7) layer and formed on the first layer. The third layer of the second upper buffer layer 56 may be SiyGe1-y(0.3≤y<0.5) layer and formed on the second layer. The fourth layer of the second upper buffer layer 56 may be SiyGe1-y(0.1≤y<0.3) layer and formed on the third layer. The fifth layer of the second upper buffer layer 56 may be SiyGe1-y(0.05≤y<0.1) layer and formed on the fourth layer. The sixth layer of the second upper buffer layer 56 may be SiyGe1-y(0<y<0.05) layer and formed on the fifth layer.
A first gate dielectric layer 62, a first gate electrode 64, and a first gate capping pattern 66 are formed on the second channel region 58. The center of the first gate electrode 64 is vertically aligned with the center of the second channel region 58. The second spacers 68 are formed on side surfaces of the first gate electrode 64 and side surfaces of the first gate capping pattern 66. A drain region 69D and a source region 69S are formed in the N-well 24 adjacent to the first gate electrode 64.
According to an exemplary embodiment of the inventive concept, tensile stress may be induced in the first channel region 27 due to the configuration of the stressor 47. The tensile stress created by stressor 47 may enhance the electron mobility of first channel region 27. The first buffer layer 46 may serve to prevent defects from being generated due to a lattice constant difference between the stressor 47 and the P-well 23. First buffer layer 46 may be used to prevent cracks from developing in stressor 47. The V shape of the first groove 39T1 and the second groove 39T2 may be used to relieve stress. Due to the configuration of the second channel region 58, hole mobility may be improved. The second buffer layer 57 may serve to prevent crystal growth defects from being generated in the second channel region 58.
Referring to fig. 2, a P-well 23, an N-well 24, a device isolation layer 25, a first spacer 37, a first trench 39T1, a second trench 39T2, a third trench 39T3, a first channel region 27, a first buffer layer 46, a stressor 47, an ohmic contact layer 49, a second buffer layer 57, a second channel region 58, a first gate dielectric layer 62, a first gate electrode 64, a first gate capping pattern 66, a second spacer 68, a drain region 69D, a source region 69S, a second lower gate dielectric layer 73, a second upper gate dielectric layer 74, a second gate electrode 77, a second gate capping pattern 78, a lower insulating layer 71, an upper insulating layer 81, and a contact plug 83 are formed on a substrate 21 including an NMOS region and a PMOS region. The first buffer layer 46 includes a first lower buffer layer 43 and a first upper buffer layer 45. The second buffer layer 57 includes a second lower buffer layer 54 and a second upper buffer layer 56. The second gate electrode 77 includes a lower gate electrode 75 and an upper gate electrode 76. The second gate electrode 77 may be referred to as a replacement gate electrode.
Referring to fig. 3, a P-well 23, a device isolation layer 25, a first spacer 37, a first trench 39T1, a second trench 39T2, a first channel region 27, a first buffer layer 46, a stressor 47, an ohmic contact layer 49, a second lower gate dielectric layer 73, a second upper gate dielectric layer 74, a second gate electrode 77, a second gate capping pattern 78, a lower insulating layer 71, an upper insulating layer 81, and a contact plug 83 are formed on a substrate 21 including an NMOS region. The first buffer layer 46 includes a first lower buffer layer 43 and a first upper buffer layer 45. The second gate electrode 77 includes a lower gate electrode 75 and an upper gate electrode 76. The upper end of stressor body 47 and the upper end of first channel region 27 are substantially coplanar. The interface between the stressor 47 and the first upper buffer layer 45 is formed by a horizontal plane.
The semiconductor device of fig. 4 is substantially similar to the semiconductor device of fig. 3, except that the semiconductor device of fig. 4 includes a V-shaped interface between the stressor 47 and the first upper buffer layer 45.
The semiconductor device of fig. 5 is substantially similar to the semiconductor device of fig. 3, except that the semiconductor device of fig. 5 includes a U-shaped interface between stressor 47 and first upper buffer layer 45. The inventive concept is not so limited. For example, the interface between stressor body 47 and first upper buffer layer 45 may have a concave shape or a convex shape.
The semiconductor device of fig. 6 is substantially similar to the semiconductor device of fig. 4 except that the upper end of stressor 47 of fig. 6 is raised to a higher level than the upper end of first channel region 27.
The semiconductor device of fig. 7 is substantially similar to the semiconductor device of fig. 4 except that the upper end of stressor 47 of fig. 7 is formed at a lower level than the upper end of first channel region 27.
Referring to fig. 8, an N-well 24, a device isolation layer 25, a third trench 39T3, a second buffer layer 57, a second channel region 58, a first gate dielectric layer 62, a first gate electrode 64, a first gate capping pattern 66, a second spacer 68, a drain region 69D, a source region 69S, a lower insulation layer 71, an upper insulation layer 81, and a contact plug 83 are formed on a substrate 21 including a PMOS region. The second buffer layer 57 includes a second lower buffer layer 54 and a second upper buffer layer 56. The upper end of the second channel region 58 is substantially coplanar with the upper end of the drain region 69D and the upper end of the source region 69S.
The semiconductor device of fig. 9 is substantially similar to the semiconductor device of fig. 8 except that the interface between the second channel region 58 and the second upper buffer layer 56 of fig. 9 is V-shaped.
The semiconductor device of fig. 10 is substantially similar to the semiconductor device of fig. 8, except that the interface between the second channel region 58 and the second upper buffer layer 56 of fig. 10 is U-shaped. The inventive concept is not so limited. For example, the interface between the second channel region 58 and the second upper buffer layer 56 may have a concave shape or a convex shape.
The semiconductor device of fig. 11 is substantially similar to the semiconductor device of fig. 9 except that the upper end of the second channel region 58 of fig. 11 is raised to a higher level than the upper end of the drain region 69D and the upper end of the source region 69S.
The semiconductor device of fig. 12 is substantially similar to the semiconductor device of fig. 9, except that the upper end of the second channel region 58 is formed at a lower level than the upper end of the drain region 69D and the upper end of the source region 69S.
Fig. 13 to 16 are sectional views of methods of forming a semiconductor device according to exemplary embodiments of the inventive concept.
Referring to fig. 13, a P-well 23, an N-well 24, and a device isolation layer 25 are formed on a substrate 21 including an NMOS region and a PMOS region. In some example embodiments, the P-well 23 may be omitted.
Referring to fig. 14, a plurality of trenches 39T1, 39T2, and 39T3 are formed. The plurality of grooves 39T1, 39T2, and 39T3 include a first groove 39T1, a second groove 39T2, and a third groove 39T 3. The first trench 39T1 and the second trench 39T2 are formed in the P-well 23. The first channel region 27 is disposed between the first trench 39T1 and the second trench 39T 2. A third trench 39T3 is formed in N-well 24.
Referring to fig. 15, the first lower buffer layer 43 is formed in the first and second trenches 39T1 and 39T 2. The first upper buffer layer 45 is formed on the first lower buffer layer 43. The first lower buffer layer 43 and the first upper buffer layer 45 constitute a first buffer layer 46. A stressor 47 is formed on the first buffer layer 46. An ohmic contact layer 49 is formed on stressor 47.
Referring to fig. 16, the second lower buffer layer 54 is formed in the third groove 39T 3. The second upper buffer layer 56 is formed on the second lower buffer layer 54. The second lower buffer layer 54 and the second upper buffer layer 56 constitute a second buffer layer 57. The second channel region 58 is formed on the second buffer layer 57.
Referring back to fig. 1, a second gate dielectric layer 74, a second gate electrode 77, and a second gate capping pattern 78 are formed on the first channel region 27 of fig. 16. The first spacers 37 are formed on side surfaces of the second gate electrode 77 and side surfaces of the second gate capping pattern 78.
A first gate dielectric layer 62, a first gate electrode 64, and a first gate capping pattern 66 are formed on the second channel region 58 of fig. 16. The center of the first gate electrode 64 is vertically aligned with the center of the second channel region 58. The second spacers 68 are formed on side surfaces of the first gate electrode 64 and side surfaces of the first gate capping pattern 66. A drain region 69D and a source region 69S are formed in the N-well 24 adjacent to the first gate electrode 64.
Fig. 17 to 40 are sectional views for illustrating a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept.
Referring to fig. 17, a P-well 23, an N-well 24, and a device isolation layer 25 are formed on a substrate 21 including an NMOS region and a PMOS region.
The substrate 21 may be a single crystal silicon wafer containing P-type impurities. The P-well 23 may include single crystal silicon containing P-type impurities. N-well 24 may comprise monocrystalline silicon containing N-type impurities. The device isolation layer 25 may be formed using a Shallow Trench Isolation (STI) method. The device isolation layer 25 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In other exemplary embodiments, the P-well 23 may be omitted.
Referring to fig. 18, a pad (pad) layer 31, a first mask pattern 33, a second mask pattern 35, and first spacers 37 are formed on a substrate 21.
The pad layer 31 may include an insulating material such as silicon oxide. The first mask pattern 33 may include a material having an etch selectivity with respect to the substrate 21. The second mask pattern 35 is formed on the first mask pattern 33. The second mask pattern 35 may include a material having an etch selectivity with respect to the first mask pattern 33 and the substrate 21. For example, the first mask pattern 33 may include polysilicon, and the second mask pattern 35 may include silicon nitride. The process of forming the first and second mask patterns 33 and 35 may include a thin film forming process and a patterning process. The first spacers 37 may cover side surfaces of the first mask patterns 33 and side surfaces of the second mask patterns 35. The process of forming the first spacer 37 may include a thin film forming process and an anisotropic etching process. The first spacers 37 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. For example, the first spacers 37 may include silicon nitride.
Referring to fig. 19, a plurality of trenches 39T1, 39T2, and 39T3 are formed by partially removing the P-well 23 and the N-well 24 using the first mask pattern 33, the second mask pattern 35, and the first spacers 37 as an etch mask. The plurality of grooves 39T1, 39T2, and 39T3 include a first groove 39T1, a second groove 39T2, and a third groove 39T 3. The first trench 39T1 and the second trench 39T2 are formed in the P-well 23. The first channel region 27 is disposed between the first trench 39T1 and the second trench 39T 2. A third trench 39T3 is formed in N-well 24.
The process of forming the plurality of trenches 39T1, 39T2, and 39T3 may include an anisotropic etching process, an isotropic etching process, a directional etching process, or a combination thereof. The lower portions of the plurality of grooves 39T1, 39T2, and 39T3 are V-shaped. The sidewalls of the plurality of trenches 39T1, 39T2, and 39T3 are C-shaped (e.g., "<" or ">"). The first channel region 27 is formed in the P-well 23. The first channel region 27 may include single crystal silicon including P-type impurities. The bottoms of the plurality of trenches 39T1, 39T2, and 39T3 are formed at a higher level than the lower end of the device isolation layer 25.
In other exemplary embodiments, each of the plurality of grooves 39T1, 39T2, and 39T3 may be U-shaped.
Referring to fig. 20, a third mask pattern 42 covering the PMOS region and exposing the NMOS region is formed. The first lower buffer layer 43 is formed in the first trench 39T1 and the second trench 39T 2.
The first lower buffer layer 43 is formed on the inner walls of the first trench 39T1 and the inner walls of the second trench 39T 2. The first lower buffer layer 43 may include a crystal growth material. The first lower buffer layer 43 may include a different material from the first channel region 27. For example, the first lower buffer layer 43 may include AlN.
Referring to fig. 21, the first upper buffer layer 45 is formed on the first lower buffer layer 43 in the first and second trenches 39T1 and 39T 2. The first lower buffer layer 43 and the first upper buffer layer 45 constitute a first buffer layer 46.
The first upper buffer layer 45 may include a crystal growth material. The first upper buffer layer 45 may be selectively formed on the first lower buffer layer 43. The first upper buffer layer 45 may include a different material from the first channel region 27. The first upper buffer layer 45 may include AlxGa1-xN(0<X is less than or equal to 1) a gradual change structure. The Al content in the first upper buffer layer 45 may increase near the bottoms of the first and second trenches 39T1 and 39T 2. The upper surface of the first upper buffer layer 45 may be flat.
For example, the first upper buffer layer 45 may include first to sixth layers sequentially stacked. The first layer of the first upper buffer layer 45 may be AlxGa1-xN (x is more than or equal to 0.7 and less than or equal to 1). The second layer of the first upper buffer layer 45 may be AlxGa1-xN(0.5≤X<0.7) layer and formed on the first layer. The third layer of the first upper buffer layer 45 may be AlxGa1-xN(0.3≤X<0.5) layer and formed on the second layer. The fourth layer of the first upper buffer layer 45 may be AlxGa1-xN(0.1≤X<0.3) layer and formed on the third layer. The fifth layer of the first upper buffer layer 45 may be AlxGa1-xN(0.05≤x<0.1) layer and formed on the fourth layer. The sixth layer of the first upper buffer layer 45 may be AlxGa1-xN(0<x<0.05) layer and formed on the fifth layer.
Referring to fig. 22, an alternative structure of the first upper buffer layer 45 is shown. In fig. 22, the upper surface of the first upper buffer layer 45 is V-shaped. The process conditions may be controlled such that the upper surface of the first upper buffer layer 45 is V-shaped.
Referring to fig. 23, an alternative structure of the first upper buffer layer 45 is shown. In fig. 23, the upper surface of the first upper buffer layer 45 is U-shaped. The process conditions may be controlled such that the upper surface of the first upper buffer layer 45 is U-shaped. The inventive concept is not limited thereto, and the upper surface of the first upper buffer layer 45 may have a concave shape or a convex shape.
Referring to fig. 24, a stressor 47 may be formed on the first buffer layer 46 in the first trench 39T1 and the second trench 39T2 of fig. 21. The inventive concept is not limited thereto, and the stressor 47 may be formed on the first buffer layer 46 of fig. 22 to 23.
Stressor 47 may comprise a crystal growth material. Stressor 47 may comprise a material having a different lattice constant than first channel region 27. Stressor 47 may comprise a material having a smaller lattice constant than first channel region 27. For example, stressor 47 may comprise GaN. Stressor 47 completely fills first trench 39T1 and second trench 39T 2. The upper end of stressor body 47 is substantially coplanar with the upper end of first channel region 27.
Alternatively, the stressor of fig. 25 is formed such that stressor 47 completely fills first trench 39T1 and the upper end of stressor 47 is raised to a higher level than the upper end of first channel region 27.
Alternatively, the stressor of fig. 26 is formed such that the upper end of stressor 47 is lower than the upper end of first channel region 27.
Referring to fig. 27, an ohmic contact layer 49 is formed on the stressor 47 of fig. 24. The inventive concept is not limited thereto and the ohmic contact layer 49 may be formed on the stressor 47 of fig. 25 and 26. The upper end of the ohmic contact layer 49 is higher than the upper end of the first channel region 27. The ohmic contact layer 49 may include InGaN, a metal silicide, Si, or a combination thereof. The ohmic contact layer 49 contacts with a side surface of the first spacer 37.
Referring to fig. 28, the third mask pattern 42 is removed, and a fourth mask pattern 51 covering the NMOS region and exposing the PMOS region is formed. The second lower buffer layer 54 is formed in the third groove 39T 3.
The second lower buffer layer 54 is formed along the inner wall of the third groove 39T 3. The second lower buffer layer 54 may include a crystal growth material. The second lower buffer layer 54 may include the same material as the N-well 24. For example, the second lower buffer layer 54 may include a crystal-grown Si layer. The bottom of the second lower buffer layer 54 is V-shaped. The side surface of the second lower buffer layer 54 is C-shaped (e.g., "<" or ">").
Referring to fig. 29, the second upper buffer layer 56 is formed on the second lower buffer layer 54 in the third grooves 39T 3. The second lower buffer layer 54 and the second upper buffer layer 56 constitute a second buffer layer 57.
The second upper buffer layer 56 may include a crystal growth material. The second upper buffer layer 56 may be selectively formed on the second lower buffer layer 54. The second upper buffer layer 56 may include a different material than the N-well 24. The second upper buffer layer 56 may include SiyGe1-y(0<y is less than or equal to 1) a gradual change structure. The Ge content in the second upper buffer layer 56 may decrease near the bottom of the third trench 39T 3.
For example, the second upper buffer layer 56 may include first to sixth layers sequentially stacked. The first layer of the second upper buffer layer 56 may be SiyGe1-y(0.7≤y<1) And (3) a layer. The second layer of the second upper buffer layer 56 may be SiyGe1-y(0.5≤y<0.7) layer and formed on the first layer. The third layer of the second upper buffer layer 56 may be SiyGe1-y(0.3≤y<0.5) layer and formed on the second layer. The fourth layer of the second upper buffer layer 56 may be SiyGe1-y(0.1≤y<0.3) layer and formed on the third layer. The fifth layer of the second upper buffer layer 56 may be SiyGe1-y(0.05≤y<0.1) layer and formed on the fourth layer. The sixth layer of the second upper buffer layer 56 may be SiyGe1-y(0<y<0.05) layer and formed on the fifth layer.
Alternatively, the formation of the second upper buffer layer 56 of fig. 30 may be controlled such that the upper surface of the second upper buffer layer 56 may be V-shaped.
Alternatively, the formation of the second upper buffer layer 56 of fig. 31 may be controlled such that the upper surface of the second upper buffer layer 56 is U-shaped. The inventive concept is not limited thereto and the upper surface of the second upper buffer layer 56 may have a concave shape or a convex shape.
Referring to fig. 32, the second channel region 58 is formed on the second buffer layer 57 in the third trench 39T3 of fig. 29. Second channel region 58 may comprise a different semiconductor material than N-well 24. The second channel region 58 may include a crystal growth material. The second channel region 58 may comprise a material having a higher hole mobility than silicon. For example, the second channel region 58 may include a Ge layer containing N-type impurities. The second channel region 58 may completely fill the third trench 39T 3. The upper end of the second channel region 58 is coplanar with the upper end of the N-well 24.
Alternatively, the second channel region 58 of fig. 33 is formed such that the upper end of the second channel region 58 is raised to a level higher than the upper end of the N-well 24.
Alternatively, the second channel region 58 of fig. 34 is formed such that the upper end of the second channel region 58 is lower than the upper end of the N-well 24.
Referring to fig. 35, the pad layer 31, the first mask pattern 33, the second mask pattern 35, and the first spacer 37 disposed on the PMOS region of fig. 32 are removed. The N-well 24 and the second channel region 58 are exposed.
Referring to fig. 36, a first gate dielectric layer 62, a first gate electrode 64, a first gate capping pattern 66, and a second spacer 68 are formed on the second channel region 58. A drain region 69D and a source region 69S are formed in the N-well 24.
The first gate dielectric layer 62 can include silicon nitride, silicon oxide, silicon oxynitride, a high-k dielectric, or a combination thereof. The first gate electrode 64 may comprise a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The first gate capping pattern 66 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The second spacers 68 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The drain region 69D and the source region 69S may be formed by implanting P-type impurities into the N-well 24.
Referring to fig. 37, the fourth mask pattern 51 is removed, and a lower insulating layer 71 covering the substrate 21 is formed. The lower insulating layer 71 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or a combination thereof.
Referring to fig. 38, the lower insulating layer 71 is planarized to expose the first mask pattern 33. The second mask pattern 35 is removed.
Referring to fig. 39, the first mask pattern 33 and the pad layer 31 are removed to form a gate trench 72T. The first channel region 27 is exposed through the gate trench 72T.
Referring to fig. 40, a second lower gate dielectric layer 73, a second upper gate dielectric layer 74, a second gate electrode 77, and a second gate capping pattern 78 are formed in the gate trench 72T. The second gate electrode 77 includes a lower gate electrode 75 and an upper gate electrode 76.
The second lower gate dielectric layer 73 may include silicon oxide. The second lower gate dielectric layer 73 may be referred to as an interface oxide or a chemical oxide. The second lower gate dielectric layer 73 may pass H2O2And Si. A second lower gate dielectric layer 73 may be formed on the first channel region 27. The second lower gate dielectric layer 73 is in contact with the first channel region 27. The second upper gate dielectric layer 74 surrounds the side surfaces and the bottom of the second gate electrode 77. A second upper gate dielectric layer 74 is interposed between the second lower gate dielectric layer 73 and the second gate electrode 77. The second upper gate dielectric layer 74 may comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.
The lower gate electrode 75 surrounds the side surfaces and the bottom of the upper gate electrode 76. The lower gate electrode 75 may include a conductive layer to adjust the work function. The upper gate electrode 76 may comprise a metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. The second gate electrode 77 may be referred to as a replacement gate electrode. The second gate capping pattern 78 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the second gate capping pattern 78 may include silicon nitride.
Referring back to fig. 2, an upper insulating layer 81 is formed on the lower insulating layer 71 of fig. 40. A contact plug 83 is formed through the upper insulating layer 81 and the lower insulating layer 71. The upper insulating layer 81 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The contact plug 83 may include a metal layer, a metal nitride layer, a metal oxide layer, a metal silicide layer, a polysilicon layer, or a combination thereof.
Fig. 41 and 42 are system block diagrams of an electronic system according to an exemplary embodiment of the inventive concept.
Referring to fig. 41, the semiconductor device according to an exemplary embodiment may be applied to an electronic system 2100. The electronic system 2100 includes a body 2110, a microprocessor 2120, a power unit 2130, a functional unit 2140, and a display controller 2150. The body 2110 may be a motherboard formed of a Printed Circuit Board (PCB). The microprocessor 2120, the power unit 2130, the functional unit 2140, and the display controller 2150 may be mounted on the main body 2110. The display 2160 may be provided inside or outside the body 2110. For example, a display 2160 is provided on the surface of the body 2110 and displays an image processed by the display controller 2150.
The power unit 2130 may receive a constant voltage from an external battery or the like, divide the voltage into different levels of required voltage, and supply those voltages to the microprocessor 2120, the functional unit 2140, the display controller 2150, and the like. Microprocessor 2120 may receive voltage from power unit 2130 to control functional unit 2140 and display 2160. The functional unit 2140 may perform various functions of the electronic system 2100. For example, when the electronic system 2100 is a smartphone, the functional unit 2140 may have several components that perform functions of a mobile phone by dialing or communicating with an external device 2170, such as outputting images to a display 2160 or outputting sounds to a speaker. The functional unit 2140 can function as a camera image processor when a camera is mounted.
The functional unit 2140 can function as a memory card controller if the electronic system 2100 is connected to a memory card or the like to increase its capacity. The functional unit 2140 can exchange signals with an external device 2170 through the wired or wireless communication unit 2180. Further, when the electronic system 2100 requires a Universal Serial Bus (USB) or the like to extend functionality, the functional unit 2140 may function as an interface controller. Further, the functional unit 2140 may include a mass storage device.
The semiconductor device according to an exemplary embodiment may be applied to the functional unit 2140 or the microprocessor 2120. For example, the microprocessor 2120 may include the first and second buffer layers 46 and 57 of fig. 1-40.
Referring to fig. 42, an electronic system 2400 may include a semiconductor device according to an exemplary embodiment of the inventive concept. The electronic system 2400 may be included in a mobile device or a computer. For example, electronic system 2400 includes memory system 2412, microprocessor 2414, Random Access Memory (RAM)2416, bus 2420, and user interface 2418. The microprocessor 2414, memory system 2412, and user interface 2418 may be connected to each other via a bus 2420. The user interface 2418 may be used to input data to the electronic system 2400 or to output data from the electronic system 2400. The microprocessor 2414 may program and control the electronic system 2400. The RAM2416 may serve as an operating memory for the microprocessor 2414. Microprocessor 2414, RAM2416, and/or other components may be assembled in a single package. The memory system 2412 may store code for operating the microprocessor 2414, data processed by the microprocessor 2414, or externally input data. The memory system 2412 may include a controller and memory devices.
The semiconductor device according to an exemplary embodiment of the inventive concept may be applied to the microprocessor 2414, the RAM2416, and the memory system 2412.
According to an exemplary embodiment of the inventive concept, a stressor may be formed on the first buffer layer in the NMOS region. The stressor may apply a tensile stress to the first channel region, which may improve electron mobility. The first buffer layer may be used to prevent cracks from being created in the stressor. A second channel region may be formed on the second buffer layer in the PMOS region. The second channel region may be subjected to a compressive stress, so that hole mobility may be improved. The second buffer layer may serve to prevent crystal growth defects from being generated in the second channel region. According to example embodiments, a semiconductor device may operate rapidly due to increased mobility of electron and/or hole carriers.
While the present invention has been shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. For example, the inventive concept can be expansively applied to a finFET (field effect transistor), a nanowire transistor, or a three-dimensional transistor.

Claims (16)

1. A semiconductor device, comprising:
a substrate including an NMOS region and a PMOS region;
a first trench and a second trench disposed in the NMOS region;
a first buffer layer disposed in the first trench and the second trench;
a stressor disposed in the first trench and the second trench and disposed on the first buffer layer;
a first channel region disposed between the first trench and the second trench and disposed in the substrate;
a first gate electrode disposed on the first channel region;
a third trench disposed in the PMOS region;
a second buffer layer disposed in the third trench;
a second channel region disposed in the third trench, disposed on the second buffer layer, and having a semiconductor material different from the substrate; and
a second gate electrode disposed on the second channel region,
wherein lower portions of the first trench, the second trench, and the third trench are V-shaped,
wherein the first buffer layer comprises a first lower buffer layer and a first upper buffer layer disposed on the first lower buffer layer, wherein a portion of the first lower buffer layer is in direct contact with a side surface of the stressor, wherein the first lower buffer layer covers an entire side surface of the stressor, and wherein the first upper buffer layer covers an entire bottom surface of the stressor, and
wherein the second buffer layer includes a second lower buffer layer and a second upper buffer layer disposed on the second lower buffer layer, and a portion of the second lower buffer layer is in direct contact with a side surface of the second channel region.
2. The semiconductor device of claim 1, wherein the stressor comprises a material having a smaller lattice constant than the first channel region.
3. The semiconductor device of claim 2, wherein the first channel region comprises Si and the stressor comprises GaN.
4. The semiconductor device of claim 2, wherein the first buffer layer comprises AlxGa1-xN(0<x ≦ 1) a graded structure, wherein the Al content decreases upwards towards the stressor.
5. The semiconductor device of claim 4, wherein the first lower buffer layer comprises AlN and the stressor comprises GaN.
6. The semiconductor device of claim 5, wherein an interface between the stressor and the first upper buffer layer is horizontal, concave, or convex.
7. The semiconductor device of claim 1, wherein an upper surface of the stressor is higher or lower than an upper surface of the first channel region, or is coplanar with an upper surface of the first channel region.
8. The semiconductor device of claim 1, further comprising an ohmic contact layer disposed on the stressor.
9. The semiconductor device of claim 8, wherein the ohmic contact layer comprises InGaN or a combination of InGaN and a metal silicide.
10. The semiconductor device of claim 1, wherein sidewalls of the first, second, and third trenches are C-shaped.
11. The semiconductor device of claim 1, wherein the substrate comprises Si and the second channel region comprises Ge.
12. The semiconductor device of claim 1, wherein the second buffer layer comprises SiyGe1-y(0<y ≦ 1) a graded structure with a Ge content increasing upwards towards the second channel region.
13. The semiconductor device of claim 12, wherein the second lower buffer layer comprises an epitaxial Si layer and the second lower buffer layer is interposed between the second upper buffer layer and sidewalls of the third trench.
14. The semiconductor device of claim 13, wherein an interface between the second channel region and the second upper buffer layer is horizontal, concave, or convex.
15. A semiconductor device, comprising:
a first well and a second well disposed in a substrate, wherein the first well and the second well are isolated from each other by a device isolation layer;
a first trench and a second trench disposed in the first well;
a stressor disposed in the first trench and the second trench;
a first buffer layer disposed in the first trench and the second trench and below the stressor;
a first channel region disposed between the first trench and the second trench and disposed in the substrate;
a first gate electrode disposed on the first channel region;
a third trench disposed in the second well;
a second channel region disposed in the third trench;
a second buffer layer disposed in the third trench and under the second channel region; and
a second gate electrode disposed on the second channel region,
wherein lower portions of the first trench, the second trench, and the third trench are V-shaped,
wherein the first channel region comprises the same material as the first well, the second channel region comprises a different material than the second well, and the stressor comprises a material having a different lattice constant than the first channel region,
wherein the first buffer layer comprises AlxGa1-xN(0<X ≦ 1), and the first buffer layer has an Al doping that decreases upward toward the stressor, the first buffer layer including a first lower buffer layer and a first upper buffer layer disposed on the first lower buffer layer, a portion of the first lower buffer layer in direct contact with the stressor, wherein the first lower buffer layer covers an entire side surface of the stressor, and wherein the first upper buffer layer covers an entire bottom surface of the stressor, and
wherein the second buffer layer comprises SiyGe1-y(0<y ≦ 1), and the second buffer layer has a Ge doping increasing upward toward the second channel region, the second buffer layer including a second lower buffer layer and a second upper buffer layer disposed on the second lower buffer layer, a portion of the second lower buffer layer being in direct contact with the second channel region, wherein the second lower buffer layer covers an entire side surface of the second channel region, and wherein the second upper buffer layer covers an entire bottom surface of the second channel region.
16. The semiconductor device of claim 15, wherein the first well is doped with a P-type impurity and the second well is doped with an N-type impurity.
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