CN105679756B - A kind of terminal structure and its manufacturing method of semiconductor devices top-level metallic - Google Patents
A kind of terminal structure and its manufacturing method of semiconductor devices top-level metallic Download PDFInfo
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- CN105679756B CN105679756B CN201510827026.8A CN201510827026A CN105679756B CN 105679756 B CN105679756 B CN 105679756B CN 201510827026 A CN201510827026 A CN 201510827026A CN 105679756 B CN105679756 B CN 105679756B
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- 229910052751 metal Inorganic materials 0.000 claims description 39
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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Abstract
The invention discloses a kind of terminal structures of semiconductor devices top-level metallic, wherein semiconductor devices includes the chip area for realizing semiconductor devices function, extends to the insulating medium layer and top-level metallic of dicing lane around the dicing lane of chip area, from chip area；Wherein dicing lane is groove structure, which slots in epitaxial layer front surface and be arranged, and trenched side-wall is located at the intersection of dicing lane and chip area, that is, forms the terminal of the top-level metallic of the present invention.The invention also discloses a kind of methods of the terminal of manufacture semiconductor devices top-level metallic of the present invention.The present invention is formed by the terminal structure of top-level metallic, and the corrosion interface pattern of top-level metallic is easy to control, can form precipitous corrosion boundary；And the structure design makes the process window of top-level metallic photoetching and corrosion increase；Dicing lane can also be reduced with cost-effective；Wafer can also be screened out in the imperfect tube core of effective die edge in probe test simultaneously.
Description
Technical field
The present invention relates to the terminal structure of semiconductor devices more particularly to a kind of top-level metallic of semi-conductor discrete device and
Its manufacturing method.
Background technology
At present in semiconductor devices, the terminal structure of top-level metallic is usually all plane, i.e. its top-level metallic
Terminal is the surface of flat insulating medium layer.It it is as shown in Fig. 1 the end of the top-level metallic of the semiconductor devices of the prior art
The primary structure of the schematic diagram of end structure, the semiconductor devices can simply be divided into two regions, that is, realize semiconductor function
Chip area 100 and dicing lane 200, two regions, which are both formed in, generally includes substrate 31（Such as N+Silicon chip：N-type heavy doping
Silicon chip）And the epitaxial layer 32 on substrate 31 by being epitaxially-formed（Such as N-Epitaxial wafer：The silicon epitaxy that N-type is lightly doped
Layer）Semiconductor substrate 300 on.It can be seen that the top-level metallic of chip area 100, is formed in from chip area 100 and prolongs
It extends to dicing lane 200 and covers the insulating medium layer 12 of entire dicing lane 200（Such as silica）Upper surface, and the top layer
The terminal 11a of metal is flat insulating medium layer 12, i.e.,：Insulating medium layer 12 from chip area 100 to scribe region be flat
Smooth extension.The prior art uses the terminal structure of this plane, and it is bad to be primarily due to metal layer Step Coverage ability, exists
The surface of high low head prepares metal layer, crack can be formed at drop having, to influence device performance and reliability.
But many semi-conductor discrete devices, such as power schottky, power MOS, it is very high-power due to needing to bear,
It is often formed by multiple layer metal as the top-level metallic 11 electrically connected, such as TiNiAg, TiWNiVAl etc., these complex metal layers one
As electrode prepared using wet etching.In the production process, the plane terminal structure for forming the top-level metallic such as Fig. 1, more
In the wet etching course of layer top-level metallic 11, due to the difference of each layer rate of metal corrosion, 11 edge circle of top-level metallic is caused
Face pattern is irregular, each layer metal edge forms irregular corrosion interface.In process of production, the top of plane terminal structure
The interfacial corrosion pattern of layer metal is not easily controlled, and the process window of corrosion and photo-mask process is also very narrow, it is desirable that stringent control
System in narrow process window, slightly fluctuate easily generation corrosion interface defect, be such as also easy to produce metal edge excessive erosion or
For metal residual the defects of dicing lane leads to metal adhesion, these defects certainly will cause chip functions to decline or fail.
In summary, the terminal structure of the top-level metallic of existing semiconductor devices, during actual fabrication, it is clear that exist
Certain inconvenience and defect, it is necessary to be improved.
Invention content
In view of the above-mentioned defects in the prior art, the purpose of the present invention is to provide a kind of semiconductor devices, the device architectures
Top-level metallic terminal structure multiple layer metal corrosion interface pattern can be made to be easy to control, etching process window bigger and simultaneously
Dicing lane can be made to narrow, to increase the chip-count on same area wafer, saving components cost；Simultaneously be also avoided that due to
Influence of the technological deficiency to device reliability caused by metal step covering power difference.
To achieve the goals above, the present invention provides a kind of terminal structure of semiconductor devices top-level metallic, described partly to lead
Body device includes：Realize the chip area of semiconductor devices function；And the dicing lane around chip area；Chip area and draw
Film channel is formed in semiconductor substrate front surface, and the semiconductor substrate includes substrate and epitaxial layer formed on a substrate；It is described
Semiconductor devices further includes insulating medium layer, and insulating medium layer extends to dicing lane from chip area and covers the table of dicing lane
Face；The semiconductor devices further includes the top-level metallic for being covered in chip area surface；Wherein dicing lane is groove structure, described
Dicing lane groove is arranged by the epitaxial layer front surface fluting positioned at street area；The dicing lane trenched side-wall is located at
The intersection of dicing lane and chip area, i.e., the terminal of the described top-level metallic.
Further, the groove depth of the dicing lane groove is not less than the thickness of the top-level metallic.
Further, the semiconductor devices is a kind of chip area knot containing groove for realizing semiconductor devices function at it
The semiconductor devices of structure.
Further, the semiconductor devices is trench schottky barrier diode or groove MOSFET.
Further, the semiconductor substrate further includes the cathodic metal for being formed in substrate floor.
The present invention also provides a kind of manufacturing methods of the terminal structure of semiconductor devices top-level metallic, include at least following
Step：
Step（1）, groove is opened up in the epitaxial layer front surface of the semiconductor substrate, groove is located at dicing lane position, institute
The side wall of the groove of formation is located at the intersection of dicing lane and chip area, the i.e. terminal of top-level metallic；
Step（2）, insulating medium layer is formed, insulating medium layer extends to dicing lane from chip area and covers entire scribing
The surface of road groove, including the side wall of covering dicing lane groove and bottom；
Step（3）, top-level metallic, the insulating medium layer of covering step (2) are formed on semiconductor structure；
Step（4）, top-level metallic photoetching corrosion exposes dicing lane trenched side-wall and the insulating medium layer of bottom；That is shape
At the terminal structure of the top-level metallic.
Further, the depth that groove is formed in step (1) is not less than the thickness of top-level metallic.
Beneficial effects of the present invention：
1）The present invention is formed by the terminal structure of top-level metallic, and the corrosion interface pattern of top-level metallic is easy to control,
Precipitous top-level metallic terminal structure can be formed；Avoiding the prior art, to be susceptible to top-level metallic interface level uneven, golden
Belong to the defective workmanships such as excessive erosion, adhesion, improves the reliability of device.
2）In forming the technique of top-level metallic terminal structure of the present invention, compared with prior art, in top-level metallic photoetching
Technique in, alignment precision allows larger error, reduces technology difficulty.
3）Meanwhile in top-level metallic wet etching, the process window of corrosion expands.
4）The precipitous terminal structure that is accurate, and eventually forming of technology controlling and process in corroding due to top-level metallic, therefore,
Correspondingly, dicing lane can be reduced with cost-effective.
5）In addition, being formed in the manufacturing method of the terminal structure of the top-level metallic of the present invention, due to its design feature, pushing up
When layer metal erosion, there are the tube core of edge metal missing, entire top-level metallic can be eroded completely, and therefore, wafer exists
The imperfect tube core of effective die edge can be screened out in probe test, avoid the packaging process in road after flowing into.
6）Meanwhile although this groove structure of the present invention, it is bad caused also to encounter top-level metallic Step Coverage ability
Metal covers bad problem at groove, still, because when top-level metallic terminal eventually forms, trenched side-wall and channel bottom
Top-level metallic be required for eroding, therefore, finally, metal cover step ability caused by the last integrity problem of product this
It can be avoided by invention.
Description of the drawings
Fig. 1 is the schematic diagram of the top-level metallic terminal structure of semiconductor devices in the prior art.
Fig. 2 is a kind of terminal structure schematic diagram of the top-level metallic of semiconductor devices of the present invention.
Fig. 3 is a kind of process sequence diagram of the formation of the terminal structure of the top-level metallic of semiconductor devices of the present invention.
Fig. 4 is the device junction composition of the trench schottky barrier diode of the prior art.
Fig. 5 is the device architecture using the trench schottky barrier diode of the terminal structure of the top-level metallic of the present invention
Figure.
Fig. 6 is the process flow chart for the trench schottky barrier diode device for manufacturing Fig. 5.
Fig. 7 is signal of the terminal structure of the top-level metallic of the semiconductor devices of the present invention before top-level metallic wet etching
Figure.
Fig. 8 is wafer die distribution schematic diagram.
Fig. 9 is the partial enlarged view of II in Fig. 8.
Figure 10 in the prior art tube core top-level metallic corner missing figure.
In each figure：100 be chip area, and 200 be dicing lane, and 31 be substrate, and 32 be epitaxial layer, and 300 be semiconductor substrate,
11 be top-level metallic, and 12 be insulating medium layer, and 11a is the terminal of top-level metallic, and 33 be cathodic metal, and 21 be dicing lane groove,
32a is epitaxial layer front surface, and 13 be active area groove, and 14 be polysilicon, and 15 be barrier metal layer, and 31b is substrate floor, and 4 are
Photoresist, 5 be effective die edge line, and 6 be Waffer edge line, and III indicates the tube core on effective die edge line, IV
Indicate the position of die sections top-level metallic missing.
Specific implementation mode
In order to more clearly illustrate technical scheme of the present invention and invention mesh, implement below in conjunction with the accompanying drawings and specifically
Example, the present invention will be described in further detail.
It is illustrated in figure 2 a kind of terminal structure schematic diagram of the top-level metallic of semiconductor devices of the present invention, the semiconductor
Device includes the chip area 100 for realizing semiconductor devices function and the dicing lane 200 around chip area 100；Chip region
Domain 100 and dicing lane 200 are both formed in 300 front surface of semiconductor substrate, and semiconductor substrate 300 generally includes substrate 31（Such as N
+ silicon chip：The silicon chip of N-type heavy doping）And the epitaxial layer 32 on substrate 31 by being epitaxially-formed（Such as N- epitaxial wafers：N-type
The silicon epitaxy layer being lightly doped）；Certainly, according to the difference of semiconductor devices, it includes substrate 31 and outer that semiconductor substrate 300, which is not limited to,
Prolong layer 32, for example, Schottky diode chip usually used at present, substrate surface also deposits the device the moon having as electrically connecting
Pole metal 33.Divided by dicing lane 200 between two adjacent chip areas 100, it can be to semiconductor by dicing lane 200
Chip on substrate 300 is cut.By Fig. 2 it can further be seen that the semiconductor devices further includes insulating medium layer 12（Such as
Silica）, insulating medium layer 12 extends to dicing lane 200 from chip area 100 and covers the surface of dicing lane 200；Also wrap
Include the top-level metallic 11 for being covered in 100 surface of chip area.Unlike the prior art, dicing lane 200 of the invention is ditch
Slot structure, dicing lane groove 21 are arranged by by the epitaxial layer front surface 32a flutings positioned at 200 region of dicing lane.Dicing lane
21 side wall of groove is located at the intersection of dicing lane 200 and chip area 100, i.e. the terminal 11a of top-level metallic.With in the prior art
The terminal of top-level metallic is that flat insulating medium layer is different, is a channel side at the terminal for the top-level metallic that the present invention is formed
Wall has been here formed as 12 1 high low head of insulating medium layer.Preferably, 21 depth of dicing lane groove is not less than top-level metallic 11
Thickness；21 depth of the dicing lane groove, that is, groove depth H, i.e. the epitaxial layer front surface of chip area 100 and dicing lane groove
The vertical range of bottom epitaxial layer front surface, as Fig. 2 is indicated.
The method for forming the terminal structure of the top-level metallic of the semiconductor devices of the present invention is walked including at least the technique of Fig. 3
Suddenly.
Step 1, dicing lane groove is opened up in the epitaxial layer front surface of semiconductor substrate, dicing lane groove is located at dicing lane position
It sets, is formed by the intersection that trenched side-wall is located at dicing lane and chip area, the i.e. terminal of top-level metallic.The step is preferred
, it is to form the thickness that the depth of groove is not less than top-level metallic, preferably to reach effect of the present invention.
Specifically, in order to open up the dicing lane groove, need semiconductor substrate epitaxial layer front surface on lead to
It crosses photoetching or other similar techniques is arranged a mask and passes through dry etching by the dicing lane in the precalculated position that the mask is exposed
Or other methods etching epitaxial layer forms the dicing lane groove to scheduled gash depth.
Step 2, insulating medium layer is formed, insulating medium layer extends to dicing lane from chip area and covers dicing lane groove
Surface, including covering dicing lane groove side wall and bottom.
Step 3, top-level metallic, the insulating medium layer of covering step 2 are formed on semiconductor structure.
Step 4, top-level metallic photoetching corrosion exposes dicing lane groove.Specifically, passing through photoetching or other similar techniques
One mask is set, dicing lane grooved position is exposed by the mask, by etching top-level metallic, exposes dicing lane groove
The insulating medium layer of side wall and channel bottom forms the terminal structure of the top-level metallic of the present invention.
It is for a more detailed description to the present invention below again by specific example.
Example 1
The terminal structure that the top-level metallic of the present invention is described in detail in the present embodiment is applied in semiconductor devices groove Xiao Te
Device architecture on base barrier diode and manufacturing method.Such as the trench schottky barrier diode device that Fig. 4 is the prior art
Structure chart；Fig. 5 is the trench schottky barrier diode device junction composition of the present embodiment, and the device applies the present invention in Fig. 5
Top-level metallic terminal structure, by two figure it can be seen that both top-level metallic terminal 11a structures variation.
If Fig. 6 is the process flow chart for the trench schottky barrier diode for manufacturing the present embodiment such as Fig. 5.It specifically describes such as
Under：
With reference to figure 6, substrate preparation process is first carried out（S10）.In the substrate preparation process, preparing substrate, any system
Monocrystalline silicon piece prepared by Preparation Method can be used as the substrate, such as：Prepare with crystal orientation be<111>Heavy doping phosphorus N-type silicon
Substrate.
Next, executing epitaxial layer forming step（S20）.In this step, silicon epitaxy layer, extension are formed on a silicon substrate
The opposite silicon substrate of layer 32 is to be lightly doped and have conduction type same as silicon substrate, such as silicon substrate is with crystal orientation<111>'s
The N-type silicon substrate of heavy doping phosphorus, then silicon epitaxy layer is that the N-type of light p-doped is conductive<111>The single-crystal Si epitaxial layers of crystal orientation.
Next, executing the forming step of sacrificial oxide layer（S30）.In this step, pass through thermal oxide or CVD method
Silicon epitaxy layer front surface formed layer of silicon dioxide be used as sacrificial oxide layer, with protect subsequently slot when epi-layer surface not by
Damage.
Next, executing groove forming step（S40）.After coating photoresist on sacrificial oxide layer, pass through lithographic definition
Go out groove figure, the groove includes the active area groove 13 that device original structure includes just（As shown in Figure 5）With for formed
The dicing lane groove 21 of the terminal structure of top-level metallic of the present invention；It is selectively removed by dry etching and is not photo-etched glue protection
Sacrificial oxide layer removes photoresist after exposing epitaxial layer corresponding with groove figure, and the sacrificial oxide layer remained is made
For hard mask；It is protection with hard mask, the epitaxial layer exposed to the open air using dry etching selective etch forms scribing in the epitaxial layer
Road groove 21 and active area groove 13.In this step, it is preferred that the depth of dicing lane groove is not less than the thickness of top-level metallic.
Next, executing primary insulation dielectric layer forming step（S50）.The removal of the methods of wet etching is used to sacrifice first
Oxide layer.Then the primary insulation dielectric layer as separation layer is grown in total top layer；Specifically, such as passing through thermal oxide
Or chemical vapor deposition silica is as insulating medium layer.Then, shape is needed by exposing for photoetching corrosion selectivity
At the region of barrier metal layer；Specifically, for example, by photoresist be mask, be selectively removed not by light using wet etching
The oxide layer of photoresist protection（Primary insulation dielectric layer）, expose corresponding with the figure for needing to form barrier metal layer segment outer
Photoresist is removed after prolonging layer.
Next, executing polysilicon filling step（S60）.In total top layer deposition polysilicon, polysilicon 14 is made to fill out
Full of active area groove 13；Dry etching selective removal partial polysilicon, last polysilicon 14 are filled only in active area groove
13, final occupied state is as shown in Figure 5.
Next, executing secondary insulating dielectric layer forming step（S70）.Secondary insulating medium is formed in total top layer
Layer；Specifically, being such as used as secondary insulating dielectric layer by chemical vapor deposition silica.Then, it is selected by photoetching corrosion
Selecting property exposes the trench region for needing to form barrier metal layer and chip area as MOS functions；Specifically, for example,
It is mask by photoresist, the oxide layer for not being photo-etched glue protection is selectively removed using wet etching（Primary insulation medium
Layer）, expose and remove photoresist with behind figure corresponding region.
Next, executing barrier metal layer forming step（S80）.In total top layer deposition Schottky barrier metal
Layer, wet etching remove the barrier metal layer of insulating medium layer and polysilicon surface, arrangement such as Fig. 5 of last barrier metal layer 15
It is shown.
Next, forming top-level metallic and end step（S90）.Specifically, first carrying out to form top-level metallic step
（S91）, i.e.,：Pass through the methods of thermal evaporation, metal sputtering deposition anode metal layer, that is, top-level metallic in total top layer.So
Afterwards, S92 steps are executed, by lithographic definition figure, wet etching removes the top-level metallic of dicing lane trench region, exposes and draws
Film channel side wall and the insulating medium layer of bottom.This step terminates, that is, forms the terminal structure of the top-level metallic of the present invention, such as scheme
5。
Next, forming cathodic metal step（S100）.Substrate 31 is carried out using the method for grinding substrate floor 31b to subtract
It is thin, then cathodic metal 33 is deposited in substrate floor 31b.Obtain the semiconductor devices trench schottky barrier two as shown in Fig. 5
Pole pipe.
During the trench schottky barrier diode of above-mentioned manufacture top-level metallic terminal structure using the present invention, phase
Trench schottky barrier diode than manufacturing the prior art embodies following advantage in preparation process.
1）In above-mentioned formation top-level metallic and end step（S80）In the process, when carrying out the lithographic definition figure, photoetching
Alignment precision allows larger error, for example the terminal of manufacture prior art top-level metallic is the trench schottky gesture of planar structure
When building diode, photoetching covers inclined about 5 μm of allowable error, and the present embodiment allows the inclined error of set of 10 μm or bigger.
2）Also in above-mentioned formation top-level metallic and end step（S80）In the process, after top-level metallic photoetching, top layer gold is carried out
The process window for belonging to wet etching broadens.For example, top-level metallic is the Schottky diode chip of TiNiAg, using existing skill
The terminal of the top-level metallic of art planar structure, when top-level metallic wet etching, etching process time control is corroded in NiAg
6min, Ti corrode 15S, and the defects of metal excessive erosion or metal residual easily occurs in etching time control slightly deviation；And this
The permission top-level metallic etching process window of embodiment can be realized in wide range：NiAg corrodes：6-10min, Ti corrode：
15-30S, as long as control can obtain precipitous top-level metallic corrosion boundary in such process window range.
3）The pattern of the terminal of top-level metallic has improvement.In the prior art, in the wet etching mistake of multilayer top-level metallic
Cheng Zhong causes top-level metallic edge interface pattern ugly irregular, is also easy to produce corrosion interface defect since corrosion rate differs,
Cause the integrity problem of product.Top-level metallic terminal structure using the present invention, when carrying out top-level metallic wet etching, such as
Shown in Fig. 7 (schematic diagram before top-level metallic wet etching), 11 surface of top-level metallic covers photoresist 4, since dicing lane is groove
Structure, therefore after having etched trenched side-wall metal, the top-level metallic 11 under the etching that will not climb photoresist 4, especially in the ditch
When the depth of slot is not less than the thickness of top-level metallic, best results can finally be formed precipitous as shown in schematic diagram 5
The terminal 11a of smooth top-level metallic.
4）Dicing lane can narrow.As described above, in top-level metallic wet etching, due to dicing lane groove structure,
Precipitous top-level metallic terminal can be formed, and its corrosion is easy to control, therefore compared with the prior art, the width of dicing lane can be reduced
Degree saves cost to increase the number of chips on the same area of chip.
5）If Fig. 8~9, Fig. 8 are tube core distribution map schematic diagram on chip, Fig. 9 is the partial enlarged view in the areas Tu8Zhong II, such as
Figure, outer ring are expressed as Waffer edge line 6, and inner lane indicates effective die edge line 5, fall effective die edge line 5 is outer and the line
On tube core can become the incomplete tube core of technique, such as usually fall often in technical process by limitations such as equipment, techniques
Tube core on effective die edge line 5（As indicated the tube core in the regions III in Fig. 9）, in 11 forming process of top-level metallic,
The tube core falls the part outside effective die edge line 5, cannot be evaporated to top-level metallic, i.e., the tube core has top-level metallic corner to lack
It loses, forms the Portions of top layer metal missing such as the regions IV indicated in Figure 10.The top-level metallic terminal of the prior art is due to using
Planar structure, the tube core of this excalation metal after corroding by top-level metallic, due to most of top-level metallic there is also,
It cannot be screened out in test, easily flow into rear road packaging process, after die package, device has potential reliability
Problem.Top-level metallic terminal structure using the present invention has top-level metallic to lack since dicing lane is groove structure in tube core corner
It when mistake, carries out in top-level metallic wet etching process, corrosive liquid can enter metal deleted areas at the top of trenched side-wall so that whole
A die surfaces top-level metallic can be fallen by general corrosion.Therefore, it using the terminal structure of top-level metallic of the present invention, falls and effectively manages
Imperfect tube core on core edge line 5 is in electrical parameter filler test, meeting test failure, so as to be sifted out and then got ready
Fall, avoids road packaging process after inflow.
6）In original structure in the semiconductor devices containing groove top-level metallic using the present invention terminal structure, due to
The groove of dicing lane groove and semiconductor devices original structure can be completed at the same time, and can't increase process, therefore use this hair
Bright scheme realizes above-mentioned technique effect although using more preferably structure, will not increase process costs simultaneously.
Certainly, the terminal structure of top-level metallic of the invention is not limited to be applied to the semiconductor device containing groove in original structure
Part can also be applied in planar semiconductor device, such as planer schottky diode, planar MOSFET；It applies flat at these
When the structural semiconductor device of face, fluting process and its corresponding cost can be increased in production technology, therefore, application person need from
The technical effect reached and the necessity for carrying out weighing application in the cost spent.
The above will only be presently preferred embodiments of the present invention, be not intended to limit the present invention in any form.
Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent of equivalent variations
Embodiment.For example, in addition on trench schottky barrier diode semiconductor devices, the semiconductor devices such as groove MOSFET can be adopted
With the top-level metallic terminal structure of the present invention, and reach the above invention effect.Therefore, every without departing from technical scheme of the present invention
Content, any simple modifications, equivalents, and modifications made to the above embodiment according to the technical essence of the invention, still
Belong in the range of technical solution of the present invention protection.
Claims (6)
1. a kind of terminal structure of semiconductor devices top-level metallic, the semiconductor devices include：
Realize the chip area of semiconductor devices function；
And the dicing lane around chip area；
Chip area and dicing lane are formed in semiconductor substrate front surface, and the semiconductor substrate includes substrate and shape on substrate
At epitaxial layer；
The semiconductor devices further includes insulating medium layer, and insulating medium layer extends to dicing lane from chip area and covers scribing
The surface in road；
The semiconductor devices further includes the top-level metallic for being covered in chip area surface；
It is characterized in that：Dicing lane is groove structure, and the dicing lane groove passes through before the epitaxial layer positioned at street area
It slots and is arranged in surface；The dicing lane trenched side-wall is located at the intersection of dicing lane and chip area, i.e., the described top-level metallic
Terminal；And the dicing lane trenched side-wall is cliff；The groove depth of the dicing lane groove is not less than the top-level metallic
Thickness.
2. a kind of terminal structure of semiconductor devices top-level metallic according to claim 1, it is characterised in that：It is described partly to lead
Body device is a kind of semiconductor devices of the chip area containing groove structure for realizing semiconductor devices function at it.
3. a kind of terminal structure of semiconductor devices top-level metallic according to claim 2, it is characterised in that：It is described partly to lead
Body device is trench schottky barrier diode or groove MOSFET.
4. a kind of terminal structure of semiconductor devices top-level metallic according to claim 1, it is characterised in that：It is described partly to lead
Structure base board further includes the cathodic metal for being formed in substrate floor.
5. a kind of method of the terminal structure of semiconductor devices top-level metallic described in 1 to 4 any one of manufacturing claims,
It is characterized in that：The terminal structure for manufacturing the semiconductor devices top-level metallic, at least includes the following steps：
Step 1, groove is opened up in the epitaxial layer front surface of the semiconductor substrate, groove is located at dicing lane position, is formed by
The side wall of groove is located at the intersection of dicing lane and chip area, the i.e. terminal of top-level metallic；Wherein, described to open up groove, refer to
In the epitaxial layer front surface of semiconductor substrate be arranged mask, be exposed by the mask dicing lane precalculated position, pass through light
Epitaxial layer is etched into scheduled gash depth and forms the dicing lane groove by quarter；
Step 2, insulating medium layer is formed, insulating medium layer extends to dicing lane from chip area and covers the table of dicing lane groove
Face, including the side wall of covering dicing lane groove and bottom；
Step 3, top-level metallic, the insulating medium layer of covering step 2 are formed on semiconductor structure；
Step 4, top-level metallic photoetching corrosion exposes dicing lane trenched side-wall and the insulating medium layer of bottom；Form institute
The terminal structure for the top-level metallic stated.
6. a kind of manufacturing method of the terminal structure of semiconductor devices top-level metallic according to claim 5, it is characterised in that：
The depth that groove is formed in step 1 is not less than the thickness of top-level metallic.
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| CN111081787B (en) * | 2019-11-20 | 2022-10-28 | 广微集成技术（深圳）有限公司 | Wafer preparation method |
| CN113363240A (en) * | 2021-04-27 | 2021-09-07 | 北京智芯微电子科技有限公司 | Chip metal wire, manufacturing method thereof and wafer |
| CN113130343B (en) * | 2021-06-17 | 2021-10-01 | 绍兴中芯集成电路制造股份有限公司 | Conductive bridge between chips, manufacturing method thereof and chip testing method |
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