CN105676730B - Override device for power distribution management equipment controlled by multiple electrical loads - Google Patents

Override device for power distribution management equipment controlled by multiple electrical loads Download PDF

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CN105676730B
CN105676730B CN201610023295.3A CN201610023295A CN105676730B CN 105676730 B CN105676730 B CN 105676730B CN 201610023295 A CN201610023295 A CN 201610023295A CN 105676730 B CN105676730 B CN 105676730B
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gate
ufm
data
override
input end
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CN105676730A (en
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曹清烽
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Shanghai Aviation Electric Co Ltd
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Shanghai Aviation Electric Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21113—Bus interface has multiplexer, control register, data shift register

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Abstract

The invention realizes the reading and writing operation explanation of the data of the corresponding address of the UFM in the CPLD through the SPI communication; a specification design of the configuration of the channel override switch by the UFM of the CPLD; powering on the CPLD to automatically read data in a corresponding address of the UFM; according to the data value in the corresponding address of UFM, realizing the configuration of override; and all override strategies can override all override signals to the lane's counterparts. Override is configurable without opening the product re-burning program.

Description

Override device for power distribution management equipment controlled by multiple electrical loads
Technical Field
The invention relates to an override device of power distribution management equipment based on multi-path electrical load control.
Background
For secondary distribution products, all the channel switches can be controlled through external communication, namely, the main controller is controlled through communication, and then the main controller controls the on-off of the channels through discrete quantities. When the main controller fails, in order to normally control the channel to be switched on and off, the control of the main controller needs to be avoided, and an override discrete magnitude signal is directly introduced from the outside to directly control the channel switch. The external override signal is independent of the control signal of the main controller, and the channel can be normally controlled to be on or off.
In a typical secondary distribution product, the configuration of the override control is generally given, i.e. given an override signal to control a certain channel or channels, in which case it can be configured by internal logic design. If the configuration of the override signal needs to be changed, the internal logic must be redesigned and a new design program must be burned, which is complicated in process.
Disclosure of Invention
The invention aims to provide an override device of power distribution management equipment controlled by multiple paths of electrical loads, and the override device is a UFM override strategy design based on a CPLD and can freely change override configuration.
In order to achieve the purpose, the technical scheme of the invention is as follows: the override device is characterized by comprising a CPLD chip, wherein the CPLD chip comprises an override configuration module and an UFM connected with the override configuration module, the input end of the override configuration module is connected with five override signals input from the outside, the output end of the override configuration module is connected with an external channel, the UFM is connected with the outside in a communication way, the NCS port of the UFM is connected with an external NCS control signal, the external communication reads and writes data into the inherent address of the UFM in the CPLD, the external NCS control signal is used for activating the UFM, the override configuration module reads data from the inherent address of the UFM, and5 override signals are configured according to the data in the inherent address to control the external channel.
Preferably, the CPLD chip is an EPM1270GT144I5, the UFM in the CPLD chip has 4 external interfaces, which are respectively NCS interfaces, the NCS interface is a chip select interface, when the NCS interface is pulled low, it indicates that the UFM is selected, and the SPI communication can be performed; the SI interface is connected with the external communication input end and is used for reading data when the clock signal rises; the SO interface is connected with the external communication output end and outputs data when the clock signal falls; the SCK interface is a serial clock interface.
Preferably, the override method for the override device of the power distribution management equipment for multi-path electrical load control comprises the following steps: A. the NSC is selected by an external NCS control signal, external communication writes a write enable command word, a write address and write data into the UFM respectively, and the data is written into the inherent address of the UFM; B. the NSC is selected by an external NCS control signal, external communication writes a write-disable command, a write address and any data into the UFM respectively, and the data is shifted out from the inherent address of the UFM to the shift register; C. the override configuration module reads data from the shift register and configures the 5-way override signal to control the external channel based on the read data.
The invention provides a UFM (UFM) override strategy design based on a CPLD (complex programmable logic device), which can randomly change override configuration. And the policy design can be updated online to override the configuration without changing the internal logic design. The design of the override strategy realizes online change of override configuration, is convenient and simple to operate, and avoids the complex operation problem that the override logic needs to be redesigned and the logic program needs to be burned when the override signal is changed. The feasibility of the product was verified by laboratory prototype testing. Meanwhile, the UFM has a power-down storage function, and the data storage operation of the UFM has a large utilization space in the aspect of data power-down storage. The memory can be used as an externally expanded memory in product design, so that the use of components in the design is reduced, and the reliability of the product is improved.
Drawings
FIG. 1 is a block diagram of a channel override control design.
Fig. 2 is a schematic diagram of SPI data transmission.
Fig. 3 illustrates the principle of automatic reading of data inside UFM.
Fig. 4 shows an automatic reading data timing sequence of the UFM internal data.
Fig. 5 is a block diagram of design of an SPI communication based UFM override strategy according to the present invention.
Fig. 6 is a schematic diagram of design of UFM override strategy based on SPI communication.
FIG. 7 shows SPI communication between the DSP and the UFM.
FIG. 8 is a diagram illustrating SPI communication between the DSP and the UFM.
Fig. 9 is a diagram of the internal implementation of the CPLD for SPI communication.
Fig. 10 is a schematic diagram of automatic reading of data inside the UFM.
Fig. 11 shows an automatic reading data sequence of the internal data of the UFM.
Fig. 12 is a diagram of an implementation of data deserialization.
Figure 13 is an implementation diagram of a single channel override configuration.
Detailed Description
The present invention is described herein with reference to 5 override signal control 64 way channels as an example. As shown in fig. 1, an override device for a multi-path electrical load controlled power distribution management device, is characterized in that the override device includes a CPLD chip, the CPLD chip includes an override configuration module and an UFM connected to the override configuration module, a serial-parallel module is further disposed between the UFM and the override configuration module, an input end of the override configuration module is connected to five override signals input from the outside, an output end of the override configuration module is connected to an external channel, the UFM is connected to an external communication, an NCS port of the UFM is connected to an external NCS control signal, the external communication reads and writes data into an inherent address of the UFM in the CPLD, the external NCS control signal is used to activate the UFM, the override configuration module reads data from the inherent address of the UFM, and configures 5 override signals to control the external channel according to the data in the inherent address.
The invention mainly stores the data of the external channel needed to be controlled in the register of the UFM in advance through the external controller, then the data is read by the override configuration module, and the external channel is controlled according to the read data.
The command word, address and written data are written by the external controller at the time of writing. During the process of power-on, the CPLD writes the command word, address and corresponding amount of null data (such as 0xFF) into the fixed address of the UFM, and the UFM automatically outputs the data in the corresponding address to the control information analysis module. The written data of the UFM actually controls whether five control signals control the corresponding channel, for example, whether override 1 controls the first channel, and is controlled by the lowest bit of the written data, as shown in fig. 13, if override 1 needs to control the first channel, D _1[0] is equal to 1; otherwise D _1[0] ═ 0; thus, whether each override controls the corresponding channel is determined by D _1[0], D _2[0], D _3[0], D _4[0], and D _4[0 ].
The present invention will be described in detail below with reference to specific examples.
As shown in fig. 1, external communication reads and writes data into the unique address of the UFM in the CPLD, and the written data is stored in the unique address (the UFM has a power-down storage function). The override configuration module in the CPLD can automatically read the data in the inherent address of the UFM after the product is powered on every time, configure 5 paths of override signals according to the data in the inherent address to specifically control which paths of channels, and each control condition can be covered. The CPLD chip referred to herein is the EPM1270GT144I 5. The UFM of the chip is divided into two types, one is a Base mode, and the UFM of the mode has 256 address spaces, each address space can store one byte, and the total number of the address spaces can store 256 bytes. One is Extended mode. The UFM of this mode has 512 address spaces, divided into two tiles, each with 256 addresses. Each address space may store one word and two tiles may store 512 words in total.
As can be seen from the general framework diagram, the overall design of the UFM override strategy based on CPLD is divided into three parts:
firstly, an external controller is in data communication with the UFM in the CPLD;
reading the data of UFM in CPLD;
and controlling the configuration of channel control.
The first step to be performed for the external communication of the data of the UFM is the data communication between the external controller and the UFM in the CPLD, and it can be known from the data manual of the UFM in the CPLD that there are four data exchange modes between the UFM and the external controller:
1. I2C communication mode (Inter-Integrated Circuit);
2. SPI communication mode (Serial Peripheral Interface);
3. parallel communication mode (Parallel Interface);
4. serial communication mode (Altera Serial Interface).
The data reading of the UFM in the CPLD herein is mainly realized through the SPI communication mode.
The UFM has 4 external interfaces, and a four-wire SPI interface is used, as shown in table 1.
Table 1 interface description
Interface Description of the function
SI Data input interface
SO Data output interface
SCK Serial clock interface
NCS Chip selection interface
As shown in table 1, the NCS is a chip select interface, and when the NCS interface is pulled low, it indicates that the UFM is selected, and SPI communication can be performed; the SI interface reads data at the rising edge of the clock signal; the SO interface outputs data when the clock signal is at the falling edge; all transmitted command words, addresses and data are transmitted bit by bit from the most significant bit to the least significant bit.
When the NCS interface is pulled low, command word data needs to be provided to the UFM immediately, otherwise the UFM will consider an internal logic error and directly ignore the data that is coming. The acquisition of the control command word is to inform the UFM of the purpose and operation of this communication. Table 2 is a channel command word.
TABLE 2 channel Command words
Figure BDA0000906604750000051
As shown in table 2, WREN is a UFM write enable command, and data can be written to the UFM after writing the command word to the UFM, while WRDI is a UFM write disable command, and data cannot be written to the UFM after writing the command word to the UFM. RDSR is a read status register command and WRSR is a write status register command. READ is a READ UFM command and WRITE is a WRITE UFM command. SECTOR-ERASE is a command word for erasing a certain area of UFM of Base mode, and UFM-ERASE is a command word for erasing two areas of UFM of Extended mode.
When the external controller communicates with the SPI of the UFM in the CPLD, the SPI shift registers of the two processors are equivalent to a closed loop connected end to end. When the external controller writes data to the UFM, the shift register of the external controller transfers the data from the most significant bit to the least significant bit of the shift register of the UFM bit by bit. At the same time, the shift register of the UFM transfers data from the most significant bit to the most significant bit of the external controller SPI shift register through the SO port, also bit by bit. As shown in fig. 2, since the data input and output are simultaneous, after the OPCODE and address are written in the process of reading data in the UFM, the UFM will only prepare the data to be read, and also needs to write an arbitrary data byte to shift out the required data from the shift register of the UFM bit by bit.
If it is desired to read data at address 0x00 in a UFM, the UFM is first selected, i.e., the NCS of the UFM is pulled low. Next, OPCODE, i.e., 0x03, is written into the UFM. Then, the address where the data needs to be read is written, and the data in the address 0x00 needs to be read is written in 0x 00. At this time, the UFM has already prepared the data in 0x00, and finally, it is necessary to write any byte of data into the UFM to move the prepared data out of the shift register of the UFM, for example, to write 0 xFF. Therefore, data 0300 FF needs to be sent after UFM chip selection to read the data at address 0x 00. If any byte of data is continuously written into the UFM, the UFM will output the data in the address 0x01, and so on.
The data is written in the same way as the data is read, i.e. the OPCODE command word 0x02 is written first, then the address to be written, e.g. 0x00(0x00 address), is written, and finally the data is written. During the data writing process, attention is paid to: the UFM internal data can only be written to "0" from "1" and cannot be written to "1" from "0", and therefore the contents of this address need to be erased before the data writing operation. Of note in the data erase operation are: data erasure is the erasure of an entire sector, so there is no significant data to confirm the erased sector prior to an erase operation.
After the override configuration data is written by the external controller to the UFM of the CPLD, the CPLD needs to be completely out of control of the external controller, and the override policy implementation is performed by internally reading the values in the UFM. According to the principle of reading and writing UFM data in the CPLD, data can be read and written according to the reading and writing timing diagram of the UFM.
The data within the internal read UFM is divided into two large blocks in total: 1) a frequency clock module; 2) and a command (read-write command) generation module.
The UFM in the CPLD is used for outputting a self-frequency clock to meet the read-write frequency clock requirement, namely, the UFM is provided with a clock frequency through the frequency division and the time delay of the clock frequency. And generating a data read-write command of a fixed address according to the clock frequency. The automatic reading principle of UFM internal data is shown in fig. 3. The OSC port of the UFM is connected with the clock frequency division module, the clock frequency division module is connected with the clock delay module, the clock delay module is connected with the command output module and connected with the SCK port of the UFM, and the command output module is connected with the SI port of the UFM.
The UFM outputs a frequency clock through the OSC port 1, the clock cycle of the normal work of the UFM is not less than 2.8us according to chip data, the maximum cycle of the output waveform of the UFM is 0.208us, and the clock frequency division is carried out through the clock frequency division module 2 to obtain the clock frequency meeting the communication requirement of the UFM.
The operating state and the interface state of the UFM are uncertain in the power-on process. If the UFM outputs a clock signal upon power-up, and a read-write command is input to the UFM, the UFM may output erroneous data. It is therefore necessary to delay a period of time before entering read and write commands into the UFM. The clock frequency is continuously provided to the UFM after being delayed for a period of time by the clock delay module 3. After the clock frequency is realized, a read-write command needs to be written into the UFM according to the clock frequency.
The channel override configuration information is determined during power-up of the product, i.e., the CPLD will read data from the fixed address of the UFM to determine override configuration information during power-up of the product. Therefore, during power-on, the command output module 5 will directly read data from the fixed address of the UFM, both the read command and the address are fixed in the command output module 5, and power-on reading is performed only once.
If the data in the address 0x11 needs to be input with the data 0311 FF, 0x03 is the read command word, 0x11 is the address, 0x03 and 0x11 are fixed in the command output module 5, and 0xFF is used to shift out the data in the address 0x 11. During power-up, when a rising edge of the clock comes, the command output module outputs one bit of data, and the transmission is started from the highest bit of 0x 03. Also the clock has the same frequency and phase as the clock 4 for reading UFM data, which ensures that the module 5 reads data every time it outputs a data UFM. And the UFM selects the state for the chip select during this time period.
The waveforms of the signals in the read period for the data operation in the address 0x11 are shown in fig. 4.
When the SCK is still present, the UFM outputs data at address 0x12 after writing any byte of data into the UFM. After continuing to write any data into the UFM, the data at address 0x13 will be output, and so on. And continuing to wait for the next chip selection signal and command word until the chip selection signal returns to the high level.
The following is an analysis of UFM override policy design based on SPI communication, according to a specific embodiment of the present invention. Fig. 5 is a block diagram of design of UFM override strategy based on SPI communication.
After receiving an external RS485 or CAN communication command, the DSP CAN read and write data into the UFM of the CPLD through the SPI, and the written data is stored into an inherent address in the UFM (the inherent address is given out when the DSP writes in). The post-write override configuration module is capable of reading data in the UFM's native address by itself. Which lanes are specifically controlled by the 5-way override signal is configured according to data within the native address and each control case can be overridden.
The overall design of the UFM override strategy based on SPI communication is divided into three parts:
firstly, the data exchange (SPI communication) between the DSP board card and the UFM in the CPLD;
reading the data of UFM in CPLD;
overriding the configuration of channel control;
the data read by the DSP and the data read by the CPLD from the UFM are selected through an IO port of the DSP, as shown in fig. 5 ″, for example.
A schematic diagram of design of UFM override policy based on SPI communication is shown in fig. 6. The figure includes UFM, the SI port of which is connected to the output of a first AND gate AND1, the first input of the first AND gate AND1 is connected to the output of a first OR gate OR1, the first input of the first OR gate OR1 is connected to the external control NSC _ EN terminal, the second input of the first OR gate OR1 is connected to the SI port for external communication, the second input of the first AND gate AND1 is connected to the output of a fourth OR gate OR4, the first input of the fourth OR gate OR4 is connected to the output of a first inverter D1, the input of the first inverter D1 is connected to the external control NSC _ EN terminal, the second input of the fourth OR gate is connected to the SI _ in terminal of the command output module 5, the SCK port of the UFM is connected to the output of a second AND gate 2, the first input of the second AND gate 2 is connected to the output of the second OR gate OR2, the first input of the second OR gate 2 is connected to the external control NSC _ EN terminal, a second input of the second OR gate OR2 is connected to the SCK port of the external communication, a second input of the second AND gate AND2 is connected to the output of the fifth OR gate OR5, a first input of the fifth OR gate OR5 is connected to the output of the first inverter D1, a second input of the fifth OR gate OR5 is connected to the output of the seventh OR gate OR7, the NCS port of the UFM is connected to the output of the third AND gate 3, a first input of the third AND gate AND3 is connected to the output of the third OR gate OR3, a first input of the third OR gate OR3 is connected to the external control NSC terminal, a second input of the third OR gate OR3 is connected to the NCS _ EN port of the external communication, a second input of the third AND gate 3 is connected to the output of the sixth OR gate OR6, a first input of the sixth OR gate OR6 is connected to the output of the first inverter D2, a second input of the sixth OR gate 6 is connected to the seventh OR gate 9, a second input of the seventh OR gate OR7 is connected to the osc _ stop port, which is output by the osc _ stop port of the external inst58, fig. 6. When the control configuration information of the fixed address is powered on and read for 1 time, the osc _ stop outputs a high level, so as to prevent the command output module 5 from continuing to send a crystal oscillator signal to the UFM during the normal working process. The OSC _ in terminal of the command sending means is connected to the output terminal of the eighth OR gate OR8, the first input terminal of the eighth OR gate OR8 is connected to the output terminal of the ninth OR gate OR9, the second input terminal of the eighth OR gate OR8 is connected to the second input terminal of the sixth OR gate OR6, the first input terminal of the ninth OR gate OR9 is connected to the output terminal of the fifth AND gate, the first input terminal of the fifth AND gate 5 is connected to the external control NSC _ EN terminal, the second input terminal of the fifth AND gate 5 is connected to the clk _ out port of the clock dividing means 2, the clk _ in port of the clock dividing means 5 is connected to the OSC port of the clock dividing means m, the output terminal of the fifth AND gate AND5 is further connected to the first input terminal of the sixth AND gate 6, the second input terminal of the sixth AND gate 6 is connected to the delay _ out port of the clock delaying means 3, the output terminal of the sixth AND gate 6 is further connected to the first input terminal of the ninth OR gate 9, the output terminal of the sixth AND gate 6 is connected to the clock delaying means 1, the delay _ out port of the clock delay module 3 is connected to the second input terminal of the ninth OR-gate OR9, the SO port of the UFM is connected to the input terminal of the tri-state gate TR1 (the tri-state gate TR1, when enabled, the output is the same as the input, AND when not enabled, the output is high impedance), the output terminal of the tri-state gate TR1 is connected to the SO output port of the output DSP, the control terminal of TR1 is connected to the output terminal of the second inverter D2, the input terminal of the second inverter D2 is connected to the external control NSC _ EN terminal, the SO port of the UFM is further connected to the second input terminal of the fourth AND-gate AND4, the first input terminal of the fourth AND-gate 4 is connected to the external control NSC _ EN terminal, AND the output terminal of the fourth AND-gate AND4 is connected to the SO _ IN port of the.
The design principle of UFM override strategy based on SPI communication comprises the following parts:
firstly, the data exchange (SPI communication) between the DSP board card and the UFM in the CPLD;
reading the data of UFM in CPLD;
overriding the configuration of channel control;
in fig. 6, "{ character } place IO port controls data reading of UFM by DSP and automatic reading of UFM by CPLD.
Communication between DSP of board card and SPI of UFM in CPLD
The SPI communication between the DSP and the UFM in the CPLD is shown in fig. 7 and 8.
Fig. 9 is a schematic diagram of the internal implementation of the SPI communication of the UFM in the DSP and the CPLD. The UFM data read-write is divided into two parts when the UFM overrides the channel control configuration, one is the read-write of the DSP to the corresponding address of the UFM, and the other is the self-read-write of the CPLD to the corresponding address of the UFM. When DSP reads and writes, the internal self-read and write functions need to be shielded, and when the internal self-read and write functions need to be shielded. Therefore, one IO port of the DSP is used for selecting the DSP read-write of the UFM or the self-read-write inside the CPLD. When the bit goes low, the DSP is selected to read and write data of the UFM, as shown in FIG. 9.
② UFM internal data reading based on SPI communication
After the configuration data is overridden by the UFM of the CPLD by the DSP, the CPLD needs to be completely out of control of the DSP, and override policy implementation is performed by internally reading the values in the UFM. According to the principle of reading and writing UFM data in the CPLD, data can be read and written according to the reading and writing timing diagram of the UFM.
The data within the internal read UFM is divided into two large blocks in total: 1) a frequency clock module; 2) and a command (read-write command) generation module.
The UFM in the CPLD is used for outputting a self-frequency clock to meet the read-write frequency clock requirement, namely, the UFM is provided with a clock frequency through the frequency division and the time delay of the clock frequency. And generating a data read-write command of a fixed address according to the clock frequency. Fig. 10 illustrates the principle of automatic reading of data inside UFM.
The UFM frequency clock output by the OSC port 1 can enable the clock cycle of the normal work of the UFM to be not less than 2.8us according to chip data, the maximum cycle of the output waveform of the UFM is 0.208us, clock frequency division is carried out through the clock frequency division module 2, the clock cycle is 4.45us, and the clock cycle requirement of the UFM is met.
Because the operating state of the UFM is not fixed during power-up, if a read-write command is input to the UFM upon power-up, the UFM may output erroneous data. It is therefore necessary to delay a period of time before entering read and write commands into the UFM. And the clock delay module 3 delays for a period of time and then continues to provide the clock frequency for the UFM. After the clock frequency is realized, a read-write command needs to be written into the UFM according to the clock frequency.
The command 0300 FF for reading data in address 00 is prepared in the command output module 5, and when a rising edge of clock comes, one bit of data is output, and the data is transmitted from the highest bit of 03. Also, the clock frequency 4 and phase of the clock are the same as those of the UFM data read, so that it is ensured that the command output module 5 reads data every time it transfers one data UFM. And the UFM selects the state for the chip select during this time period.
Because the part is the self-reading and writing of the data in the corresponding address of the UFM by the CPLD, the data reading and writing of the UFM by the DSP are required to be shielded, and the VCC is required to be pulled up to shield the operation of the DSP.
If data in the address of 0x11 is read, the waveforms of the signals in the read period are as shown in fig. 11.
Read data at address 0x 11: firstly sending a read command word 0x03 to the UFM, secondly sending the address 0x11 of the read data to the UFM, and finally sending any byte of data to shift out the data in the address 0x11 in the UFM. When the SCK is still present, the UFM outputs data at address 0x12 after writing any byte of data into the UFM.
Override control channel configuration based on SPI communication
For override designs, processing of the read data is required. The serial-to-parallel data transmission module is used for converting serial data into parallel data after receiving the serial data.
If the serial input data of fig. 12 is converted into parallel data after passing through the module and is transmitted out, the five overrides control 64 channels, and 40 bytes of data are needed. The 40 bytes of data are converted to 320 bits of data, with the 320 bits of data in parallel being used as an override enable for each lane.
As shown in fig. 13, the leading bit of the data D _1 corresponds to the enable of the override signal, and if the override signal can control the T1_1 channel, the leading bit of D _1 is 1, otherwise it is 0. Therefore, each bit of 320 bits can be determined to be a "0" or a "1" according to the corresponding data in the UFM, so that 5 overrides can be performed to control the channel to be controlled, and the combination of 5 override signals to control the 64 channels is arbitrary, and any override combination can be covered.
The UFM and the SPI and SCI of the main controller are comprehensively communicated, namely the main controller uses the SCI communication interface to communicate with the SPI communication interface of the UFM, and the communication mainly completes the matching of two data frames and a communication clock, and the understanding of a communication mechanism and the application of a communication time sequence.
The above description is only intended to represent the embodiments of the present invention, and the description is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (2)

1. The override device is characterized in that the override device comprises a CPLD chip, an override configuration module and an UFM (universal serial bus) connected with the override configuration module are arranged in the CPLD chip, the input end of the override configuration module is connected with five override signals input from the outside, the output end of the override configuration module is connected with an external channel, the UFM is connected with a main controller, the NCS (network control system) port of the UFM is connected with an external NCS (network control system) control signal, external communication reads and writes data into the inherent address of the UFM in the CPLD, the external NCS control signal is used for activating the UFM, the override configuration module reads data from the inherent address of the UFM, and five override signals are configured according to the data in the inherent address to control the external channel; the CPLD chip comprises a UFM, wherein an SI port of the UFM is connected with an output end of a first AND gate, a first input end of the first AND gate is connected with an output end of a first OR gate, a first input end of the first OR gate is connected with an external control end, a second input end of the first OR gate is connected with an external communication port, a second input end of the first AND gate is connected with an output end of a fourth OR gate, a first input end of the fourth OR gate is connected with an output end of a first phase inverter, an input end of the first phase inverter is connected with an external control end, a second input end of the fourth OR gate is connected with an SI _ in end of a command output module, an SCK port of the UFM is connected with an output end of a second AND gate, a first input end of the second AND gate is connected with an output end of the second OR gate, a first input end of the second OR gate is connected with the external control end, a second input end of the second OR gate is connected with an SCK port of the external, the second input end of the second AND gate is connected with the output end of the fifth OR gate, the first input end of the fifth OR gate is connected with the output end of the first inverter, the second input end of the fifth OR gate is connected with the output end of the seventh OR gate, the NCS port of the UFM is connected with the output end of a third AND gate, the first input end of the third AND gate is connected with the output end of a third OR gate, the first input end of the third OR gate is connected with an external control end, the second input end of the third OR gate is connected with an NCS _ EN port for external communication, the second input end of the third AND gate is connected with the output end of a sixth OR gate, the first input end of the sixth OR gate is connected with the output end of a first phase inverter, the second input end of the sixth OR gate is connected with an osc _ stop port, the first input end of a seventh OR gate is connected with the output end of a ninth OR gate, the second input end of the seventh OR gate is connected with an osc _ stop port, and the osc _ stop port is output from an osc _ stop port of external inst 58.
2. The electrical power distribution management apparatus override device of claim 1, wherein the CPLD chip is EPM1270GT144I5, the UFM in the CPLD chip has 4 external interfaces, each of which is an NCS interface, the NCS interface is a chip select interface, when the NCS interface is pulled low, it indicates that the UFM is selected and can perform SPI communication; the SI interface is connected with the external communication input end and is used for reading data when the clock signal rises; the SO interface is connected with the external communication output end and outputs data when the clock signal falls; the SCK interface is a serial clock interface.
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