CN105656460A - Binary angle quantity signal converting system and method - Google Patents

Abstract

The invention belongs to a system and method for converting a binary angle signal based on a digital circuit. It involves the conversion technology of the angle signal. The invention realizes the conversion of binary angle quantity into quadrature incremental pulse. The solution adopted by the present invention is to design an accumulator and a comparator to store and compare the internal state angle. By comparing the size of the input angle with the internal state angle, the internal state angle amount is gradually increased or decreased to a state equal to the input angle. Compute and output quadrature incremental pulse signals during the internal state angle change process. Through this conversion technique, the binary digital angle can be converted into quadrature incremental pulses, which can improve the driving capability of some motor drivers that cannot use resolvers. The resolver output signal is subjected to R/D resolution and angular quantity/quadrature incremental pulse conversion, making these drives compatible with resolvers.

Description

System and method for binary angle measurement signal conversion

technical field

The invention relates to the technical field of digital circuits.

Background technique

In some engineering modules with rotary motion, a motor driver is required for motor rotation control. The motor driver needs to obtain the angle information of the motor during control. There are many sensors that acquire angle information, among which resolvers have high reliability. However, limited by its principle, many drives cannot use a resolver as an angle sensor, or there are many restrictions on the resolver used. Therefore, it is necessary to solve the output signal of the resolver to obtain the binary angle data, and convert the binary angle data into an orthogonal incremental pulse signal to adapt to the driver.

Binary angle data is multi-bit binary digital quantity, its value represents the rotation angle of the rotating mechanism, and its value range is: 0～(2 ⁿ -1), the more bits, the higher the resolution. The quadrature incremental pulses are 3-way quadrature pulse signals, including phase A, phase B, and phase Z. Among them, phase A and phase B are orthogonal to each other. When the rotating structure rotates forward, the pulse signal of phase A is 90° ahead of the pulse signal of phase B; The pulse signal lags by 90°; when the rotating mechanism turns to 0, the Z phase outputs a positive pulse, and it is negative at other times.

Contents of the invention

The technical problem to be solved by the present invention is to convert binary angle data into quadrature incremental pulses based on digital circuits, so that drivers or other engineering module devices that cannot use rotary transformers can use rotary transformers.

The invention provides a system for converting binary angle signals, which is characterized in that it includes an increase and decrease accumulator (1), a comparator (2), a zero-crossing detector (3), a direction gate (4) and a pulse logic ( 5):

The increase and decrease accumulator (1) is used to latch the internal state angle and carry out increase and decrease control to it, and then output the internal state angle signal to the comparator (2); one implementation mode of the increase and decrease accumulator (1) is to adopt Single or multi-stage 74193 binary 4-bit up-down accumulator.

The comparator (2) is used to compare the size of the input angle and the internal state angle, and output the result; one implementation mode is to adopt a single or multi-stage 7485 binary 4-bit comparator.

The zero-crossing detector (3) further judges the size logic output of the comparator (2), corrects the size judgment logic error of the zero-crossing, and outputs the judgment result to the direction gate (4); the input includes the expression of the output of the comparator (2) magnitude of the signal, as well as the input angle and the internal state angle. When the upper 2 bits of the input angle are all 1 and the internal state angle is 0, the output indicates the signal result of "less than"; when the upper 2 bits of the input angle are both 0 and the internal state angle is 1, the output indicates "greater than" The result of the signal; otherwise output the same result as the input from comparator (2).

In one embodiment of the present invention, the zero-crossing detector (3) uses two signals to output the comparison result to the direction gate (4), one signal is A>B, and the other is A<B. When input A is greater than input B, output A>B is valid, and A<B is invalid; when input A is smaller than input B, output A>B is invalid, and A<B is valid; when input A is equal to input B, output A>B and A<B are both invalid. The zero-crossing detector (3) adopts 4-quadrant division to judge and correct the zero-crossing size. Divide the binary quantity from the minimum value (0) to the maximum value (2n) into 4 quadrants, namely 0, 1, 2, 3. The binary number judges which quadrant it is in by the highest two bits, for example, the 8-digit binary number (01000010) ₂ is in the first quadrant. When the input A is in the 0th quadrant and B is in the 3rd quadrant, the correction result is A>B; when A is in the 3rd quadrant and B is in the 0th quadrant, the correction result is A<B; otherwise, no correction is performed.

Direction gate (4), according to the judgment result of zero-crossing detector (3) output, guides external clock input, is used for controlling the amount of increase and decrease accumulator (1) to increase or decrease; Direction gate (4) input includes from crossing The signal representing the size output by the zero detector (3) and the external clock signal; the output control increase or decrease signal of the accumulator (1) to increase or decrease. When the signal indicating size in the input terminal is "greater than", the input clock signal is introduced into the signal terminal indicating "increase" in the output, and the control increase/decrease accumulator (1) increases; when the signal indicating size in the input terminal When it is "less than", the input clock signal is introduced into the signal terminal representing "decrease" in the output, and the increase/decrease accumulator (1) is controlled to decrease; when the signal representing the size in the input terminal is "equal", no Introduce a clock signal to any output.

A kind of embodiment of the present invention, direction gate (4) input end is the A>B input end that represents " greater than ", represents " less than " A<B input end, and external clock input end CLK; Output includes expression " The UP end means "increase" and the DOWN end means "decrease". When A>B is high, it means increase, and the output of UP follows the input clock signal of external clock CLK; when A<B is high, it means decrease, and the output of DOWN follows the input clock signal of external clock CLK; when A>B When A<B and A<B are both high or low, neither the UP terminal nor the DOWN terminal follows the input clock signal of the external clock CLK.

The pulse logic (5) calculates the quadrature incremental pulse to be output under the control of the external clock according to the internal state angle output by the increase/decrease accumulator (1).

Further, the zero-crossing detector (3). The input of the zero-crossing detector (3) includes the signal representing the magnitude output by the comparator (2), as well as the input angle and the internal state angle. When the upper 2 bits of the input angle are all 1 and the internal state angle is 0, the output indicates the signal result of "less than"; when the upper 2 bits of the input angle are both 0 and the internal state angle is 1, the output indicates "greater than" The result of the signal; otherwise output the same result as the input from comparator (2).

Further, the direction door (4). The direction gate input includes the signal indicating the size output from the zero-crossing detector (3) and an external clock signal; the output controls the increase or decrease signal of the increase-decrease accumulator (1). When the signal indicating size in the input terminal is "greater than", the input clock signal is introduced into the signal terminal indicating "increase" in the output, and the control increase/decrease accumulator (1) increases; when the signal indicating size in the input terminal When it is "less than", the input clock signal is introduced into the signal terminal representing "decrease" in the output, and the increase/decrease accumulator (1) is controlled to decrease; when the signal representing the size in the input terminal is "equal", no Introduce a clock signal to any output.

Further, the pulse logic (5). Inputs to the pulse logic include internal state angles and an external clock; output quadrature incremental pulse signals. When the external clock generates a rising or falling edge that is valid for the pulse logic (5) (the rising or falling edge is opposite to the increase and decrease accumulator (1)), the pulse logic (5) calculates the quadrature at this time according to the internal state angle incremental pulse.

Pulse logic (5) input includes binary number P and clock signal CLK; A+, A-, B+, B-, Z+ and Z- of input quadrature incremental pulse. According to the logic relationship of 74193, the increase and decrease accumulator (1) calculates the increase or decrease of the binary number on the falling edge of the clock, so the pulse logic (5) needs to calculate and output the quadrature incremental pulse on the rising edge of the clock. When the input clock signal CLK terminal inputs a rising edge, the pulse logic (5) calculates A+ and A-, B+ and B-, Z+ and Z- by the following formula by inputting the binary number P;

$\left[\begin{array}{c}\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; +</span>\\ \mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; -</span>\\ \mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; +</span>\\ \mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; -</span>\\ \mathrm{<span\; class="notranslate">\; Z</span>}<span\; class="notranslate">\; +</span>\\ \mathrm{<span\; class="notranslate">\; Z</span>}<span\; class="notranslate">\; -</span>\end{array}\right]\left[\begin{array}{c}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}\\ {\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>}\\ {\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>}\\ \frac{{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 15</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 14</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 15</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 14</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>}\end{array},<span\; class="notranslate">\; +</span>{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\right]$

The present invention provides a kind of method of binary angle quantity signal conversion, it is characterized in that, comprises the following steps:

Lock the internal state angle in the increase and decrease accumulator (1), then output the internal state angle signal to the comparator (2);

Comparator (2) compares the size of the input angle and the internal state angle, and outputs the result;

The zero-crossing detector (3) further judges the size logic output of the comparator (2), corrects the size judgment logic error of the zero-crossing, and outputs the judgment result to the direction gate (4);

The direction gate (4) guides the external clock input according to the judgment result output by the zero crossing detector (3), and controls whether the amount of the increase/decrease accumulator (1) increases or decreases;

The pulse logic (5) calculates the quadrature incremental pulse to be output under the control of the external clock according to the internal state angle output by the increase/decrease accumulator (1).

The specific calculation process is as follows:

1. Set an internal state angle and latch it with an increasing or decreasing accumulator.

2. Compare the input angle with the internal state angle through a comparator, and output the result to the zero-crossing detection module.

3. In the zero-crossing detection module, correct the result according to the input angle and the value of the internal state angle. Mainly when the two angles are extremely large and extremely small respectively, the size relationship of the two angles is corrected. Output the result to the direction gate module.

4. In the direction gate module, according to the relationship between the input angle and the internal state angle, input the clock into the increase/decrease accumulator, and control the internal state angle in the increase/decrease accumulator to approach the input angle.

5. During the change of the internal state angle, the pulse logic module calculates the output quadrature incremental pulse according to the internal state angle.

The present invention has the advantages and beneficial effects: the digital circuit-based binary angle measurement/orthogonal incremental pulse signal conversion module of the present invention has high speed, high reliability and low implementation cost during use. Extended driver compatibility is achieved through signal conversion.

Description of drawings

Fig. 1 is the schematic diagram of binary angle quantity/orthogonal incremental pulse conversion method based on digital circuit;

Fig. 2 is the digital circuit diagram of a kind of realization method of binary angle measurement/orthogonal incremental pulse conversion based on digital circuit;

Fig. 3 is a kind of realization mode digital circuit diagram of zero crossing detector;

Fig. 4 is a kind of realization mode digital circuit diagram of direction gate;

Fig. 5 is a kind of implementation mode digital circuit diagram of pulse logic;

FIG. 6 is a time sequence diagram of a binary angle/orthogonal incremental pulse conversion method based on a digital circuit.

detailed description

Referring to accompanying drawing 2, the present invention will be described in further detail below. Designing a 4-bit binary angle conversion incremental pulse module, the steps to solve the above digital circuit-based binary angle measurement/orthogonal incremental pulse conversion method are as follows:

1. Select Fairchild's DM74LS193 as the increase and decrease accumulator (1).

2. Select the M74HC85 of STMicroelectronics as the comparator (2).

3, with reference to accompanying drawing 3 is a kind of realization digital circuit diagram of zero crossing detector (3). When A ₀ A ₁ is high and B ₀ B ₁ is low at the same time, ignore the value of A<B and B>A, the output P<Q is high, P>Q is low; when A ₁ A ₀ is low at the same time And when B ₁ B ₀ is high at the same time, the value of A<B and B>A is ignored, and the output P<Q is low, and P>Q is high; in other cases, P<Q is the value of A<B, and P>Q is B>A value.

4, with reference to accompanying drawing 4 is a kind of realization digital circuit diagram of direction door (4). When A>B is high and A<B is low, UP follows the clock signal and DOWN remains high; when A>B is low and A<B is high, UP remains high and DOWN follows the clock signal.

5, with reference to accompanying drawing 5 is a kind of realization digital circuit diagram of pulse logic (5). Calculate the output incremental pulse according to the value of P _0-3 , latch and output when CLK generates a rising edge.

Example

1, with reference to accompanying drawing 2, illustrate a kind of real-time example of 4 binary angle conversion incremental pulse modules of the present invention below.

2. Select Fairchild's DM74LS193 as the increase and decrease accumulator (1). Input the binary angle as the module input from the DATA end of DM74LS193. The CLEAR end is set low, the BORROW end and the CARRY end are set high, and the loading signal is introduced from the LOAD end.

3. Select the M74HC85 of STMicroelectronics as the comparator (2). Input the output data of DM74LS193 to the B terminal of M74HC85, and input the binary angle measurement data of the module to the A terminal of M74HC85. A<B terminal, A=B terminal and A=B terminal are set low.

4. Build the zero-crossing detector (3) digital circuit according to accompanying drawing 3. The lower two bits of the binary angle input by the module and the lower two bits of the internal state angle latched in the accumulator (1) are respectively used as A ₁ A ₀ and B ₁ B of the zero-crossing detector (3) ₀ input. Input P>Q and P<Q of the comparator (2) to input terminals A>B and A<B of the zero-crossing detector (3) respectively.

5. Build the digital circuit of the direction door (4) according to accompanying drawing 4. Input the P>Q and P<Q of the zero-crossing detector (3) to the input terminals A>B and A<B of the direction gate (4) respectively. At the same time, an external clock signal CLK is introduced.

6. Build the pulse logic (5) digital circuit according to accompanying drawing 5. Input the internal state angle latched in the increase/decrease accumulator (1) to the data terminal P of the pulse logic (5). At the same time, an external clock signal CLK is introduced.

Claims (5)

1. a system of binary angle quantity signal conversion is characterized in that, comprises increase and decrease accumulator (1), comparator (2), zero crossing detector (3), direction gate (4) and pulse logic (5) : An increase/decrease accumulator (1), which is used to latch the internal state angle and perform increase/decrease control on it, and then output the internal state angle signal to the comparator (2); Comparator (2), used to compare the size of the input angle and the internal state angle, and output the result; The zero-crossing detector (3) further judges the size logic output of the comparator (2), corrects the size judgment logic error of the zero-crossing, and outputs the judgment result to the direction gate (4); The direction gate (4) guides the external clock input according to the judgment result output by the zero crossing detector (3), and is used to control whether the amount of the increase/decrease accumulator (1) increases or decreases; The pulse logic (5) calculates the quadrature incremental pulse to be output under the control of the external clock according to the internal state angle output by the increase/decrease accumulator (1). 2. The system of binary angle signal conversion according to claim 1 is characterized in that, the zero-crossing detector (3), the input of the zero-crossing detector (3) includes the representation size of the output of the comparator (2) The signal, as well as the input angle and the internal state angle, when the high 2 bits of the input angle are 1 and the internal state angle is 0, the output indicates the signal result of "less than"; when the high 2 bits of the input angle are 0 and the internal state When the angles are all 1, the output indicates a signal result of "greater than"; otherwise, the output is the same as the result input from the comparator (2). 3. The system of binary angle signal conversion according to claim 1 is characterized in that, the direction gate (4), the direction gate input includes the signal representing the magnitude output from the zero-crossing detector (3), and an external Clock signal; output control increase or decrease accumulator (1) to increase or decrease the signal, when the signal representing the size in the input terminal is "greater than", the input clock signal is introduced into the signal terminal representing "increase" in the output , control the increase and decrease accumulator (1) to increase; when the signal representing the size in the input terminal is "less than", the input clock signal is introduced into the signal terminal representing "decrease" in the output, and the increase and decrease accumulator (1) is controlled ) decreases; when the magnitude signal in the input is "equal", no clock signal is introduced to any output. 4. The system of binary angle measurement signal conversion according to claim 1 is characterized in that, described pulse logic (5), the input of pulse logic comprises internal state angle and external clock; Output quadrature incremental pulse signal, when When the external clock generates a rising or falling edge that is valid for the pulse logic (5), the rising or falling edge is opposite to the increase and decrease accumulator (1), and the pulse logic (5) calculates the quadrature increment at this time according to the internal state angle. Quantity pulse. 5. A method for binary angle measurement signal conversion, characterized in that, comprising the following steps: Lock the internal state angle in the increase and decrease accumulator (1), then output the internal state angle signal to the comparator (2); Comparator (2) compares the size of the input angle and the internal state angle, and outputs the result; The zero-crossing detector (3) further judges the size logic output of the comparator (2), corrects the size judgment logic error of the zero-crossing, and outputs the judgment result to the direction gate (4); The direction gate (4) guides the external clock input according to the judgment result output by the zero crossing detector (3), and controls whether the amount of the increase/decrease accumulator (1) increases or decreases; The pulse logic (5) calculates the quadrature incremental pulse to be output under the control of the external clock according to the internal state angle output by the increase/decrease accumulator (1).