CN116961511A - Improved MSMU hardware current loop and control method - Google Patents
Improved MSMU hardware current loop and control method Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/22—Current control, e.g. using a current control loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/0003—Control strategies in general, e.g. linear type, e.g. P, PI, PID, using robust control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
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Abstract
The invention belongs to the technical field of motor control, and discloses an improved MSMU hardware current loop and a control method, wherein the global timer function of an FPGA is re-planned to realize complete real-time control of current sampling, encoder data reading, encoder data calculation, coordinate transformation, PID operation and SVPWM output modules, so that delay from angle updating to angle calculation is shortened, and the control precision of the current loop is improved. The improved MSMU duty ratio updating strategy refines the time sequence of angle triggering and trigonometric function calculation, and the characteristics of high-speed parallelism of the FPGA are utilized to enable the current acquisition module, the angle updating module and the trigonometric function operation module to work in parallel, and the current acquisition module, the angle updating module and the trigonometric function operation module are synchronously latched to corresponding registers before Park conversion is carried out. The invention formulates the improved MSMU hardware for updating the electric angle in real time by refining the global timer and the FPGA functional moduleCurrent loop update strategy to delay electrical angle update from t+Δt θ Shortening to TN, and realizing the optimization of the electric angle updating delay.
Description
Technical Field
The invention belongs to the technical field of motor control, and particularly relates to an improved MSMU hardware current loop.
Background
The general permanent magnet synchronous motor control technology generally adopts three-ring control of a position ring, a speed ring and a current ring, wherein the performance of the current ring serving as the three-ring control inner ring directly influences the control characteristics of the speed ring, the position ring and other outer rings and even the whole control system.
Thanks to the features of simple programming, short development period, etc. of the DSP processor, currently, the common servo driver in the market usually adopts DSP to realize the three-loop control. The control period of the current loop is difficult to be further reduced due to the fact that the main frequency of a special DSP (such as STM320F28XX series of TI company, the highest main frequency is only 150 MHz) for controlling the motor is limited, and microprocessors such as the DSP only support the architecture of serial execution of instructions; meanwhile, the application of a general bus (such as a CANopen bus) further increases the time for communication processing, the system load further increases, the idle time outside a control period is further reduced, and the difficulty of algorithm optimization increases. Moreover, depending on the chopper updating characteristic of the DSP, the sampling calculation in the period can only be updated in the next period, a period of time delay is generated, and the bandwidth of a current loop and the real-time performance of the system are greatly reduced.
Through the above analysis, the problems and defects existing in the prior art are as follows: the sampling calculation in the current loop period can only be updated in the next period, so that a period of time delay is generated, and the bandwidth of the current loop and the real-time performance of the system are greatly reduced.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides an improved MSMU hardware current loop.
The invention is realized in such a way that an improved MSMU hardware current loop comprises:
a global timer for controlling the interrupt time;
the current sampling module is used for sampling the signals;
an encoder data reading module for reading the encoder signal;
the encoder data calculation module is used for calculating the read encoder signals;
the PID operation module is used for realizing accurate control of the motor;
and the SVPWM output module is used for outputting a control signal.
Further, the method comprises the steps of:
global timer:
the realization of the global timer can be realized by means of timer resources or external clock sources inside the FPGA; the counting period of the timer can be set to realize the required interrupt time; when the timer counts to a set value, an interrupt signal is triggered, so that a control algorithm of the current loop is executed in a fixed period;
And a current sampling module:
the current sampling module is used for converting the motor current signal from an analog form to a digital form by means of an analog-to-digital converter; the sampling rate of the ADC should be determined based on control requirements and signal frequency, and will typically be set to a high enough sampling rate to ensure accurate signal sampling;
encoder data reading and calculation module:
the signal of the encoder needs to be read and connected with the encoder through a counter or an input capturing module; by reading the count value or the pulse number of the encoder signal, the angle information of the motor can be calculated;
PID operation module:
the PID operation module realizes a PID control algorithm, and comprises calculation of a proportional term (P), an integral term (I) and a differential term (D); the input of the PID algorithm is a current error (the difference between a set current value and an actual current value), and the output is a control signal;
SVPWM output module:
the SVPWM output module calculates a corresponding PWM signal according to the output of the PID operation module; the SVPWM algorithm is a modulation technology for generating three-phase alternating voltage, and can realize accurate control of a motor;
utilization of high-speed parallel characteristics of the FPGA:
the high-speed parallel characteristic of the FPGA can be realized through reasonable hardware design and parallel calculation; a proper data path and control logic are established among the current acquisition module, the angle updating module and the trigonometric function operation module, so that the current acquisition module, the angle updating module and the trigonometric function operation module can calculate simultaneously in the same clock period, and the operation efficiency of the whole current loop is improved;
Synchronous latching before Park conversion:
before Park conversion is carried out, synchronization of electrical angle updating and current sampling is ensured; the electrical angle updated values may be latched into the corresponding registers at the current sampling instants using appropriate clock synchronization and register latching techniques to ensure proper data processing.
Further, the implementation of the encoder data reading and calculating module involves the design of the hardware interface and the parsing of the encoder signals specifically including:
1. hardware interface design:
firstly, an AB phase signal of an encoder is connected to an input pin of an FPGA chip; the phase A and the phase B of the encoder are two orthogonal square wave signals, and are used for determining the rotation direction and the rotation speed of the rotor;
ab phase signal analysis:
the counter or the input capturing module on the FPGA chip is used for capturing pulses of the AB phase signals; each time a pulse is captured, the counter value will increase or decrease accordingly; the AB phase signal of the encoder is orthogonally encoded, so that the counter value can be increased in the forward rotation and decreased in the reverse rotation;
3. and (3) angle calculation:
assuming that the AB phase signal of the encoder produces N pulses (N is typically an even number) per revolution, each pulse represents an angle of 360 degrees/N; by reading the value of the counter, the angle of the motor rotor can be calculated;
When the counter value is k, the motor rotor angle is k/N x 360 degrees; for example, when the counter value is 3, the motor rotor angle is 3/360×360 degrees=3 degrees;
4. zero calibration:
in practical application, zero calibration is usually required, namely, the starting position of the motor rotor is determined; the zero calibration process is to determine the initial position by detecting the zero signal of the encoder or the pulse of a specific sequence and calibrate the initial value of the counter correspondingly;
the specific encoder interface and counter/capture module configuration varies from FPGA chip to FPGA chip and encoder model to model.
Further, the implementation of the encoder data reading and calculating module can be divided into the following key steps:
1. hardware interface design:
firstly, an output signal of an encoder needs to be connected to an input pin of an FPGA chip; the encoder outputs two signals: phase A and phase B, these signals are two orthogonal square wave pulse signals; in addition, there is one Z-phase signal for zero calibration, but we don't consider the Z-phase signal here;
2. a counter or input capture module configuration:
a counter or an input capturing module is usually arranged in the FPGA chip and can be used for capturing pulse signals of the encoder; the counter is a register which can increase or decrease the count value each time a trigger signal is received; the input capturing module is used for capturing the time stamp of the pulse signal accurately;
3. Signal decoding and counting:
according to the output signal of the encoder, whether the motor rotates clockwise or anticlockwise can be judged; the direction of each rotation can be obtained by decoding the phase A and the phase B; the counter can record the number of pulse signals, so that the rotating angle of the motor can be tracked in real time; for example, each pulse represents an angle of 360 degrees/N, then the counter value divided by N is the angle of motor rotation;
4. zero calibration:
zero calibration is to determine the starting position of the motor by detecting the zero signal of the encoder or a pulse of a specific sequence; before starting the motor or during system initialization, zero calibration can be performed, and the initial value of the counter is set to a known position, so that a mapping relation between the motor angle and the counter value is established.
Furthermore, by utilizing the characteristic of high-speed parallelism of the FPGA, the current acquisition module, the angle updating module and the trigonometric function operation module work in parallel and are synchronously latched to corresponding registers before Park conversion is carried out.
Further, let N be the number of updates of the electrical angle in one speed loop cycle, the electrical angle update delay is: Δt (delta t) θ ＝Δt I ＝T/N。
Another object of the present invention is to provide an improved MSMU hardware current loop control method using the improved MSMU hardware current loop, where the improved MSMU hardware current loop control method includes:
Step one, setting interrupt time through a global timer;
step two, sampling the signal through a current sampling module;
step three, reading the encoder signal through an encoder data reading module;
step four, resolving the read encoder signals through an encoder data calculation module;
step five, generating a control signal through a PID operation module;
and step six, outputting a control signal through the SVPWM output module.
It is a further object of the present invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of the improved MSMU hardware current loop control method.
It is a further object of the present invention to provide a computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the improved MSMU hardware current loop control method.
Another object of the present invention is to provide an information data processing terminal, where the information data processing terminal is configured to implement the improved MSMU hardware current loop.
In combination with the technical scheme and the technical problems to be solved, the technical scheme to be protected has the following advantages and positive effects:
Firstly, the invention analyzes the control architecture and control performance of the current loop, and researches the electrical angle update delay in detail, and optimizes the hardware current loop by adopting an update strategy based on improved MSMU.
The invention establishes an improved MSMU hardware current loop updating strategy for updating the electric angle in real time through refining the global timer and the FPGA functional module, and delays the electric angle updating from T+delta T θ Shortening to T/N realizes the optimization of the electric angle updating delay.
Secondly, the technical scheme of the invention solves the technical problems that people always want to solve but still fail to obtain success:
in practical applications, delays due to discrete sampling are unavoidable and various errors and delays are introduced in each link of signal transmission. In order to improve the control instantaneity of the servo drive system, each module needs to be implemented in an embedded microprocessor or other programmable devices, and resource allocation, timing design and signal delay of each module are considered in detail.
Therefore, the invention provides an improved MSMU hardware current loop control strategy, and the improved MSMU hardware current loop update strategy for updating the electrical angle in real time is formulated through refining the global timer and the FPGA functional module, so that the electrical angle update is delayed from T+delta T θ Shortening to T/N, thereby realizing the optimization of the electric angle updating delay.By adopting the invention, the problem that the electric angle updating delay error becomes large under the magnetic field directional control strategy in servo drive control can be solved, the real-time performance of the current loop control of the system is effectively improved, and the control precision of the drive current is ensured.
Third, significant technical advances made in individual structural components in motor controllers cover a number of areas. The following are some important technological advances:
1. global timer:
a significant technical advance is a global timer of higher precision and stability. Timer resources in modern FPGAs and embedded systems typically have higher clock frequencies and accurate timing capabilities, enabling more accurate interrupt triggering, and thus improving the stability and accuracy of motor control.
2. And a current sampling module:
advances in ADC technology have led to current sampling becoming more accurate and fast. The high-precision analog-to-digital converter allows analog current signals to be converted into digital form more accurately, and the faster sampling rate enables more real-time current monitoring, and improves the response speed of the control system.
3. Encoder data reading and calculation module:
Significant technological advances in encoder data reading and computation modules include higher encoder pulse resolution and faster data processing capabilities. The pulse number and the resolution ratio of the modern encoder are greatly increased, so that the motor angle calculation is more accurate. Meanwhile, the high-speed parallel computing capability of the FPGA and the ASIC makes the real-time computation of the motor angle more efficient.
PID operation module:
the implementation of the PID algorithm is constantly optimized, so that the controller is more stable and rapid. The introduction of new technologies such as a self-adaptive PID control algorithm, an incremental PID control algorithm and the like enables the control response of the motor to be more flexible and has stronger adaptability.
SVPWM output module:
in terms of the SVPWM output module, the application of the efficient SVPWM algorithm and hardware acceleration techniques enables the generation of PWM signals more quickly and accurately. Hardware logic circuits are integrated inside modern FPGAs and ASICs to accelerate SVPWM operations, thereby improving the accuracy and efficiency of motor control.
In summary, the significant technical advances made by the various structural components in the motor controller involve improvements in hardware resources, improvements in data processing capabilities, and optimization of control algorithms. These technological advances have driven the development of motor controllers together, resulting in tremendous improvements in motor control in terms of accuracy, stability, and efficiency.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a FOC control module in an engineering application provided by an embodiment of the present invention;
FIG. 2 is a comparison chart of current loop update strategies provided by an embodiment of the present invention;
FIG. 3 is a diagram of a current loop control architecture based on MCU and FPGA provided by an embodiment of the invention;
FIG. 4 is a timing diagram of a hardware current loop MSMU update that takes into account angular updates provided by an embodiment of the present invention;
FIG. 5 is a comparison of an improved hardware current loop MSMU update with angular update in mind provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of q-axis current in current closed loop mode provided by an embodiment of the present invention; wherein, (a) the invention, (b) 1 current loop cycle, (c) 4 current loop cycles, (d) no treatment;
fig. 7 is a schematic diagram of a feedback speed curve in a current closed loop mode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The specific implementation scheme provided by the embodiment of the invention is as follows:
1. global timer:
implementing the global timer may be by means of a timer resource internal to the FPGA or an external clock source. The count period of the timer may be set to achieve the desired interrupt time. When the timer counts to a set value, an interrupt signal is triggered, so that a control algorithm of the current loop is executed in a fixed period.
2. And a current sampling module:
the current sampling module requires conversion of the motor current signal from analog to digital form by means of an analog-to-digital converter (ADC). The sampling rate of the ADC should be determined based on control requirements and signal frequency and will typically be set to a high enough sampling rate to ensure accurate signal sampling.
3. Encoder data reading and calculation module:
reading the encoder signal requires interfacing with the encoder, either through a counter or an input capture module. By reading the count value or the pulse number of the encoder signal, the angle information of the motor can be calculated.
PID operation module:
the PID operation module realizes a PID control algorithm, and comprises calculation of a proportional term (P), an integral term (I) and a differential term (D). The input of the PID algorithm is the current error (the difference between the set current value and the actual current value) and the output is a control signal, e.g. PWM duty cycle.
SVPWM output module:
and the SVPWM output module calculates a corresponding PWM signal according to the output of the PID operation module. The SVPWM algorithm is a modulation technology for generating three-phase alternating voltage, and can realize accurate control of a motor;
utilization of high-speed parallel characteristics of the FPGA:
the high-speed parallel characteristic of the FPGA can be realized through reasonable hardware design and parallel computation. And establishing proper data paths and control logic among the current acquisition module, the angle updating module and the trigonometric function operation module, so that the data paths and the control logic can be simultaneously calculated in the same clock period, and the operation efficiency of the whole current loop is improved.
Synchronous latching before park conversion:
synchronization of the electrical angle update with the current sampling is ensured before Park conversion is performed. The electrical angle updated values may be latched into the corresponding registers at the current sampling instants using appropriate clock synchronization and register latching techniques to ensure proper data processing.
For the actual implementation of each module, specific hardware platform and circuit design, and accuracy and performance requirements of the control algorithm need to be considered. In addition, some optimization and special treatment are required for specific application scenarios and performance requirements.
A brief implementation will be given below for each module, covering the functions and key steps of each module. Note that the actual implementation will vary with the specific hardware platform and application requirements.
1. Global timer:
implementing the global timer may be by means of a timer resource internal to the FPGA or an external clock source. The count period of the timer may be set to achieve the desired interrupt time. When the timer counts to a set value, an interrupt signal is triggered, so that a control algorithm of the current loop is executed in a fixed period.
2. And a current sampling module:
the current sampling module requires conversion of the motor current signal from analog to digital form by means of an analog-to-digital converter (ADC). The sampling rate of the ADC should be determined based on control requirements and signal frequency and will typically be set to a high enough sampling rate to ensure accurate signal sampling.
3. Encoder data reading and calculation module:
Reading the encoder signal requires interfacing with the encoder, either through a counter or an input capture module. By reading the count value or the pulse number of the encoder signal, the angle information of the motor can be calculated.
PID operation module:
the PID operation module realizes a PID control algorithm, and comprises calculation of a proportional term (P), an integral term (I) and a differential term (D). The input of the PID algorithm is the current error (the difference between the set current value and the actual current value) and the output is a control signal, e.g. PWM duty cycle.
SVPWM output module:
and the SVPWM output module calculates a corresponding PWM signal according to the output of the PID operation module. The SVPWM algorithm is a modulation technology for generating three-phase alternating voltage, and can realize accurate control of a motor;
utilization of high-speed parallel characteristics of the FPGA:
the high-speed parallel characteristic of the FPGA can be realized through reasonable hardware design and parallel computation. And establishing proper data paths and control logic among the current acquisition module, the angle updating module and the trigonometric function operation module, so that the data paths and the control logic can be simultaneously calculated in the same clock period, and the operation efficiency of the whole current loop is improved.
Synchronous latching before park conversion:
Synchronization of the electrical angle update with the current sampling is ensured before Park conversion is performed. The electrical angle updated values may be latched into the corresponding registers at the current sampling instants using appropriate clock synchronization and register latching techniques to ensure proper data processing.
For the actual implementation of each module, specific hardware platform and circuit design, and accuracy and performance requirements of the control algorithm need to be considered. In addition, some optimization and special treatment are required for specific application scenarios and performance requirements.
The implementation of the encoder data reading and calculating module involves the design of the hardware interface and the resolution of the encoder signals;
1. hardware interface design:
first, the AB phase signal of the encoder is connected to the input pin of the FPGA chip. The phase a and phase B signals of the encoder are two orthogonal square wave signals used to determine the direction and speed of rotation of the rotor.
Ab phase signal analysis:
a counter or input capture module on the FPGA chip is used to capture pulses of the AB phase signal. Each time a pulse is captured, the counter value will increase or decrease accordingly. The orthogonal encoding of the AB phase signal of the encoder can realize the increment of the counter value in the forward rotation and the decrement of the counter value in the reverse rotation.
3. And (3) angle calculation:
assuming that the AB phase signal of the encoder produces N pulses (N is typically an even number) per revolution, each pulse represents an angle of 360 degrees/N. By reading the value of the counter, the angle of the motor rotor can be calculated.
For example, assuming a counter initial value of 0, each pulse represents 1 degree (n=360), and the encoder AB phase signals acquisition of the following pulse sequence: 0,1,2,3,..n-2, N-1,0,1,2,...
When the counter value is k, the motor rotor angle is k/N x 360 degrees. For example, when the counter value is 3, the motor rotor angle is 3/360×360 degrees=3 degrees.
4. Zero calibration (optional):
in practical applications, it is often necessary to perform zero calibration, i.e. to determine the starting position of the motor rotor. The zero calibration procedure is to determine the starting position by detecting the zero signal of the encoder or a pulse of a specific sequence and calibrate the initial value of the counter accordingly.
The specific encoder interface and counter/capture module configuration varies from FPGA chip to FPGA chip and encoder model to model. Therefore, in practical design, the manual of the FPGA chip and the encoder is consulted to understand the specific interface and configuration requirements thereof, and corresponding settings and debugging are performed according to the hardware platform.
The implementation of the encoder data reading and calculating module can be divided into the following key steps:
1. hardware interface design:
first, the output signal of the encoder needs to be connected to the input pins of the FPGA chip. The encoder outputs two signals: phase a and phase B, these signals are two orthogonal square wave pulse signals. In addition, there is one Z-phase signal for zero calibration, but we don't consider the Z-phase signal here once.
2. A counter or input capture module configuration:
the FPGA chip typically has a counter or input capture module inside that can be used to capture the encoder's pulse signals. The counter is a register that can increment or decrement a count value each time a trigger signal is received. The input capture module is used for accurately capturing the time stamp of the pulse signal.
3. Signal decoding and counting:
based on the output signal of the encoder, it is possible to determine whether the motor rotates clockwise or counterclockwise. By decoding the phase a and B phases, the direction of each rotation can be obtained. The counter can record the number of pulse signals, so that the rotating angle of the motor can be tracked in real time. For example, each pulse represents an angle of 360 degrees/N, then the counter value divided by N is the angle of rotation of the motor.
4. Zero calibration (optional):
as previously mentioned, zero calibration is the determination of the starting position of the motor by detecting the zero signal of the encoder or a specific sequence of pulses. Before starting the motor or during system initialization, zero calibration can be performed, and the initial value of the counter is set to a known position, so that a mapping relation between the motor angle and the counter value is established.
The specific implementation details will be influenced by the type of FPGA chip used, the type of encoder and the application requirements. Therefore, in practical design, the manual of the FPGA chip and the encoder is consulted to understand the specific interface and configuration requirements thereof, and corresponding settings and debugging are performed according to the hardware platform.
The implementation of the encoder data reading and computation module requires that the encoder signals be connected through a hardware interface, and then the pulse signals are captured and counted in real time using a counter or input capture module. Through decoding the signals and carrying out angle calculation, the angle information of the rotation of the motor can be obtained, so that the angle control and the positioning of the motor are realized.
In practical applications, delay errors due to discrete sampling are unavoidable, and in the magnetic field steering control algorithm, the feedback signal sampling and data processing process of the current loop is shown in fig. 1. During sampling of the signal, sampling errors may be introduced. In the calculation process, precision errors and delay errors are introduced. In order to implement the modules in an embedded microprocessor or other programmable device, the resource allocation, timing design, and signal delay of the modules need to be considered in detail to achieve minimization of errors. The invention analyzes the control architecture and control performance of the current loop, and researches the electrical angle update delay in detail, and optimizes the hardware current loop by adopting an update strategy based on improved MSMU.
1. Comparison of current loop control structure schemes
The improvement of the current loop calculation frequency and the PWM carrier frequency can bring remarkable optimization to the torque control effect, but the PWM carrier frequency cannot be too high due to the limitation of the switching loss of the power module of the three-phase inverter, otherwise, the efficiency of a power device is reduced and even the power device is damaged due to heating, so the PWM frequency is generally below 20 KHz. As can be seen from fig. 1, optimizing the electrical angle update delay and the current loop calculation flow can improve torque control accuracy. Analysis of the control flow and architecture of the servo system is required.
For a single-core MCU, a timer interrupt mode is generally adopted to periodically execute control operation tasks. Its interrupt service function must be designed strictly to prevent program run time-outs. Otherwise, the control period is changed, so that the control effect is affected, and even the background program is blocked to cause accidents. If the MCU performs the control function at the timer underflow interrupt, then a single current sample and a single duty cycle update (Single Sample and Single Update, SSSU) can be performed during one carrier cycle, and the update delay of this scheme can be expressed as:
wherein T is the interrupt period of MCU, T θ To get into the time to interrupt the service function to read and calculate the trigonometric function value of the angle, t I To get into the time to interrupt the service function to run the corresponding current loop code.
For MCU with stronger operation performance, the interrupt service function can be executed in a shorter time, the timer overflow event can also be used as an interrupt source to trigger interrupt, so that in one carrier period, twice current sampling and twice duty ratio updating (Double Sample and Double Update, DSDU) can be realized, the operation frequency of a current loop is further improved, and the current loop delay and the angle updating delay are:
since the MCU is a single-core architecture, only pipeline work can be performed, and frequent interruption can cause low operation efficiency of the processor, and stability problems are easy to occur. When the FPGA is introduced, an ARM+FPGA architecture is adopted, and a magnetic field orientation control algorithm is operated through the characteristic of high-speed parallelism of the FPGA, so that a hardware current loop strategy of multiple current sampling and multiple duty ratio updating (Multiple Sample and Multiple Update, MSMU) in one carrier period can be further realized on the basis of DSDU, and the comparison of the three updating strategies is shown in figure 2. If the hardware current loop algorithm in the FPGA runs N times under one MCU interrupt, the current loop and angle update delay of the MSMU strategy can be expressed as:
The scheme of multiple current sampling and updating greatly improves the running frequency of the current loop, and improves the dynamic performance of current control. For realizing the hardware current loop, a global timer, a current acquisition module, an encoder decoding module, a current loop operation module and other modules need to be built in an FPGA by using a Very High-speed integrated circuit hardware description language (Very High-Speed Integrated Circuit Hardware Description Language, VHDL), and the structure of the modules is shown in figure 3. Because each module can independently work in parallel, a control time sequence is required to be set through the global clock module, so that each module can be executed orderly. The calculation speed of the current loop is greatly improved, and the interrupt processing of ARM is not influenced while the current loop calculation and the PWM duty ratio updating are realized for a plurality of times, so that the control efficiency is further optimized.
The current loop MSMU strategy realized by the FPGA breaks through the limitation of MCU based on the pipeline architecture, and the time sequence control is carried out on each module based on the global timer, so that the periodic execution of the current loop can be strictly realized, and the current loop operation is more stable. But it can be seen from analysis of current loop control architecture based on MCU and FPGA, where Park transform, iPark transform requires sine and cosine values of the used angle. The speed and accuracy of the angle update will affect the performance of the current loop.
After researching the angle updating strategy of the hardware current loop based on the FPGA and the MCU, the invention discovers that trigonometric function operation occupies larger scale logic resources in the FPGA, and in order to realize effective utilization of the controller resources, the trigonometric function operation is realized in the MCU with the trigonometric function fixed-point operation library function.
Since the MCU only accesses and calculates the angle data of the FPGA when the MCU is interrupted, the defect that the sine and cosine values are not updated timely is caused. When the timer is interrupted every time, the MCU controls the FPGA to trigger the encoder to update the task, calculates the angle value obtained by the encoder into a sine and cosine value in the next period, transmits the sine and cosine value to the FPGA to perform hardware current loop related operation, and when the angle update is considered, the update time sequence of the MSMU is shown in figure 4.
And when the MCU enters the underflow interrupt, the angle information obtained by the last encoder module is read from the FPGA, the next encoder updating instruction of the FPGA is triggered, and the angle data is written into a register corresponding to the FPGA after trigonometric function operation is carried out on the angle data. This process causes a delay of the angle update of more than 1 cycle.
The electrical angle of the motor is continuously changed in one control period, and Park conversion, IPark conversion and SVPWM generate mode The block uses the electrical angular position sine and cosine values obtained in the previous cycle. And the MCU lacks real-time characteristics, so that the update time of the trigonometric function value is influenced by a program, and the value is set as t θ ：
Although the multiple current loop calculations increase the bandwidth of the current loop, the angle is not updated, which results in errors between the torque current obtained by coordinate transformation and the actual torque current, and thus results in a decrease in control accuracy. As the rotational speed increases, the error between the torque current calculation value and the actual value increases gradually. And because of the multiple relation of the pole pair number between the electric angle and the mechanical angle, the motor with larger pole pair number is caused, and the critical rotating speed of the problem is lower.
2. MSMU duty cycle update based on electrical angle real-time update
Aiming at the problem that the updating of the electrical angle of a hardware current loop based on the MSMU is not timely, the invention provides an updating scheme of the duty ratio based on the improved MSMU, and the global timer function of the FPGA is re-planned so as to realize the complete real-time control of current sampling, encoder data reading, encoder data calculation, coordinate transformation, PID operation and SVPWM output module, thereby shortening the delay from the updating of the angle to the calculation of the angle and improving the control precision of the current loop. The improved MSMU duty cycle update timing diagram is shown in FIG. 5.
The improved MSMU duty ratio updating strategy refines the time sequence of angle triggering and trigonometric function calculation, and the characteristics of high-speed parallelism of the FPGA are utilized to enable the current acquisition module, the angle updating module and the trigonometric function operation module to work in parallel and to be synchronously latched to a corresponding register before Park conversion is carried out. Let N be the update times of the electrical angle in the primary speed ring period, the electrical angle update delay of the scheme is:
Δt θ ＝Δt I ＝T/N (5)
after analyzing the current loop control scheme, the invention positions the hardware current loop angle based on the MSMUThe problem of larger update delay is solved, and an improved MSMU hardware current loop update strategy for real-time update of the electrical angle is formulated through refinement of a global timer and an FPGA functional module, so that the electrical angle update is delayed from T+delta T θ Shortening to T/N, thereby realizing the optimization of the electric angle updating delay.
An application embodiment of the present invention provides a computer device including a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the improved MSMU hardware current loop control method.
An application embodiment of the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of an improved MSMU hardware current loop control method.
The embodiment of the application of the invention provides an information data processing terminal which is used for realizing an improved MSMU hardware current loop.
In order to verify the proposed improved MSMU hardware current loop technique, different electrical angle delays are set in the servo drive current closed loop mode, and the fluctuation amplitude of the electromagnetic torque is observed.
Table 1 parameters of permanent magnet synchronous motor
The permanent magnet servo motor for test and parameters are shown in table 1, and when the viscosity friction coefficient and the coulomb friction coefficient of the motor are both set to be 0, the motor is subjected to constant torque and then uniformly accelerated. The command current is set to 1A, and the current loop control period is 40kHz. P=10, i=1000 in PI controller. And (3) applying a current step signal at 0.01s, and performing uniform acceleration movement on the motor, wherein the simulation duration is 0.15s, so that the rotating speed of the motor is accelerated to about 2000 rpm. The comparative electrical angle update delays are the feedback current curves at no delay (invention), 25us (1 current loop period), 100us (4 current loop periods) and 500us (no process), respectively, and the velocity feedback curves, as shown in fig. 6 and 7, respectively.
It can be seen that after a step command is applied to the current loop, the motor starts to perform uniform acceleration motion, and the fluctuation amplitude of the feedback current is gradually increased. The waveforms of the feedback currents are substantially similar for electrical angle delays of 0, 25, 100us, respectively. But when the angular delay is 500us, the fluctuation amplitude of the feedback current becomes large, and burrs start to appear. And it can be seen from the feedback speed profile shown in fig. 3 that when the angular delay is 500us, the feedback speed is also changed considerably from the other three cases. The reason for this is that an excessively large angular delay causes a large q-axis current calculation error, and the deviation of the electromagnetic torque from the ideal state becomes large, so that the ideal speed waveform cannot be accurately followed. Test results show that the improved MSMU hardware current loop technology provided by the invention can realize that the electrical angle update is basically free from delay, can meet the requirements of a servo driving system on the electrical angle update frequency and the current loop calculation frequency, and ensures the control instantaneity.
Example 1: hardware implementation scheme of motor controller
1. Global timer:
the counting period of the timer is set to a control period, for example, 1ms, using a timer resource inside the FPGA. When the timer counts to 1ms, an interrupt is triggered.
2. And a current sampling module:
the motor current signal is sampled using a 12-bit analog-to-digital converter (ADC). An analog current signal is connected to the input pin of the ADC, and the sampling frequency of the ADC is set to 10kHz to ensure high-precision current sampling.
3. Encoder data reading and calculation module:
two external counters are used to connect the a-phase and B-phase output signals of the encoder, respectively. Each time a rising or falling edge trigger is received, the count value of the corresponding counter is incremented or decremented. In each control period, the values of the a-phase and B-phase counters are read, and then the motor angle is calculated from the encoder pulse number and resolution (e.g., n=2048).
PID operation module:
a PID controller with adjustable parameters is realized, and PID output, namely a current control signal, is calculated according to the error of the current set value and the actual current value. For example, calculate the PID output as: pid_output=kp×error+ki× integral (error) +kd× derivative (error), where Kp, ki and Kd are proportional, integral and differential gains, respectively, error is the current error.
SVPWM output module:
and according to the output current control signal of the PID operation module, a SVPWM algorithm is realized to generate a three-phase PWM signal. The PWM signal is sent to the power switching device of the motor to control the current and speed of the motor.
Example 2: implementation scheme of motor controller on embedded system
1. Global timer:
using the timer resources of the embedded system, the counting period of the timer is set to a control period, e.g. 1ms. At the end of each cycle, a timer interrupt is triggered.
2. And a current sampling module:
the motor current signal is converted to a digital signal using a built-in analog-to-digital converter (ADC). The sampling frequency of the ADC is set to 5kHz to ensure adequate accuracy.
3. Encoder data reading and calculation module:
GPIO (general purpose input output) pins are used to read the a-phase and B-phase signals of the encoder. In each control period, the states of the A-phase and B-phase signals are read, and the motor angle is calculated according to the number of encoder pulses and the resolution.
PID operation module:
the PID control algorithm is implemented in the control loop of the embedded system. And calculating a PID output signal, namely a current control signal according to the error of the current set value and the actual current value.
SVPWM output module:
and according to the output current control signal of the PID operation module, a SVPWM algorithm is realized to generate a three-phase PWM signal. And a PWM module is used for outputting PWM signals to control the current and the speed of the motor.
These two embodiments illustrate specific implementations of the motor controller under different hardware platforms. In practical applications, finer adjustments and optimizations may be made depending on the specific hardware resources, performance requirements, and cost considerations. The motor control involves the cooperative work of a plurality of modules, so that the problems of time sequence, data transmission and the like among the modules are required to be considered in the implementation process, so that the stability and the accuracy of the motor control are ensured.
It should be noted that the embodiments of the present invention can be realized in hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or special purpose design hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such as provided on a carrier medium such as a magnetic disk, CD or DVD-ROM, a programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The device of the present invention and its modules may be implemented by hardware circuitry, such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., as well as software executed by various types of processors, or by a combination of the above hardware circuitry and software, such as firmware.
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.
Claims (10)
1. An improved MSMU hardware current loop, comprising:
a global timer for controlling the interrupt time;
the current sampling module is used for sampling the signals;
an encoder data reading module for reading the encoder signal;
the encoder data calculation module is used for calculating the read encoder signals;
the PID operation module is used for realizing accurate control of the motor;
and the SVPWM output module is used for outputting a control signal.
2. An improved MSMU hardware current loop as recited in claim 1, comprising:
global timer:
the realization of the global timer can be realized by means of timer resources or external clock sources inside the FPGA; the counting period of the timer can be set to realize the required interrupt time; when the timer counts to a set value, an interrupt signal is triggered, so that a control algorithm of the current loop is executed in a fixed period;
And a current sampling module:
the current sampling module is used for converting the motor current signal from an analog form to a digital form by means of an analog-to-digital converter; the sampling rate of the ADC should be determined based on control requirements and signal frequency, and will typically be set to a high enough sampling rate to ensure accurate signal sampling;
encoder data reading and calculation module:
the signal of the encoder needs to be read and connected with the encoder through a counter or an input capturing module; by reading the count value or the pulse number of the encoder signal, the angle information of the motor can be calculated;
PID operation module:
the PID operation module realizes a PID control algorithm, and comprises calculation of a proportional term (P), an integral term (I) and a differential term (D); the input of the PID algorithm is a current error (the difference between a set current value and an actual current value), and the output is a control signal;
SVPWM output module:
the SVPWM output module calculates a corresponding PWM signal according to the output of the PID operation module; the SVPWM algorithm is a modulation technology for generating three-phase alternating voltage, and can realize accurate control of a motor;
utilization of high-speed parallel characteristics of the FPGA:
the high-speed parallel characteristic of the FPGA can be realized through reasonable hardware design and parallel calculation; a proper data path and control logic are established among the current acquisition module, the angle updating module and the trigonometric function operation module, so that the current acquisition module, the angle updating module and the trigonometric function operation module can calculate simultaneously in the same clock period, and the operation efficiency of the whole current loop is improved;
Synchronous latching before Park conversion:
before Park conversion is carried out, synchronization of electrical angle updating and current sampling is ensured; the electrical angle updated values may be latched into the corresponding registers at the current sampling instants using appropriate clock synchronization and register latching techniques to ensure proper data processing.
3. The improved MSMU hardware current loop of claim 1 wherein the implementation of the encoder data reading and computation module involves design of the hardware interface and parsing of the encoder signal specifically comprises:
1) Hardware interface design:
firstly, an AB phase signal of an encoder is connected to an input pin of an FPGA chip; the phase A and the phase B of the encoder are two orthogonal square wave signals, and are used for determining the rotation direction and the rotation speed of the rotor;
2) AB phase analysis:
the counter or the input capturing module on the FPGA chip is used for capturing pulses of the AB phase signals; each time a pulse is captured, the counter value will increase or decrease accordingly; the AB phase signal of the encoder is orthogonally encoded, so that the counter value can be increased in the forward rotation and decreased in the reverse rotation;
3) And (3) angle calculation:
assuming that the AB phase signal of the encoder generates N pulses per revolution, each pulse represents an angle of 360 degrees/N; by reading the value of the counter, the angle of the motor rotor can be calculated;
When the counter value is k, the motor rotor angle is k/N x 360 degrees; for example, when the counter value is 3, the motor rotor angle is 3/360×360 degrees=3 degrees;
4) Zero calibration:
the zero calibration process is to determine the initial position by detecting the zero signal of the encoder or the pulse of a specific sequence and calibrate the initial value of the counter correspondingly;
the specific encoder interface and counter/capture module configuration varies from FPGA chip to FPGA chip and encoder model to model.
4. The improved MSMU hardware current loop of claim 1 wherein the implementation of the encoder data reading and computation module comprises the steps of:
1) Hardware interface design:
connecting an output signal of the encoder to an input pin of the FPGA chip;
2) A counter or input capture module configuration:
a counter or an input capturing module is usually arranged in the FPGA chip and can be used for capturing pulse signals of the encoder; increasing or decreasing the count value each time a trigger signal is received; the input capturing module is used for capturing the time stamp of the pulse signal accurately;
3) Signal decoding and counting:
judging whether the motor rotates clockwise or anticlockwise according to the output signal of the encoder; the direction of each rotation is obtained by decoding the phase A and the phase B; the counter can record the number of pulse signals, so that the rotating angle of the motor can be tracked in real time;
4) Zero calibration:
zero calibration is to determine the starting position of the motor by detecting the zero signal of the encoder or a pulse of a specific sequence; before starting the motor or during system initialization, zero calibration can be performed, and the initial value of the counter is set to a known position, so that a mapping relation between the motor angle and the counter value is established.
5. The improved MSMU hardware current loop of claim 1 wherein the current acquisition module, angle update and trigonometric function operation module are operated in parallel by utilizing the high speed parallelism feature of the FPGA and latched in synchronization to the corresponding registers prior to Park conversion.
6. The improved MSMU hardware current loop of claim 1 wherein, assuming N is the number of updates of the electrical angle in a single speed loop cycle, the electrical angle update delay is: Δt (delta t) θ ＝Δt I ＝T/N。
7. An improved MSMU hardware current loop control method using the improved MSMU hardware current loop of any one of claims 1-6, comprising:
step one, setting interrupt time through a global timer;
step two, sampling the signal through a current sampling module;
Step three, reading the encoder signal through an encoder data reading module;
step four, resolving the read encoder signals through an encoder data calculation module;
step five, generating a control signal through a PID operation module;
and step six, outputting a control signal through the SVPWM output module.
8. A computer device comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the improved MSMU hardware current loop control method of claim 7.
9. A computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the improved MSMU hardware current loop control method of claim 7.
10. An information data processing terminal for implementing an improved MSMU hardware current loop as claimed in any one of claims 1 to 6.
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