CN212433614U - Multi-axis motor pipeline control system based on FPGA - Google Patents
Multi-axis motor pipeline control system based on FPGA Download PDFInfo
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Abstract
The utility model relates to a multi-axis motor assembly line control system based on FPGA, which comprises a motor operation circuit, an assembly line control circuit, a multi-path data acquisition circuit, a multi-path interface circuit and a multi-path modulation output circuit; all the data acquisition feedback circuits, all the interface circuits and all the modulation output circuits are electrically connected with the motor arithmetic circuit respectively, and all the data acquisition feedback circuits, all the interface circuits and all the modulation output circuits are electrically connected with the production line control circuit respectively. The utility model discloses no matter how many motor shafts, all only need a motor operation circuit to the mode of assembly line realizes multiaxis motor parallel control, reduces FPGA and occupies the resource manyfold, saves the chip cost greatly.
Description
Technical Field
The utility model relates to a motor control technical field, in particular to multi-axis motor assembly line control system based on FPGA.
Background
An AC servo permanent magnet synchronous motor is an electromagnetic machine with a position operation feedback device. The motor is controlled by the servo driving device, displacement output and digital command position input are strictly synchronous, the control precision is high, the control is simple, the starting and stopping are rapid, the performance is stable, and the servo motor is widely applied to the fields of numerical control systems, robots and the like. With the deep development of industrial automation, more and more devices need to be matched with each other by a plurality of axes to complete the motion control of the space trajectory, such as a multi-axis machining center, a multi-joint manipulator and other devices. How to cooperatively control motors on various shafts and an implementation method thereof are problems to be researched and solved by a multi-shaft motor controller.
For the control of a multi-axis motor, a pure software method is adopted for a microprocessor based on an MCU or a DSP and the like in the prior art, but the software-based method is easy to generate lag, the real-time performance of motor control is reduced, and the control performance of a multi-axis motor control system is reduced. Therefore, a pure hardware logic implementation based on FPGA appears, as shown in fig. 1, which is a multi-axis parallel control system for an FPGA motor in the prior art, and a single FPGA chip is used to control a plurality of motors to operate independently, including a multi-path data acquisition circuit 1, a multi-path interface circuit 2, a multi-path motor operation circuit 3, and a multi-path modulation output circuit 4. The multi-path data acquisition circuit 1 is a sampling circuit from a first shaft motor, a second shaft motor to an nth shaft motor, wherein the acquired data comprises phase current data, position data and speed data; the multi-path interface circuit 2 is specifically a control instruction input interface circuit from a first shaft motor, a second shaft motor to an nth shaft motor, wherein the control instruction comprises a position request instruction, a system synchronization instruction, a control parameter issuing instruction and the like; the multi-path motor operation circuit 3 is specifically a calculation circuit from a first shaft motor, a second shaft motor to an nth shaft motor, wherein calculated data comprise errors and adjustment quantities of positions, errors and adjustment quantities of speeds and errors and adjustment quantities of currents; the multi-path modulation output circuit 4 is specifically an U, V, W three-phase duty ratio output circuit from the first shaft motor, the second shaft motor to the nth shaft motor.
In the existing FPGA motor multi-axis parallel control system, each axis motor can realize parallel control by independently calculating logic by using a data acquisition circuit, an instruction input circuit and a motor operation circuit of each channel, and all axes are not influenced by each other. However, the control system needs a motor operation circuit, so that the FPGA calculation logic needs to be occupied repeatedly, resource waste is caused, chip cost is increased, and the requirement on an FPGA chip is high.
SUMMERY OF THE UTILITY MODEL
The utility model provides a multiaxis motor assembly line control system based on FPGA has solved and has adopted a plurality of motor operation circuits among the prior art, and repeated FPGA computational logic that occupies causes the wasting of resources, the technical problem of chip cost increase.
The utility model provides an above-mentioned technical problem's technical scheme as follows:
a multi-axis motor assembly line control system based on FPGA comprises a motor operation circuit, an assembly line control circuit, a multi-path data acquisition circuit, a multi-path interface circuit and a multi-path modulation output circuit which are arranged on an FPGA programmable logic device;
the number of the data acquisition circuits, the number of the interface circuits and the number of the modulation output circuits are the same;
the motor arithmetic circuit, the assembly line control circuit, all the data acquisition circuits, all the interface circuits and all the modulation output circuits are respectively and electrically connected with the FPGA programmable logic device, all the data acquisition circuits, all the interface circuits and all the modulation output circuits are respectively and electrically connected with the motor arithmetic circuit, and all the data acquisition circuits, all the interface circuits and all the modulation output circuits are respectively and electrically connected with the assembly line control circuit;
the assembly line control circuit provides a first time sequence and a second time sequence, output data of all the data acquisition circuits and output data of all the interface circuits are input into the motor operation circuit in an assembly line mode polling mode according to the first time sequence, and all the modulation output circuits receive the output data of the motor operation circuit in an assembly line mode polling mode according to the second time sequence.
The utility model has the advantages that: the data acquisition circuit is used for acquiring sampling data of the motor shaft; the interface circuit is used for acquiring a motor motion control instruction of a motor shaft; the pipeline control circuit is used for providing a first time sequence, and the sampling data and the motor motion control instructions of all the motor shafts are input into the motor arithmetic circuit in a pipeline mode in a polling mode according to the first time sequence; the motor operation circuit is used for calculating error adjusting data of each motor shaft according to the sampling data and the motor motion control instruction input according to the first time sequence; the pipeline control circuit is also used for providing a second time sequence, and all the modulation output circuits poll and receive error regulation data of the corresponding motor shaft in a pipeline mode according to the second time sequence; the modulation output circuit is used for receiving error regulation data of the corresponding motor shaft according to a second time sequence, calculating a three-phase duty ratio modulation signal of the corresponding motor shaft according to the error regulation data and outputting the three-phase duty ratio modulation signal to the corresponding motor; therefore, the data input into the motor arithmetic circuit by the data acquisition circuit (namely, the output data of the data acquisition circuit) is the sampling data of the motor shaft, and the data input into the motor arithmetic circuit by the interface circuit (namely, the output data of the interface circuit) is the motor motion control instruction of the motor shaft; based on an FPGA chip, a three-phase duty ratio modulation signal (namely a PWM modulation signal) of each motor is obtained through a data acquisition circuit, an interface circuit, a production line control circuit, a motor operation circuit and a modulation output circuit and is output to the motors of corresponding channels, so that the parallel control of the multi-shaft motors is realized;
the utility model discloses a multiaxis motor control system, based on the assembly line logic (including first chronogenesis and second chronogenesis) that FPGA programmable logic device and assembly line control circuit provided, with the mode of assembly line with sampling data and motor motion control instruction input, with the mode of assembly line with PWM modulation signal output again, no matter how many motor shafts, all only need a motor operation circuit, compare with traditional multiaxis motor parallel control method, reduce FPGA and occupy the resource manyly, save chip cost greatly, the requirement to the FPGA chip is lower.
On the basis of the technical scheme, the utility model discloses there is following improvement in addition:
further: each data acquisition circuit comprises an encoder and a current sensor;
in any one of the data acquisition circuits, the encoder and the current sensor are respectively and electrically connected with the motor operation circuit, the encoder and the current sensor are respectively and electrically connected with the assembly line control circuit, and the encoder and the current sensor are respectively and electrically connected with the FPGA programmable logic device.
The beneficial effects of the further technical scheme are as follows: the encoder is used for conveniently acquiring position data and speed data of a channel where each motor shaft is located, the motor operation circuit is used for conveniently acquiring position feedback data, position errors and the like according to the position data, the motor operation circuit is used for conveniently acquiring related data such as speed feedback data, speed errors and the like according to the speed data, the current sensor is used for conveniently acquiring phase current data input by the channel where each motor shaft is located, and further the related data such as current errors, current error regulation data and the like are conveniently acquired; the encoder and the current sensor are respectively electrically connected with the assembly line control circuit, so that the encoder and the current sensor can be conveniently input into the motor operation circuit in an assembly line mode for calculation according to the provided first time sequence, and the occupation resource of the FPGA is effectively reduced on the basis of accurately calculating current error adjusting data.
Further: the motor operation circuit comprises a position feedback calculation sub-circuit, a position error calculation sub-circuit, a position regulation sub-circuit, a speed feedback calculation sub-circuit, a speed error calculation sub-circuit, a speed regulation sub-circuit, a current feedback calculation sub-circuit, a current error calculation sub-circuit and a current regulation sub-circuit;
the position error calculation sub-circuit is electrically connected with the current regulation sub-circuit through the position regulation sub-circuit, the speed error calculation sub-circuit, the position regulation sub-circuit and the current error calculation sub-circuit in sequence, the output ends of all the interface circuits are respectively and electrically connected with the position error calculating sub-circuit, the output ends of all the modulation output circuits are respectively and electrically connected with the current regulating sub-circuit, the output ends of all the encoders are respectively and electrically connected with the position error calculating sub-circuit through the position feedback calculating sub-circuit, the output ends of all the encoders are also respectively and electrically connected with the speed error calculating sub-circuit through the speed feedback calculating sub-circuit, and the output ends of all the current sensors are respectively and electrically connected with the current error calculating sub-circuit through the current feedback calculating sub-circuit; the position feedback computing sub-circuit, the position error computing sub-circuit, the position adjusting sub-circuit, the speed feedback computing sub-circuit, the speed error computing sub-circuit, the speed adjusting sub-circuit, the current feedback computing sub-circuit, the current error computing sub-circuit and the current adjusting sub-circuit are respectively and electrically connected with the FPGA programmable logic device.
The beneficial effects of the further technical scheme are as follows: the position feedback calculating sub-circuit is used for calculating position feedback data corresponding to the motor shaft according to the position data input according to the first time sequence; the position error calculation sub-circuit is used for calculating and obtaining the position error of the corresponding motor shaft according to the motor motion control command input in the first time sequence and the position feedback data; the position adjusting sub-circuit is used for obtaining position error adjusting data corresponding to the motor shaft according to the position error; the speed feedback calculating sub-circuit is used for calculating speed feedback data corresponding to the motor shaft according to the speed data input according to the first time sequence; the speed error calculation sub-circuit is used for calculating the speed error of the corresponding motor shaft according to the speed feedback data and the position error adjusting data; the speed regulating sub-circuit is used for obtaining speed error regulating data corresponding to the motor shaft according to the speed error; the current feedback calculation sub-circuit is used for calculating current feedback data corresponding to the motor shaft according to the phase current data input according to the first time sequence; the current error calculation sub-circuit is used for calculating and obtaining the current error of the corresponding motor shaft according to the current feedback data and the speed error adjusting data; the current regulating sub-circuit is used for obtaining current error regulating data corresponding to the motor shaft according to the current error;
under the pipeline logic provided by the pipeline control circuit, when the data acquisition circuit and the interface circuit input position data, speed data and current data of a certain motor shaft and a motor motion control instruction corresponding to the shaft according to a first time sequence, a position feedback sub-circuit in the motor operation circuit obtains position feedback data according to the position data, then a position error calculation sub-circuit calculates a position error of the corresponding motor shaft according to the position feedback data and the motor motion control instruction (such as the position control instruction, a system set position parameter and the like), and then a position error adjusting sub-circuit obtains corresponding position error adjusting data according to the position error, wherein the three circuit structures form a position error adjusting ring; the position error regulation is transmitted to a subsequent serial node, namely a node for speed error regulation, similarly, the speed feedback calculation sub-circuit calculates speed feedback data according to the speed data, the speed error calculation sub-circuit obtains a speed error according to the speed feedback data and the position error regulation data transmitted by the previous node, and the speed regulation sub-circuit obtains corresponding speed error regulation data according to the speed error, namely the speed feedback calculation sub-circuit, the speed error calculation sub-circuit and the speed regulation sub-circuit form a speed error regulation ring; the speed error regulation data is transmitted to a following serial node, namely a current error regulation node, and similarly, a current error regulation ring is formed through a current feedback calculation sub-circuit, a current error calculation sub-circuit and a current regulation sub-circuit to obtain input current error regulation data corresponding to a motor shaft;
through the motor operational circuit of above-mentioned structure, can calculate current error adjustment data to the signal of inputing according to first time sequence, the modulation output circuit of being convenient for is according to the second time sequence to the current error adjustment data of output is polled periodically to the mode of assembly line, and then the modulation output circuit of being convenient for acquires the three-phase duty ratio modulation signal of corresponding motor shaft, realize the parallel control to the multiaxis motor with the mode of assembly line, no matter how many motor shafts, only need the motor operational circuit of an above-mentioned structure, FPGA occupation resource has been reduced greatly.
Further: the first time sequence comprises input pulse periods and input sequence of output data of all the data acquisition circuits and output data of all the interface circuits, which are input into the motor operation circuit in a polling mode in a pipeline mode, and input pulse intervals of output data of the data acquisition circuits of every two adjacent channels and output data of the interface circuits of every two adjacent channels, which are input into the motor operation circuit in a polling mode in a pipeline mode;
the second time sequence comprises output pulse periods and output sequence of output data of all the modulation output circuits in a pipeline mode in a polling mode, and output pulse intervals of output data of the motor operation circuits in a pipeline mode in a polling mode by the modulation output circuits of every two adjacent channels;
the input pulse period is equal to the output pulse period, the input pulse interval is equal to the output pulse interval, the input sequence is equal to the output sequence, and the input sequence and the output sequence are respectively equal to the motor shaft number sequencing.
The beneficial effects of the further technical scheme are as follows: distributing the input sequence of sampling data and motor motion control instructions of all channels to be input into a motor operation circuit according to the motor shaft number sequencing, and distributing the output sequence of error regulation data of all channels to be received by a modulation output circuit according to the motor shaft number sequencing, so that the input of a production line and the output of the production line correspond to a motor shaft respectively and keep synchronization, and further ensuring that input signals (namely sampling data and motor motion control instructions) and output signals (namely three-phase duty ratio modulation signals or PWM modulation signals) are the same motor and are input and output in sequence in a production line mode; the input pulse period is equal to the output pulse period, the input pulse interval is equal to the output pulse interval, the input sequence is equal to the output sequence, and the input sequence and the output sequence are respectively equal to the sequencing of the motor shaft numbers.
Drawings
FIG. 1 is a schematic structural diagram of a multi-axis parallel control system of an FPGA motor in the prior art;
fig. 2 is a schematic structural diagram of a multi-axis motor assembly line control system based on an FPGA according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another FPGA-based multi-axis motor assembly line control system according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a motor operation circuit according to an embodiment of the present invention;
fig. 5 is a circuit diagram of an embodiment of the present invention, in which the pipeline control circuit controls the pipeline inputs of the data acquisition circuit and the interface circuit, and controls the pipeline output of the modulation output circuit;
fig. 6 is a schematic diagram of a model of a first timing sequence and a second timing sequence provided by the pipeline control circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a deformation structure of the multi-axis motor assembly line control system based on the FPGA in the embodiment of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
1. the device comprises a data acquisition circuit, a data acquisition interface circuit, a data acquisition circuit, a motor operation circuit, a data acquisition circuit, a modulation output circuit, a data acquisition pipeline control circuit, a data acquisition encoder, a data acquisition interface circuit, a data acquisition.
Detailed Description
The principles and features of the present invention are described below in conjunction with the following drawings, the examples given are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.
The present invention will be described with reference to the accompanying drawings.
In an embodiment, as shown in fig. 2, a multi-axis motor pipeline control system based on an FPGA includes a motor operation circuit 3, a pipeline control circuit 5, a multi-path data acquisition circuit 1, a multi-path interface circuit 2, and a multi-path modulation output circuit 4, which are arranged on an FPGA programmable logic device;
the number of the data acquisition circuits 1, the number of the interface circuits 2 and the number of the modulation output circuits 4 are the same;
the motor arithmetic circuit 3, the pipeline control circuit 5, all the data acquisition circuits 1, all the interface circuits 2 and all the modulation output circuits 4 are respectively and electrically connected with the FPGA programmable logic device, all the data acquisition circuits 1, all the interface circuits 2 and all the modulation output circuits 4 are respectively and electrically connected with the motor arithmetic circuit 3, and all the data acquisition circuits 1, all the interface circuits 2 and all the modulation output circuits 4 are respectively and electrically connected with the pipeline control circuit 5;
the pipeline control circuit 5 provides a first time sequence and a second time sequence, the output data of all the data acquisition circuits 1 and the output data of all the interface circuits 2 are polled and input into the motor arithmetic circuit 3 in a pipeline mode according to the first time sequence, and all the modulation output circuits 4 are polled and received in the pipeline mode according to the second time sequence, wherein the output data of the motor arithmetic circuit 3 are output by the modulation output circuits 4.
The embodiment provides a pure hardware multi-axis motor control system based on an FPGA chip, which is characterized in that sampling data of a channel where each motor is located is obtained through a data acquisition circuit, a motor motion control instruction is obtained through an interface circuit, a first time sequence of data input each time in a motor operation circuit is provided through a production line control circuit, namely, the sampling data of all motor shafts and the motor motion control instruction are input into the motor operation circuit in a polling mode in a production line mode according to the first time sequence; the motor arithmetic circuit can calculate error adjustment data of a channel corresponding to the data input each time according to the sampling data input each time and the motor motion control instruction; providing a second time sequence of data output every time in the motor operation circuit through the pipeline control circuit, namely polling and receiving error adjusting data of a corresponding motor shaft by all modulation output circuits in a pipeline mode according to the second time sequence; finally, the modulation output circuit of the channel where each motor is located calculates a corresponding three-phase duty ratio modulation signal (namely a PWM modulation signal) according to the corresponding error regulation data and outputs the three-phase duty ratio modulation signal to the motor of the corresponding channel, so that the parallel control of the multi-axis motor is realized;
the multi-axis motor control system of the embodiment inputs sampling data and motor motion control instructions in a pipeline mode based on pipeline logic (including a first time sequence and a second time sequence) provided by the FPGA programmable logic device and the pipeline control circuit, and outputs PWM modulation signals in a pipeline mode.
Specifically, as shown in fig. 2, the data acquisition circuits share N paths, and the numbers thereof are N1 and N2 … … NN, respectively, and similarly, the numbers of the interface circuit and the modulation output circuit are N1 and N2 … … NN, respectively, and the order of the numbers is the same as the order of the motor shaft numbers.
Preferably, as shown in fig. 3, each of the data acquisition circuits 1 includes an encoder 11 and a current sensor 12;
in any one of the data acquisition circuits 1, the encoder 11 and the current sensor 12 are respectively electrically connected with the motor arithmetic circuit 3, the encoder 11 and the current sensor 12 are respectively electrically connected with the pipeline control circuit 5, and the encoder 11 and the current sensor 12 are respectively electrically connected with the FPGA programmable logic device.
The encoder is used for conveniently acquiring position data and speed data of a channel where each motor shaft is located, the motor operation circuit is used for conveniently acquiring position feedback data, position errors and the like according to the position data, the motor operation circuit is used for conveniently acquiring related data such as speed feedback data, speed errors and the like according to the speed data, the current sensor is used for conveniently acquiring phase current data input by the channel where each motor shaft is located, and further the related data such as current errors, current error regulation data and the like are conveniently acquired; the encoder and the current sensor are respectively electrically connected with the assembly line control circuit, so that the encoder and the current sensor can be conveniently input into the motor operation circuit in an assembly line mode for calculation according to the provided first time sequence, and the occupation resource of the FPGA is effectively reduced on the basis of accurately calculating current error adjusting data.
Specifically, in any modulation output circuit of the present embodiment, the output three-phase duty ratio modulation output signals include U-phase PWM modulation signals (i.e., PWM _ U _ N1, PWM _ U _ N2 … … PWM _ U _ NN in fig. 3), V-phase PWM modulation signals (i.e., PWM _ V _ N1, PWM _ V _ N2 … … PWM _ V _ NN in fig. 3), and W-phase PWM modulation signals (i.e., PWM _ W _ N1, PWM _ W _ N2 … … PWM _ W _ NN in fig. 3); in any one of the data acquisition circuits of the present embodiment, the phase current data acquired by the current sensor includes a U-phase input phase current and a V-phase input phase current.
Preferably, as shown in fig. 4, the motor operation circuit 3 includes a position feedback calculation sub-circuit 31, a position error calculation sub-circuit 32, a position adjustment sub-circuit 33, a speed feedback calculation sub-circuit 34, a speed error calculation sub-circuit 35, a speed adjustment sub-circuit 36, a current feedback calculation sub-circuit 37, a current error calculation sub-circuit 38, and a current adjustment sub-circuit 39;
the position error calculation sub-circuit 32 is electrically connected to the current adjustment sub-circuit 39 through the position adjustment sub-circuit 33, the velocity error calculation sub-circuit 35, the position adjustment sub-circuit 33, and the current error calculation sub-circuit 38 in this order, the output terminals of all the interface circuits 2 are electrically connected to the position error calculating sub-circuit 32, the output terminals of all the modulation output circuits 4 are electrically connected to the current regulating sub-circuit 39, the output terminals of all the encoders 11 are electrically connected to the position error calculating sub-circuit 32 through the position feedback calculating sub-circuit 31, the output terminals of all the encoders 11 are electrically connected to the speed error calculating sub-circuit 35 through the speed feedback calculating sub-circuit 34, and the output terminals of all the current sensors 12 are electrically connected to the current error calculating sub-circuit 38 through the current feedback calculating sub-circuit 37; the position feedback calculation sub-circuit 31, the position error calculation sub-circuit 32, the position adjustment sub-circuit 33, the velocity feedback calculation sub-circuit 34, the velocity error calculation sub-circuit 35, the velocity adjustment sub-circuit 36, the current feedback calculation sub-circuit 37, the current error calculation sub-circuit 38, and the current adjustment sub-circuit 39 are electrically connected to the FPGA programmable logic device, respectively.
In this embodiment, the position feedback calculating sub-circuit is configured to calculate position feedback data corresponding to the motor shaft based on the position data input according to the first timing sequence; the position error calculation sub-circuit is used for calculating and obtaining the position error of the corresponding motor shaft according to the motor motion control command input in the first time sequence and the position feedback data; the position adjusting sub-circuit is used for obtaining position error adjusting data corresponding to the motor shaft according to the position error; the speed feedback calculating sub-circuit is used for calculating speed feedback data corresponding to the motor shaft according to the speed data input according to the first time sequence; the speed error calculation sub-circuit is used for calculating the speed error of the corresponding motor shaft according to the speed feedback data and the position error adjusting data; the speed regulating sub-circuit is used for obtaining speed error regulating data corresponding to the motor shaft according to the speed error; the current feedback calculation sub-circuit is used for calculating current feedback data corresponding to the motor shaft according to the phase current data input according to the first time sequence; the current error calculation sub-circuit is used for calculating and obtaining the current error of the corresponding motor shaft according to the current feedback data and the speed error adjusting data; and the current regulating sub-circuit is used for obtaining current error regulating data corresponding to the motor shaft according to the current error.
Under the pipeline logic provided by the pipeline control circuit, when the data acquisition circuit and the interface circuit input position data, speed data and current data of a certain motor shaft and a motor motion control instruction corresponding to the shaft according to a first time sequence, a position feedback sub-circuit in the motor operation circuit obtains position feedback data according to the position data, then a position error calculation sub-circuit calculates a position error of the corresponding motor shaft according to the position feedback data and the motor motion control instruction (such as the position control instruction, a system set position parameter and the like), and then a position error adjusting sub-circuit obtains corresponding position error adjusting data according to the position error, wherein the three circuit structures form a position error adjusting ring; the position error regulation is transmitted to a subsequent serial node, namely a node for speed error regulation, similarly, the speed feedback calculation sub-circuit calculates speed feedback data according to the speed data, the speed error calculation sub-circuit obtains a speed error according to the speed feedback data and the position error regulation data transmitted by the previous node, and the speed regulation sub-circuit obtains corresponding speed error regulation data according to the speed error, namely the speed feedback calculation sub-circuit, the speed error calculation sub-circuit and the speed regulation sub-circuit form a speed error regulation ring; the speed error regulation data is transmitted to a following serial node, namely a current error regulation node, and similarly, a current error regulation ring is formed through a current feedback calculation sub-circuit, a current error calculation sub-circuit and a current regulation sub-circuit to obtain input current error regulation data corresponding to a motor shaft;
through the motor operational circuit of above-mentioned structure, can calculate current error adjustment data to the signal of inputing according to first time sequence, the modulation output circuit of being convenient for is according to the second time sequence to the current error adjustment data of output is polled periodically to the mode of assembly line, and then the modulation output circuit of being convenient for acquires the three-phase duty ratio modulation signal of corresponding motor shaft, realize the parallel control to the multiaxis motor with the mode of assembly line, no matter how many motor shafts, only need the motor operational circuit of an above-mentioned structure, FPGA occupation resource has been reduced greatly.
Specifically, the motor motion control instruction in this embodiment includes a position request instruction, a system synchronization instruction, a current instruction, a control parameter issue instruction, and the like, for example, the number of motor shafts, motor parameters, control parameters, and the like; the interface circuit can be used as an input interface of the control instructions, the number of motor shafts, motor parameters, control parameters and the like can be configured through the interface circuit, and meanwhile, the interface circuit can also be used as a state parameter monitoring output interface, for example, the interface circuit can output state parameters such as current magnitude, speed magnitude, actual operation position feedback and alarm information.
It should be noted that, the specific calculation formulas of the position feedback calculation sub-circuit calculating position feedback data, the position error calculation sub-circuit calculating position error, the position adjustment sub-circuit calculating position error adjusting data, the speed feedback calculation sub-circuit calculating speed feedback data, the speed error calculation sub-circuit calculating speed error, the speed adjustment sub-circuit calculating speed error adjusting data, the current feedback calculation sub-circuit calculating current feedback data, the current error calculation sub-circuit calculating current error and the current adjustment sub-circuit calculating current error adjusting data in the present invention are the prior art, and the specific circuit structure corresponding to each sub-circuit is the common circuit structure in the motor operation circuit of the conventional technology shown in fig. 1, the present invention improves the structure of the whole multi-axis motor assembly line control system based on the FPGA only based on the known common knowledge of the FPGA chip and the motor control, the parallel control of the multi-axis motor with smaller occupied resources and lower chip cost is realized, the improvement of a computer program is not related, and the specific details are not described again.
Preferably, the first timing sequence includes input pulse periods and input sequence in which all the output data of the data acquisition circuits 1 and all the output data of the interface circuits 2 are polled and input into the motor operation circuit 3 in a pipeline manner, and input pulse intervals in which the output data of the data acquisition circuits 1 of every two adjacent channels and the output data of the interface circuits 2 of every two adjacent channels are polled and input into the motor operation circuit 3 in a pipeline manner;
the second time sequence comprises output pulse periods and output sequence of output data of the motor operation circuit 3 polled and received by all the modulation output circuits 4 in a pipeline mode, and output pulse intervals of output data of the motor operation circuit 3 polled and received by the modulation output circuits 4 of every two adjacent channels in a pipeline mode;
the input pulse period is equal to the output pulse period, the input pulse interval is equal to the output pulse interval, the input sequence is equal to the output sequence, and the input sequence and the output sequence are respectively equal to the motor shaft number sequencing.
Distributing the input sequence of sampling data and motor motion control instructions of all channels to be input into a motor operation circuit according to the motor shaft number sequencing, and distributing the output sequence of error regulation data of all channels to be received by a modulation output circuit according to the motor shaft number sequencing, so that the input of a production line and the output of the production line correspond to a motor shaft respectively and keep synchronization, and further ensuring that input signals (namely sampling data and motor motion control instructions) and output signals (namely three-phase duty ratio modulation signals or PWM modulation signals) are the same motor and are input and output in sequence in a production line mode; the input pulse period is equal to the output pulse period, the input pulse interval is equal to the output pulse interval, the input sequence is equal to the output sequence, and the input sequence and the output sequence are respectively equal to the sequencing of the motor shaft numbers.
Specifically, a circuit diagram of the present embodiment, in which the pipeline control circuit is used to control pipeline inputs of the data acquisition circuit and the interface circuit, and to control a pipeline output of the modulation output circuit, is shown in fig. 5. A model diagram of the first timing and the second timing provided by the pipeline control circuit is shown in fig. 6.
When the motor shaft numbers are respectively No. 1, No. 2, No. … … and No. n, the first time sequence provided by the pipeline control circuit is specifically as follows: the input pulse period is T, the input pulse interval is T/n, and the input sequence is respectively the sampling data and the motor motion control instruction of the No. 1 motor shaft, the sampling data and the motor motion control instruction of the No. 2 motor shaft, … … and the sampling data and the motor motion control instruction of the No. n motor shaft; the second time sequence provided by the pipeline control circuit is specifically as follows: the output pulse period is T, the output pulse interval is T/n, the output sequence is that a modulation output circuit corresponding to the No. 1 motor shaft receives the current error adjustment data, a modulation output circuit corresponding to the No. 2 motor shaft receives the current error adjustment data, … … and a modulation output circuit corresponding to the No. n motor shaft receives the current error adjustment data.
The specific process is as follows: when a first pulse arrives, starting a data acquisition circuit and an interface circuit corresponding to the No. 1 motor shaft, inputting sampling data of the No. 1 motor shaft and a motor motion control instruction into a motor arithmetic circuit, calculating corresponding current error adjustment data by the motor arithmetic circuit, starting a modulation output circuit corresponding to the No. 1 motor shaft, receiving the data by the modulation output circuit corresponding to the No. 1 motor shaft, calculating a corresponding PWM modulation signal, and outputting the PWM modulation signal to the No. 1 motor; when the second pulse arrives, starting a data acquisition circuit and an interface circuit corresponding to the No. 2 motor shaft, inputting the sampling data of the No. 2 motor shaft and a motor motion control instruction into a motor arithmetic circuit, calculating corresponding current error adjustment data by the motor arithmetic circuit, starting a modulation output circuit corresponding to the No. 2 motor shaft, receiving the data by the modulation output circuit corresponding to the No. 2 motor shaft, calculating a corresponding PWM modulation signal, and outputting the PWM modulation signal to the No. 2 motor; … …, repeating the steps until the last pulse of a period T comes, starting a data acquisition circuit and an interface circuit corresponding to the n motor shafts, inputting the sampled data of the n motor shafts and a motor motion control command to a motor arithmetic circuit, calculating corresponding current error regulation data by the motor arithmetic circuit, starting a modulation output circuit corresponding to the n motor shafts, receiving the data and calculating corresponding PWM modulation signals by the modulation output circuit corresponding to the n motor shafts, and outputting the PWM modulation signals to the n motor shafts; and the assembly line parallel control of the whole multi-shaft motor in one period is completed.
Specifically, the FPGA programmable logic device may adopt models such as a Cyclone V-series FPGA chip 5CEFA7F 31.
In another embodiment, based on the multi-axis motor pipeline control system provided in this embodiment, the motor operation circuit includes a position error adjustment loop and a speed error adjustment loop, and further includes a plurality of current error adjustment loops, that is, the position error adjustment loop includes a position feedback calculation sub-circuit, a position error calculation sub-circuit, and a position adjustment sub-circuit, the speed error adjustment loop includes a speed feedback calculation sub-circuit, a speed error calculation sub-circuit, and a speed adjustment sub-circuit, and each current error adjustment loop includes a current feedback calculation sub-circuit, a current error calculation sub-circuit, and a current adjustment sub-circuit, as shown in fig. 7. In the motor arithmetic circuit in fig. 7, a position error adjusting ring and a speed error adjusting ring adopt the same pipeline control method as the above-mentioned embodiment, i.e. the position error calculating sub-circuit accesses the motor motion control command according to the first timing provided by the pipeline control circuit, the position feedback calculating sub-circuit accesses the position data according to the first timing provided by the pipeline control circuit, the speed feedback calculating sub-circuit accesses the speed data according to the first timing provided by the pipeline control circuit, and all the current error adjusting rings access the current data of the corresponding motor shaft respectively according to the conventional parallel control manner (i.e. each current feedback calculating sub-circuit shown in fig. 1 accesses the current data of the corresponding motor shaft respectively, and then each current adjusting sub-circuit outputs the current error adjusting data to the modulation output circuit of the corresponding motor shaft respectively), compared with the conventional parallel control method, and the occupation of resources of the FPGA is reduced to a certain extent, and the chip cost is reduced.
In another embodiment, the motor arithmetic circuit comprises a position error adjusting ring, a plurality of speed error adjusting rings and a plurality of current error adjusting rings; similarly, the position feedback calculation sub-circuits access the position data according to the first time sequence provided by the pipeline control circuit, and all the speed error adjusting rings and all the current error adjusting rings access the speed data of the corresponding motor shaft according to the traditional parallel control mode (i.e. each speed feedback calculation sub-circuit shown in fig. 1 accesses the current data of the corresponding motor shaft, and each current feedback calculation sub-circuit accesses the current data of the corresponding motor shaft, and then each current adjustment sub-circuit outputs the current error adjusting data to the modulation output circuit of the corresponding motor shaft); similarly, compared with the traditional parallel control method, the embodiment also reduces the occupation resource of the FPGA to a certain extent and reduces the chip cost.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (4)
1. A multi-axis motor assembly line control system based on FPGA is characterized by comprising a motor arithmetic circuit (3), an assembly line control circuit (5), a multi-path data acquisition circuit (1), a multi-path interface circuit (2) and a multi-path modulation output circuit (4) which are arranged on an FPGA programmable logic device;
the number of the data acquisition circuits (1), the number of the interface circuits (2) and the number of the modulation output circuits (4) are the same;
the motor arithmetic circuit (3), the assembly line control circuit (5), all the data acquisition circuits (1), all the interface circuits (2) and all the modulation output circuits (4) are respectively and electrically connected with the FPGA programmable logic device, all the data acquisition circuits (1), all the interface circuits (2) and all the modulation output circuits (4) are respectively and electrically connected with the motor arithmetic circuit (3), and all the data acquisition circuits (1), all the interface circuits (2) and all the modulation output circuits (4) are respectively and electrically connected with the assembly line control circuit (5);
the pipeline control circuit (5) provides a first time sequence and a second time sequence, output data of all the data acquisition circuits (1) and output data of all the interface circuits (2) are input into the motor operation circuit (3) in a pipeline polling mode according to the first time sequence, and all the modulation output circuits (4) receive the output data of the motor operation circuit (3) in a pipeline polling mode according to the second time sequence.
2. The FPGA-based multi-axis motor pipeline control system of claim 1, wherein each of the data acquisition circuits (1) comprises an encoder (11) and a current sensor (12);
in any way in data acquisition circuit (1), encoder (11) with current sensor (12) equally divide respectively with motor arithmetic circuit (3) electricity is connected, encoder (11) with current sensor (12) equally divide respectively with assembly line control circuit (5) electricity is connected, encoder (11) with current sensor (12) equally divide respectively with FPGA programmable logic device electricity is connected.
3. The FPGA-based multi-axis motor pipeline control system of claim 2, wherein the motor arithmetic circuit (3) comprises a position feedback calculation sub-circuit (31), a position error calculation sub-circuit (32), a position adjustment sub-circuit (33), a speed feedback calculation sub-circuit (34), a speed error calculation sub-circuit (35), a speed adjustment sub-circuit (36), a current feedback calculation sub-circuit (37), a current error calculation sub-circuit (38), and a current adjustment sub-circuit (39);
the position error calculation sub-circuit (32) sequentially passes through the position adjustment sub-circuit (33), the speed error calculation sub-circuit (35), the position adjustment sub-circuit (33) and the current error calculation sub-circuit (38) to be electrically connected with the current adjustment sub-circuit (39), the output ends of all the interface circuits (2) are respectively and electrically connected with the position error calculation sub-circuit (32), the output ends of all the modulation output circuits (4) are respectively and electrically connected with the current adjustment sub-circuit (39), the output ends of all the encoders (11) are respectively and electrically connected with the position error calculation sub-circuit (32) through the position feedback calculation sub-circuit (31), and the output ends of all the encoders (11) are also respectively and electrically connected with the speed error calculation sub-circuit (35) through the speed feedback calculation sub-circuit (34), the output ends of all the current sensors (12) are respectively and electrically connected with the current error calculating sub-circuit (38) through the current feedback calculating sub-circuit (37); the position feedback calculation sub-circuit (31), the position error calculation sub-circuit (32), the position adjustment sub-circuit (33), the speed feedback calculation sub-circuit (34), the speed error calculation sub-circuit (35), the speed adjustment sub-circuit (36), the current feedback calculation sub-circuit (37), the current error calculation sub-circuit (38), and the current adjustment sub-circuit (39) are electrically connected with the FPGA programmable logic device respectively.
4. The FPGA-based multi-axis motor pipeline control system according to any one of claims 1 to 3, wherein the first timing sequence comprises output data of all the data acquisition circuits (1) and output data of all the interface circuits (2) polling input pulse cycles and input precedence order into the motor operation circuit (3) in a pipeline manner, and output data of the data acquisition circuits (1) of every two adjacent channels and output data of the interface circuits (2) of every two adjacent channels polling input pulse intervals into the motor operation circuit (3) in a pipeline manner;
the second time sequence comprises output pulse periods and output sequence of output data of the motor operation circuits (3) which are polled and received by all the modulation output circuits (4) in a pipeline mode, and output pulse intervals of output data of the motor operation circuits (3) which are polled and received by the modulation output circuits (4) of every two adjacent channels in a pipeline mode;
the input pulse period is equal to the output pulse period, the input pulse interval is equal to the output pulse interval, the input sequence is equal to the output sequence, and the input sequence and the output sequence are respectively equal to the motor shaft number sequencing.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112083668A (en) * | 2020-08-03 | 2020-12-15 | 重庆智能机器人研究院 | Multi-axis motor pipeline control system based on FPGA and control method thereof |
| CN115712253A (en) * | 2022-09-19 | 2023-02-24 | 重庆智能机器人研究院 | Driving and controlling integrated control framework easy to expand |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112083668A (en) * | 2020-08-03 | 2020-12-15 | 重庆智能机器人研究院 | Multi-axis motor pipeline control system based on FPGA and control method thereof |
| CN115712253A (en) * | 2022-09-19 | 2023-02-24 | 重庆智能机器人研究院 | Driving and controlling integrated control framework easy to expand |
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