CN105655486B - Phase transition storage and forming method thereof - Google Patents
Phase transition storage and forming method thereof Download PDFInfo
- Publication number
- CN105655486B CN105655486B CN201410658849.8A CN201410658849A CN105655486B CN 105655486 B CN105655486 B CN 105655486B CN 201410658849 A CN201410658849 A CN 201410658849A CN 105655486 B CN105655486 B CN 105655486B
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- interlayer dielectric
- hearth electrode
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
A kind of phase transition storage and forming method thereof, wherein forming method includes：Semiconductor substrate is provided, on a semiconductor substrate formed with the first interlayer dielectric layer and interconnection layer；The second interlayer dielectric layer is formed on the first interlayer dielectric layer and interconnection layer；Through hole is formed in the second interlayer dielectric layer；On the second interlayer dielectric layer, through-hole side wall and bottom formation tunneling insulation layer；Hearth electrode material is formed on tunneling insulation layer and in through hole；Grinding removes the tunneling insulation layer and hearth electrode material higher than the second interlayer dielectric layer, and the remaining hearth electrode material in through hole is as hearth electrode.In the present case, tunnelling can block between the active device in Semiconductor substrate and lapping liquid and turn on and make lapping liquid not charged, the hearth electrode material infiltrated in lapping liquid will not be by electrochemical corrosion, this makes hearth electrode upper surface maintain an equal level with the second interlayer dielectric layer upper surface, and good contact electrical connection is able to ensure that hearth electrode carries out effectively heating to phase-change material layers to change its state.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of phase transition storage and forming method thereof.
Background technology
Phase transition storage (PCRAM) as a kind of emerging nonvolatile storage technologies, read or write speed, read-write number,
It is larger superior that data hold time, cellar area, multivalue realize etc. that all many-sided very fast flash memories (FLASH) all have
Property, turn into the focus of current non-volatile memory technology research.
Using resistance difference of the phase-change material under crystalline state and amorphous state come data storage, it is mainly utilized phase transition storage
The control of curtage impulse wave is completed to write, wiped, read operation.Generally, a phase-changing memory unit is by up to
Under include：Top electrode, phase-change material layers and hearth electrode, three contact electrical connection.In write operation, in top electrode and hearth electrode
Between apply a short time and of a relatively high reset (reset) voltage, make the phase-change material layer segment liter contacted with hearth electrode
Temperature melts and quickly cools down and switch to amorphous state by crystalline state.Because amorphous phase-change material has higher resistance (such as 105
~107 ohm), " 1 " is generally entered as, when being read, there is provided a reading electric current can obtain high level.Grasped in erasing
When making, there is provided a long period and relatively low set voltages so that the temperature of amorphous phase-change material layer segment be raised to it is molten
Change under temperature, on crystallization temperature, kept for a period of time promote nucleus growth afterwards, tie Amorphous Phase change material layer part
It is brilliant and be converted into crystalline state from amorphous state.Because the phase-change material of crystalline state has relatively low resistance (such as 102~104Ohm), generally
" 0 " is entered as, when being read, there is provided a reading electric current can obtain low level.Therefore, phase transition storage is to utilize to work as
Resistance difference when phase-change material layers are in crystalline state or amorphous state carrys out the nonvolatile memory of writing/reading data.
A kind of forming method of existing phase transition storage includes：
Reference picture 1, there is provided Semiconductor substrate 1, on semiconductor substrate 1 formed with active device (not shown)；
Interlayer dielectric layer 2, the interconnection layer 3 in interlayer dielectric layer 2 are also formed with Semiconductor substrate 1, interconnection layer 3 has with lower section
Source device electrical connection.
Reference picture 2, forms through hole 4 in interlayer dielectric layer 2, and through hole 4 connects with interconnection layer 3.
Reference picture 3, deposits tungsten layer 5, and tungsten layer 5 covers interlayer dielectric layer 2 and fills full through hole 4 (reference picture 2).
Reference picture 4, cmp tungsten layer 5 (reference picture 3), remove the tungsten layer higher than the interlayer dielectric layer 2, (ginseng of through hole 4
According to Fig. 3) in remaining tungsten layer part as hearth electrode 6.Afterwards, formed on interlayer dielectric layer 2 and contact electrical connection with hearth electrode 6
Phase-change material layers and the top electrode that is electrically connected with phase-change material layers is formed on phase-change material layers.
But the phase transition storage performance formed using prior art is bad.
The content of the invention
The present invention solves the problems, such as that the phase transition storage performance formed using prior art is bad.
To solve the above problems, the present invention provides a kind of forming method of phase transition storage, the formation of the phase transition storage
Method includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with the first interlayer dielectric layer and positioned at the first layer
Between interconnection layer in dielectric layer；
The second interlayer dielectric layer is formed on first interlayer dielectric layer and interconnection layer；
Through hole is formed in second interlayer dielectric layer, the through hole connects interconnection layer；
On second interlayer dielectric layer, through-hole side wall and bottom formation tunneling insulation layer；
Hearth electrode material, the full through hole of hearth electrode material filling are formed on the tunneling insulation layer and in through hole；
Grinding removes the tunneling insulation layer and hearth electrode material higher than second interlayer dielectric layer, surplus in the through hole
Remaining hearth electrode material is as hearth electrode.
Alternatively, the material of the tunneling insulation layer is tunnelling metal oxide.
Alternatively, the forming method of the tunneling insulation layer is chemical vapor deposition or physical vapour deposition (PVD).
Alternatively, the tunnelling metal oxide is：Ta2O5、TiO2Or Al2O3。
Alternatively, the physical vapour deposition (PVD) sputters for the metallic plasma of ionization, the tunnelling metal oxide
For Ta2O5；
In the metallic plasma sputter procedure of the ionization, parameter setting is as follows：The power bracket of the sputtering
For 630W~770W, the pressure range in reaction chamber is 4.5mTorr~5.5mTorr.
Alternatively, the tunnelling metal oxide is Ta2O5, Ta2O5Thickness range 1.5nm~4nm.
Alternatively, in addition to：
The dielectric layer between formation third layer on second interlayer dielectric layer and hearth electrode；
Phase-change material layers are formed in dielectric layer between the third layer, the phase change layer electrically connects with hearth electrode；
Between the third layer the 4th interlayer dielectric layer is formed on dielectric layer and phase-change material layers；
Top electrode is formed in the 4th interlayer dielectric layer, the top electrode electrically connects with phase-change material layers.
Alternatively, the hearth electrode material is W, TiN, TaN, TiC or TiCN.
The present invention also provides a kind of phase transition storage, and the phase transition storage includes：
Semiconductor substrate；
The first interlayer dielectric layer in the Semiconductor substrate and the interconnection in first interlayer dielectric layer
Layer；
The second interlayer dielectric layer on first interlayer dielectric layer and interconnection layer；
Through hole in second interlayer dielectric layer, the through hole connect interconnection layer；
Tunneling insulation layer positioned at the through-hole side wall and bottom；
The hearth electrode surrounded in the through hole and by the tunneling insulation layer, fill full through hole.
Alternatively, the material of the tunneling insulation layer is tunnelling metal oxide.
Alternatively, the tunnelling metal oxide is：Ta2O5、TiO2Or Al2O3。
Alternatively, the tunnelling metal oxide is Ta2O5, Ta2O5Thickness range 1.5nm~4nm.
Alternatively, in addition to：
Dielectric layer between third layer on second interlayer dielectric layer, tunneling insulation layer and hearth electrode；
Phase-change material layers between the third layer in dielectric layer, are electrically connected with hearth electrode；
The 4th interlayer dielectric layer between the third layer on dielectric layer and phase-change material layers；
Top electrode in the 4th interlayer dielectric layer, is electrically connected with phase-change material layers.
Alternatively, the hearth electrode material is W, TiN, TaN, TiC or TiCN.
Compared with prior art, technical scheme has advantages below：
Before filling hearth electrode material in through-holes, in through-hole side wall and bottom formed with tunneling insulation layer.So, grinding
Hearth electrode material is ground to when exposing the second interlayer dielectric layer, hearth electrode material and tunneling insulation layer upper surface in through hole are dipped in
In lapping liquid, but tunneling insulation layer separates interconnection layer and hearth electrode material, and tunneling insulation layer has insulating properties, and resistance is very
Greatly, it can block between the active device in Semiconductor substrate and lapping liquid and turn on and make lapping liquid not charged, infiltrate and grinding
Hearth electrode material in liquid will not be by electrochemical corrosion.This is able to ensure that the hearth electrode upper surface after grinding is situated between with the second interlayer
Matter layer upper surface maintains an equal level, and will not produce pit.Phase-change material layers can form good contact with hearth electrode and electrically connect, to phase transformation
When material layer writes and wipes data, good contact electrical connection is able to ensure that hearth electrode is effectively heated to phase-change material layers
To change its state.Moreover, the voltage in the write-in, erasing and read operation of phase transition storage can promote tunneling insulation layer
Generation tunnel-effect, realizes tunneling conduction, it is ensured that the sensitivity of phase transition storage is higher, and performance is preferable.
Brief description of the drawings
Fig. 1~Fig. 4 is cross-sectional view of the phase transition storage in forming process each stage of prior art；
Fig. 5~Fig. 8, Figure 11~Figure 16 are each stage of the phase transition storage in forming process of the specific embodiment of the invention
Cross-sectional view；
Fig. 9 is Ta2O5During generation tunnel-effect, the curve map of relation between its thickness and tunneling voltage；
Figure 10 is the Ta for 2nm to thickness2O5When application magnitude of voltage is+5V and -5V respectively, between its resistance and temperature
The schematic diagram of relation.
Embodiment
The problem of inventor exists for prior art is analyzed, and finds：Reference picture 2, Fig. 3, due in inter-level dielectric
The reason for through hole 4 be present in layer 2, in the deposition process of tungsten layer 5, the tungsten layer of the corresponding position of through hole 4 is partially below on interlayer dielectric layer 2
Tungsten layer part.With reference to reference picture 4, due to above reason, the process for grinding tungsten layer is roughly divided into two steps：The first step, grind
Grind off except the tungsten layer part higher than interlayer dielectric layer 2, in this process, because the tungsten layer of lead to the hole site is partially below other interlayers
Tungsten layer part on dielectric layer, and lapping liquid is substantially indiscriminate to the grinding rate of tungsten layer various pieces, therefore first
When step terminates, the thickness of the tungsten layer part in through hole can be less than the depth of through hole；Second step, grinding interlayer dielectric layer is crossed to through hole
In tungsten layer remained basically stable with interlayer dielectric layer.But during second step, in active device on a semiconductor substrate,
To electrical potential difference between adjacent source electrode and drain electrode in two metal-oxide-semiconductors of cmos circuit, be present, source electrode passes through interconnection layer respectively with drain electrode
3 electrically connect with the tungsten layer in through hole, and because tungsten layer partial wetting is in lapping liquid, the potential official post between source electrode and drain electrode makes to grind
Grinding fluid is powered, because the tungsten layer upper surface in through hole is exposed in lapping liquid, causes to infiltrate tungsten layer and aquatic products in lapping liquid
Raw electrochemical reaction, tungsten layer upper surface is by electrochemical corrosion.Reference picture 4, the upper surface of hearth electrode 6 ultimately formed is formed with recessed
Hole 6'(refers to dotted line frame region), pit causes to be incomplete contact between the phase-change material layers being subsequently formed and hearth electrode.This
The risk of phase transition storage signal transmission interruption can be increased, cause phase-change material layers to be heated and change its crystalline state or amorphous
State, phase transition storage sensitivity is caused to decline, it is impossible to normally to read and write data, performance is bad.
On the other hand, inventor once attempted to replace the acid solution in traditional handicraft to grind tungsten using the lapping liquid of acidity
Layer, but larger can not improve the problem of tungsten layer corrodes, also once attempted to avoid tungsten layer from meeting with by increasing the characteristic size of hearth electrode
To the corrosion of thicker degree, but this can increase manufacturing cost.Therefore, inventor passes through creative work, it is proposed that a kind of new
The forming method of phase transition storage.Using this method, before hearth electrode material is formed, on the first interlayer dielectric layer, through hole
Side wall and bottom are pre-formed one layer of tunneling insulation layer, so in cmp hearth electrode material, the tunneling insulation layer
The electrical connection between hearth electrode material and the interconnection layer in through hole can be blocked, due in the absence of electrical potential difference, lapping liquid and hearth electrode
Electrochemical reaction will not occur between material, and then avoid forming pit on hearth electrode surface.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Reference picture 5, there is provided Semiconductor substrate 10, over the semiconductor substrate 10 formed with active device (not shown),
Cover the first interlayer dielectric layer 11, the interconnection layer in the first interlayer dielectric layer 11 of Semiconductor substrate 10 and active device
12, interconnection layer 12 is electrically connected with active device, and its upper surface is exposed.
In Figure 5, interconnection layer 12 is conductive plunger, and electrical connection or logical is contacted with the active device in Semiconductor substrate 10
Other interconnection layer portions are crossed to electrically connect with active device.The forming method of the conductive plunger includes：First in the first inter-level dielectric
Contact hole is formed in layer 11, through hole connects with interconnection layer below or active device；Then, conductive material such as tungsten, aluminium are deposited
Or copper, the full contact hole of conductive material filling simultaneously cover the first interlayer dielectric layer 11；Afterwards, by cmp or it is etched back to
Technique, remove and be higher by the conductive plunger material of the upper surface of the first interlayer dielectric layer 11, remaining conductive material conduct in contact hole
Conductive plunger.
In the present embodiment, interconnection layer 12 is conductive plunger, merely illustrative.As an example, interconnection layer 12 is alternatively with leading
The interconnecting metal layer of electric plug electrical connection.
In the present embodiment, Semiconductor substrate 10 can be silicon substrate or germanium, germanium silicon, gallium arsenide substrate or exhausted
Silicon substrate on edge body.Those skilled in the art can select substrate as needed, therefore the type of substrate should not limit this hair
Bright protection domain.Semiconductor substrate 10 in the present embodiment selects silicon substrate, because implementing the technical program on a silicon substrate
Cost than implementing the technical program on other above-mentioned substrates is low.
Reference picture 6, the second interlayer dielectric layer 13 is formed on the first interlayer dielectric layer 11 and interconnection layer 12.Second interlayer is situated between
The material of matter layer 13 is silicon nitride or silica, or the second interlayer dielectric layer 13 includes the silicon nitride layer and oxygen that stack together
SiClx layer, usable chemical vapor deposition method are formed.
Reference picture 7, forms through hole 14 in the second interlayer dielectric layer 13, and through hole 14 connects interconnection layer 12, and exposed portion
Interconnection layer 12.The method of through hole 14 is formed in the second interlayer dielectric layer 13 to be included：
Patterned mask layer is formed on the second interlayer dielectric layer 13, such as patterned photoresist layer, it is patterned to cover
Film layer defines the position of through hole；
Using patterned mask layer as mask, dielectric layer 13 to interconnection layer 12 exposes between etching of second layer, forms through hole 14；
Remove patterned mask layer.
Reference picture 8, on the second interlayer dielectric layer 13, the side wall of through hole 14 and bottom formation tunneling insulation layer 15, tunnelling is exhausted
Edge layer 15 plays the insulating effect between follow-up hearth electrode and interconnection layer 12.
In the present embodiment, the material of tunneling insulation layer 15 is Ta2O5, specifically used chemical vapor deposition or physical vapor
Depositing operation is formed.Wherein, chemical vapor deposition method selection low-pressure chemical vapor deposition (Low Pressure Chemical
Vapor Deposition, LPCVD), Ta (OC2H are utilized during LPCVD5)5For raw material.Ta (OC2H in this process5)5
It is decomposed into Ta2O5And volatile materials, wherein Ta2O5It is deposited on the second interlayer dielectric layer 13, the side wall of through hole 14 and bottom, it is raw
Into volatile materials be discharged reaction chamber.During the LPCVD, the temperature range in reaction chamber is 369 DEG C~451 DEG C,
The temperature of the present embodiment is 410 DEG C.
In the present embodiment, physical gas-phase deposition selection sputtering, such as the metallic plasma sputtering of ionization.Remove
Outside this, radio-frequency sputtering and magnetron sputtering can be also used.Compared to radio-frequency sputtering, the metallic plasma (Ioned of ionization
Mental Plasma, IMP) sputtering sedimentation rate it is higher, can especially cover the through hole 14 with high-aspect-ratio well
Gap between side wall and through-hole side wall and bottom.During IMP, the present embodiment forms Ta in sputtering2O5Process can be with
It is：During Ta is sputtered, O is passed through into reaction chamber2, O2Generation Ta is reacted with Ta2O5, in this process using Ar as
Sputter gas, the high-energy Ar ion excitation Ta targets of ionization sputter Ta atoms；It can also be：First sputtering forms Ta layers, then
Oxidation processes are carried out to Ta layers to form Ta2O5.Dc source is provided in the metallic plasma sputter procedure of the ionization, is carried
For the power bracket of confession between 630W~770W, the pressure range in reaction chamber is 4.5mTorr~5.5mTorr, can be obtained
Obtain preferable sedimentation rate.
Phase transition storage is being write, read and during erasing operation, interconnection layer 12 needs and the bottom in follow-up through hole
Electrode conduction, to be passed through electric current to phase-change material layers, it is therefore necessary to ensure that tunneling insulation layer 15 can be tunneled over.Reference picture 9, figure
9 be Ta2O5During generation tunnel-effect, the curve map of relation, wherein Ta between its thickness and tunneling voltage2O5Thickness it is attached in 2nm
When near, required tunneling voltage value is smaller；And Ta2O5Thickness to be more than required tunneling voltage value during 4nm higher, and increase with thickness,
Required tunneling voltage value increase.Therefore, the thickness range of the tunneling insulation layer 15 of the present embodiment is 1.5nm~4nm.To phase transformation
Memory write " 1 ", apply the reset voltages of high value between top electrode and hearth electrode, tunneling insulation layer 15 can be made to exist
Tunnelling is conductive in short period, to promote phase-change material layers to be heated to more than fusing point within a short period of time；Deposited in erasing phase transformation
During the high level stored in reservoir, although the set voltages provided are relatively low, tunneling voltage needed for tunneling insulation layer 15 is relatively low,
Set voltages can make the tunneling conduction of tunneling insulation layer 15, be wiped the high level of phase-change material layers storage with realizing.Reading number
According to when, there is provided one it is relatively low read electric current can make the tunneling conduction of tunneling insulation layer 15.In addition, when phase transition storage is not powered on,
Tunneling insulation layer 15 plays good insulating effect, to avoid phase transition storage data from being lost in.Therefore, tunneling insulation layer 15 is in
In the above-mentioned thickness range, it can be ensured that phase transition storage normal work, and the sensitivity of phase transition storage will not be reduced.
Except Ta2O5Outside, other tunnelling metal oxides, such as TiO also may be selected in tunneling insulation layer 152Or Al2O3.For tradition
Tunnelling SiO2, its dielectric constant is relatively low, and the high integration of integrated circuit requires the thinner thickness of tunneling insulation layer, but makes
Very thin tunnelling SiO is hardly resulted in existing semiconductor technology2.By contrast, tunnelling metal oxide is partly led with existing
Body technology compatibility is good, thinner thickness, and dielectric constant is high., can be according to its tunnelling electricity to the different materials of tunneling insulation layer 15
Pressure obtains its thickness range.But compared to TiO2Or Al2O3, Ta2O5Tunneling voltage it is lower, corresponding phase transition storage it is sensitive
Property is higher.Moreover, Ta2O5There is good adhesion between the second interlayer dielectric layer 13 (reference picture 8), will not loosen easily,
Peel off.
In addition, reference picture 10, the Ta that it is 2nm to thickness that Figure 10, which is,2O5When application magnitude of voltage is+5V and -5V respectively, its electricity
Relation between resistance and temperature, as we know from the figure：On the one hand, raised with temperature, Ta2O5Resistance also raise, but the amplification of resistance
It is smaller；On the other hand, under+5V and -5V, Ta2O5Resistance be not more big changes substantially.It follows that Ta2O5Thermal conductivity
Rate (thermal conductivity) is relatively low.When phase transition storage writes and wipes data, the phase transformation that is contacted with hearth electrode
Layer material sections can be heated, although write-in is different with magnitude of voltage is applied during erasing operation, and the temperature of phase-change material layers is very high,
But surround the Ta of hearth electrode2O5Substantially will not significantly heat up, also just substantially will not be by the heat transfer of phase-change material layer segment to mutual
Even layer, phase-change material layers heat is avoided to scatter and disappear and cause to fail.
Reference picture 11, hearth electrode material 16, hearth electrode material are formed on tunneling insulation layer 15 and in through hole 14 (reference picture 8)
The full through hole 14 of the filling of material 16.In the present embodiment, hearth electrode material 16 is tungsten, and usable physical gas-phase deposition is formed.Remove
Outside tungsten, other materials also may be selected in hearth electrode material 16, such as TiN, TaN, TiC or TiCN.
Reference picture 12, using cmp, remove higher than the tunneling insulation layer of the second interlayer dielectric layer 13 and bottom electricity
Pole material part, remaining hearth electrode material is as hearth electrode 17 in through hole 14 (reference picture 8).
Chemical mechanical planarization process can be divided into three steps：
The first step, grinding hearth electrode material to tunneling insulation layer 15 expose, now hearth electrode material and tunneling insulation layer 15
It is dipped in lapping liquid, but tunneling insulation layer 15 separates interconnection layer 12 and hearth electrode material, and tunneling insulation layer 15 has insulation
Property, resistance is very big, can block and path is formed between active device and lapping liquid in Semiconductor substrate 10, and lapping liquid will not
Powered, the hearth electrode material infiltrated in lapping liquid will not produce electrochemical corrosion；
Second step, tunneling insulation layer 15 and hearth electrode material are ground, is exposed to the second interlayer dielectric layer 13；
3rd step, grinding tunneling insulation layer 15 and hearth electrode material are crossed, the upper surface of hearth electrode 17 into through hole 14 and the
The upper surface of two interlayer dielectric layer 13 is remained basically stable, in this process, due to the insulating properties of tunneling insulation layer 15, the upper table of hearth electrode 17
Electrochemical corrosion will not occur for face, and the upper surface of hearth electrode 17 will not produce pit, relatively flat.So, follow-up phase-change material layers
Good contact can be formed with hearth electrode 17 to electrically connect, it is unobstructed that this can guarantee that the signal of phase transition storage transmits, it is ensured that is writing
During with erasing data, phase-change material layers can be carried out with effectively heating to change its state, and the sensitivity of phase transition storage compared with
Height, performance are preferable.
Reference picture 13, medium between third layer is formed on the second interlayer dielectric layer 13, tunneling insulation layer 15 and hearth electrode 17
Layer 18, specifically used chemical vapor deposition.
Reference picture 14, phase-change material layers 19, phase-change material layers 19 and hearth electrode 17 are formed in dielectric layer 18 between third layer
Contact electrical connection, is also contacted with tunneling insulation layer 15, and the material of phase-change material layers 19 (GeSbTe, is write a Chinese character in simplified form for Ge-Sb-Te alloy
For GST), because GST is larger in the resisitivity of amorphous state and crystalline state, about differ three orders of magnitude so that be easier to identify
State with current storage is determined, can form good contact, work as phase-change material between phase-change material layers 19 and hearth electrode 17
Layer 19 can form good signal transmission after being heated with hearth electrode 17, and the upper surface of hearth electrode 17 is relatively flat, in phase
When change material layer writes and wipes data, the phase change material section contacted with hearth electrode 17 can be sufficiently heated, to avoid phase
Change material layer 19 fails.Forming the method for phase-change material layers 19 includes：Through hole is formed in dielectric layer 18 first between third layer, is led to
Expose the upper surface of hearth electrode 17 and tunneling insulation layer 15 and the upper surface of dielectric layer 18 between portion of third layer in hole；Afterwards, sink
Phase-change material is accumulated, medium 18 expires through hole with filling between phase-change material overlays third layer；Then, phase-change material is planarized, to through hole
In phase-change material layer material and third layer between dielectric layer 18 remain basically stable, remaining phase-change material is as phase-change material in through hole
Layer.
Reference picture 15, the 4th interlayer dielectric layer 20 is formed on dielectric layer 18 and phase-change material layers 19 between third layer；
Reference picture 16, forms top electrode 21 in the 4th interlayer dielectric layer 20, and top electrode 21 contacts with phase-change material layers 19
Electrical connection.
The present invention also provides a kind of phase transition storage, reference picture 16, and the phase transition storage includes：
Semiconductor substrate 10；
The first interlayer dielectric layer 11 in Semiconductor substrate 10 and the interconnection layer in the first interlayer dielectric layer 11
12；
The second interlayer dielectric layer 13 on the first interlayer dielectric layer 11 and interconnection layer 12；
Through hole 14 (refer to Fig. 8) in the second interlayer dielectric layer 13, through hole 14 connect interconnection layer 12；
Tunneling insulation layer 15 positioned at the side wall of through hole 14 and bottom；
The hearth electrode 17 surrounded in through hole 14 and by tunneling insulation layer 15, the full through hole 14 of the filling of hearth electrode 17, and
Its upper surface and the upper surface of the second interlayer dielectric layer 13 maintain an equal level；
Dielectric layer 18 between third layer on the second interlayer dielectric layer 13, tunneling insulation layer 15 and hearth electrode 17；
Phase-change material layers 19 between third layer in dielectric layer 18, electrical connection is contacted with hearth electrode 17；
The 4th interlayer dielectric layer 20 between third layer on dielectric layer 18 and phase-change material layers 19；
Top electrode 21 in the 4th interlayer dielectric layer 20, electrical connection is contacted with phase-change material layers 19.
In the present embodiment, the material of tunneling insulation layer 15 is tunnelling metal oxide, such as Ta2O5、TiO2Or Al2O3.Its
In, tunnelling metal oxide is Ta2O5When, its thickness range is 1.5nm~4nm.
In the present embodiment, the material of hearth electrode 17 is W, TiN, TaN, TiC or TiCN.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
- A kind of 1. forming method of phase transition storage, it is characterised in that including：Semiconductor substrate is provided, is situated between on the semiconductor substrate formed with the first interlayer dielectric layer and positioned at first interlayer Interconnection layer in matter layer；The second interlayer dielectric layer is formed on first interlayer dielectric layer and interconnection layer；Through hole is formed in second interlayer dielectric layer, the through hole connects interconnection layer；On second interlayer dielectric layer, through-hole side wall and bottom formation tunneling insulation layer；Hearth electrode material, the full through hole of hearth electrode material filling are formed on the tunneling insulation layer and in through hole；Grinding removes the tunneling insulation layer and hearth electrode material higher than second interlayer dielectric layer, the remaining bottom in the through hole Electrode material is as hearth electrode.
- 2. the forming method of phase transition storage as claimed in claim 1, it is characterised in that the material of the tunneling insulation layer is Tunnelling metal oxide.
- 3. the forming method of phase transition storage as claimed in claim 2, it is characterised in that the formation side of the tunneling insulation layer Method is chemical vapor deposition or physical vapour deposition (PVD).
- 4. the forming method of phase transition storage as claimed in claim 3, it is characterised in that the tunnelling metal oxide is： Ta2O5、TiO2Or Al2O3。
- 5. the forming method of phase transition storage as claimed in claim 4, it is characterised in that the physical vapour deposition (PVD) is ion The metallic plasma sputtering of change, the tunnelling metal oxide is Ta2O5；In the metallic plasma sputter procedure of the ionization, parameter setting is as follows：The power bracket of the sputtering is 630W~770W, the pressure range in reaction chamber is 4.5mTorr~5.5mTorr.
- 6. the forming method of phase transition storage as claimed in claim 4, it is characterised in that the tunnelling metal oxide is Ta2O5, Ta2O5Thickness range 1.5nm~4nm.
- 7. the forming method of phase transition storage as claimed in claim 1, it is characterised in that also include：The dielectric layer between formation third layer on second interlayer dielectric layer and hearth electrode；Phase-change material layers are formed in dielectric layer between the third layer, the phase-change material layers electrically connect with hearth electrode；Between the third layer the 4th interlayer dielectric layer is formed on dielectric layer and phase-change material layers；Top electrode is formed in the 4th interlayer dielectric layer, the top electrode electrically connects with phase-change material layers.
- 8. the forming method of phase transition storage as claimed in claim 1, it is characterised in that the hearth electrode material be W, TiN, TaN, TiC or TiCN.
- A kind of 9. phase transition storage, it is characterised in that including：Semiconductor substrate；The first interlayer dielectric layer in the Semiconductor substrate and the interconnection layer in first interlayer dielectric layer；The second interlayer dielectric layer on first interlayer dielectric layer and interconnection layer；Through hole in second interlayer dielectric layer, the through hole connect interconnection layer；Tunneling insulation layer positioned at the through-hole side wall and bottom；The hearth electrode surrounded in the through hole and by the tunneling insulation layer, fill full through hole.
- 10. phase transition storage as claimed in claim 9, it is characterised in that the material of the tunneling insulation layer is tunnelling metal Oxide.
- 11. phase transition storage as claimed in claim 10, it is characterised in that the tunnelling metal oxide is：Ta2O5、TiO2Or Al2O3。
- 12. phase transition storage as claimed in claim 11, it is characterised in that the tunnelling metal oxide is Ta2O5, Ta2O5 Thickness range 1.5nm~4nm.
- 13. phase transition storage as claimed in claim 9, it is characterised in that also include：Dielectric layer between third layer on second interlayer dielectric layer, tunneling insulation layer and hearth electrode；Phase-change material layers between the third layer in dielectric layer, are electrically connected with hearth electrode；The 4th interlayer dielectric layer between the third layer on dielectric layer and phase-change material layers；Top electrode in the 4th interlayer dielectric layer, is electrically connected with phase-change material layers.
- 14. phase transition storage as claimed in claim 9, it is characterised in that the hearth electrode material be W, TiN, TaN, TiC or TiCN。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410658849.8A CN105655486B (en) | 2014-11-18 | 2014-11-18 | Phase transition storage and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410658849.8A CN105655486B (en) | 2014-11-18 | 2014-11-18 | Phase transition storage and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105655486A CN105655486A (en) | 2016-06-08 |
| CN105655486B true CN105655486B (en) | 2018-03-30 |
Family
ID=56479884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410658849.8A Active CN105655486B (en) | 2014-11-18 | 2014-11-18 | Phase transition storage and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105655486B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399199A (en) * | 2007-09-26 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Method for cleaning metallic layer and forming conductive plug and silicon based LCD |
| CN102386324A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing phase change memory element |
| CN102479924A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Manufacture method of phase change memory |
| JP2013074275A (en) * | 2011-09-29 | 2013-04-22 | Fujitsu Semiconductor Ltd | Semiconductor device manufacturing method |
| CN104051530A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier |
| CN104126220A (en) * | 2011-12-20 | 2014-10-29 | 英特尔公司 | Conformal low temperature hermetic dielectric diffusion barriers |
-
2014
- 2014-11-18 CN CN201410658849.8A patent/CN105655486B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399199A (en) * | 2007-09-26 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Method for cleaning metallic layer and forming conductive plug and silicon based LCD |
| CN102386324A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing phase change memory element |
| CN102479924A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Manufacture method of phase change memory |
| JP2013074275A (en) * | 2011-09-29 | 2013-04-22 | Fujitsu Semiconductor Ltd | Semiconductor device manufacturing method |
| CN104126220A (en) * | 2011-12-20 | 2014-10-29 | 英特尔公司 | Conformal low temperature hermetic dielectric diffusion barriers |
| CN104051530A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105655486A (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100495756C (en) | Phase change memory and its forming method | |
| US7173271B2 (en) | Phase-change memory device and method of manufacturing the same | |
| US9276202B2 (en) | Phase-change storage unit containing TiSiN material layer and method for preparing the same | |
| CN101556986B (en) | Multi-state resistive switching material, thin film prepared therewith, multi-sate resistive switching memory element and application of memory element in memory device | |
| CN102696107A (en) | Resistance-varying element and process for production thereof | |
| US20060003515A1 (en) | Phase-change memory device and method for manufacturing the same | |
| JP4532605B2 (en) | Phase change memory element, phase change memory cell, vacuum processing apparatus, and method of manufacturing phase change memory element | |
| CN103427022B (en) | The preparation method comprising the phase change storage structure of sandwich type electrode | |
| CN106206938B (en) | Phase-change memory and its manufacturing method | |
| CN103682095B (en) | A kind of resistance-variable storing device with selectivity characteristic and preparation method thereof | |
| CN105449101B (en) | The forming method of phase-changing memory unit | |
| CN103794722A (en) | Novel phase change storage cell structure and manufacturing method thereof | |
| CN105655486B (en) | Phase transition storage and forming method thereof | |
| KR101052860B1 (en) | Phase change memory device and its manufacturing method | |
| CN103441215B (en) | Phase change storage structure of sandwich type blade-like electrode and preparation method thereof | |
| CN105449100B (en) | Phase transition storage and forming method thereof | |
| CN106997924A (en) | Phase transition storage and its manufacture method and electronic equipment | |
| CN105633279A (en) | Phase-change memory unit comprising partially defined phase-change material structures and fabrication method | |
| CN103500795B (en) | Preparation method of phase change memory electrode structure | |
| CN104993049B (en) | Phase-change memory and its manufacture method | |
| CN102376884B (en) | Manufacturing method of phase change layer of phase change random access memory | |
| CN102637820B (en) | Phase change random access memory forming method | |
| CN103325940B (en) | Phase-change memory cell and manufacturing method thereof | |
| CN104124337A (en) | Method for manufacturing phase change memory unit | |
| CN204118135U (en) | A kind of New-type phase change memory cell structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |