CN103500795B - Preparation method of phase change memory electrode structure - Google Patents
Preparation method of phase change memory electrode structure Download PDFInfo
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Abstract
The invention relates to a preparation method of a phase change memory electrode structure. According to the method, firstly, a first insulation layer and a second insulation layer are sequentially deposited on a silicon substrate, then, a first round hole type groove penetrating through the first insulation layer and the second insulation layer is formed through etching; tungsten material is deposited in the first groove; then, the tungsten material filled in the first groove are etched by a dry etch back method until the upper surface of the tungsten material is aligned with the upper surface of the first insulation layer, a second round hole type groove is formed, and the tungsten material at the bottom of the second groove is used as a lower electrode; then, conducting thin film layers are deposited on the upper surface of the second insulation layer and the inner surface of the second groove, next, third insulation layer material is filled in the second groove, then, the redundant third insulation layer material and the conducting thin film layers on the upper surface of the second insulation layer are removed through chemical-mechanical polishing, and the rest conducting thin film layers are used as an upper electrode. The method has the characteristics that the qualification rate of devices is greatly improved, in addition, the height uniformity of annular electrodes in silicon wafers is improved, the resistance distribution is narrowed in the phase change process, and the stability of the devices is improved.
Description
Technical field
The present invention relates to a kind of preparation method of phase change memory electrode structure, belong to field of semiconductor devices.
Background technology
Phase change memory technology is that the conception that can be applied to phase change memory medium at the phase-change thin film that beginning of the seventies late 1960s proposes based on Ovshinsky is set up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be processed in silicon wafer substrate, and its critical material is recordable phase-change thin film, heating electrode material, heat-insulating material and top electrode material etc.The general principle of phase transition storage utilizes electric impulse signal to act on device cell, make phase-change material, between amorphous state and polycrystalline state, reversible transition occur, by low-resistance when high resistant during measurement amorphous state and polycrystalline state, the write of information, erasing and read operation can be realized.
Typical phase transition storage uses chalcogenide alloy (such as GST, Ge2Sb2Te5) as phase change resistor, memory cell is a kind of minimum chalcogenide alloy particle, amorphous (a-GST) and crystallization (c-GST) state of phase change resistor have different resistivity, crystalline state has and is approximately kilohm typical resistances of (k Ω), and noncrystalline state has the typical resistances being approximately megohm (M Ω), (such as GST makes phase change resistor therefore usually to utilize chalcogenide alloy materials.PCRAM unit is read by the resistance value (i.e. the resistance value of phase change resistor) measuring PCRAM memory cell.
The phase transition storage of prior art, generally includes bottom electrode, top electrodes and the phase change layer between bottom electrode and top electrodes.The temperature that wherein the crystalline state process need of phase change layer is higher, is generally heated phase change layer by bottom electrode, and top electrodes only plays interconnection effect, and the heating effect quality of bottom electrode on phase change layer will directly affect the read-write speed of phase transition storage.
Along with the raising of technological level, the size of phase transition storage constantly reduces, and requires to reduce operation power consumption while preparing superchip.Its operation lower power consumption is mainly through reducing the region of required phase transformation in operating process or significantly improving the phase change region efficiency of heating surface.In order to reduce operating current, reduce the power consumption of phase transition storage, a kind of fairly simple method is exactly reduce the contact area of hearth electrode and phase-change material, be disclose a kind of contact area reducing hearth electrode and phase-change material in the Chinese patent application of CN102664236A, CN101271918 at publication number, what it adopted is annular electrode structure.In this annular electrode structure, be all adopt cmp method to remove unnecessary insulative dielectric material and annular electrode in above-mentioned two kinds of structures.In actual manufacture process, in order to reduce contact area, require the sidewall thickness of annular electrode very little (few tens of nanometers), height can not be too high.The insulating barrier of insulated plug of conducting electricity under normal circumstances is TEOS(tetraethoxysilane) silicon dioxide of method growth and the insulation dielectric of filling in annular electrode be the silicon dioxide adopting high-aspect-ratio (High Aspect Ratio Process, HARP) technique to grow.In the insulation dielectric adopting the removal of chemico-mechanical polishing unnecessary and annular electrode process, because the thickness of annular electrode is very quick-fried, the signal of end point determination is difficult to obtain, be difficult to adopt end-point detection method to carry out the control of polishing end point, and it is very many to affect chemico-mechanical polishing factor, as polishing fluid, polishing pad, mechanical parameter (pressure, rotating speed, flow) etc. all can to having an impact in polishing process, therefore the technique controlling polishing end point by polishing time usually causes excessive polishing or directional polish, the result of excessive polishing can cause the height of annular electrode to shorten even not to be had, directional polish can cause the open circuit of circuit, thus cause the inefficacy of device.
Therefore, how to adopt end-point detection method to control polishing end point in given annular electrode structure manufacture and become this area phase transition storage volume production technical problem urgently to be resolved hurrily in fact.
Summary of the invention
The object of the invention is to the defect overcoming prior art, a kind of preparation method of phase change memory electrode structure is provided, for solving the problem of excessive polishing in prior art in phase transition storage annular electrode manufacture process and directional polish, avoiding component failure, improving yield.
The present invention is achieved by the following technical solutions:
A preparation method for phase change memory electrode structure, comprises the following steps:
(1) utilize chemical vapor deposition method to form the first insulating barrier on a silicon substrate and be positioned at the second insulating barrier on the first insulating barrier;
(2) utilize photoetching and dry etch process etching described first insulating barrier and the second insulating barrier, and automatically end at the upper surface of silicon substrate, form through first insulating barrier and the second insulating barrier and bottom surface is the circular hole groove I of silicon substrate upper surface;
(3) chemical vapor deposition method deposits tungsten material in described groove I is utilized, and make described tungsten material be covered in the upper surface of the second insulating barrier, then the tungsten material on described second insulating barrier upper surface is removed by cmp method, final tungsten material and the second insulating barrier upper surface flush;
(4) dry etchback (Dry Etch Back) technique is utilized to etch the tungsten material be filled in described groove I, until be filled in the upper surface of the tungsten material in described groove I and the upper surface flush of the first insulating barrier, form the circular hole groove II that bottom is tungsten material, sidewall is the second insulating barrier, the tungsten material of bottom is then as bottom electrode;
(5) chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process depositing electrically conductive thin layer on the inner surface of described groove II and the upper surface of the second insulating barrier is utilized;
(6) utilize chemical vapor deposition method to fill groove II, form the 3rd insulating barrier, and make the 3rd insulating layer material be covered on described conductive membrane layer completely;
(7) end-point detecting system of optical means is adopted, the 3rd insulating layer material and conductive membrane layer unnecessary on the second insulating barrier upper surface is removed in chemico-mechanical polishing, and automatically terminate in the second insulating barrier upper surface, and in groove II remaining conductive membrane layer as top electrode.
Wherein,
Preferably, in step (1), the material of described silicon substrate is Si.
Preferably, in step (1), the material of described first insulating barrier is SiO
2, thickness is 100 ~ 300nm; The material of described second insulating barrier is SiN or SiON, and the thickness of the second insulating barrier is 50 ~ 150nm.
Preferably, in step (1), the growth temperature of described chemical vapor deposition method is 350-500 DEG C.
Preferably, in step (2), the diameter of described groove I is 50 ~ 200nm.
Preferably, in step (3), the growth temperature of described chemical vapor deposition method is 350 ~ 500 DEG C; The initial packed height of described tungsten material should be the 1.5-2.5 of the degree of depth of groove I doubly; The polishing fluid of described chemico-mechanical polishing is acid polishing slurry, and its pH is 2-6.
Preferably, in step (5), the material of described conductive membrane layer is selected from TiN, TiSiN and TiON, and the conductivity of conductive membrane layer is 1 × 10
3Ω
-1m
-1~ 1 × 10
6Ω
-1m
-1, the thickness of conductive membrane layer is 5 ~ 15nm.
Preferably, in step (6), described chemical vapor deposition method is high-aspect-ratio (High Aspect Ratio Process, HARP) chemical vapor deposition method.
Preferably, in step (6), the material of described 3rd insulating barrier is SiO
2; The initial packed height of described 3rd insulating barrier is 3 to 6 times of the degree of depth of groove II.
Preferably, in step (7), the polishing fluid of described chemico-mechanical polishing is alkalescence polishing liquid, and pH is 9 ~ 11.
Preferably, in step (7), during chemico-mechanical polishing, the ratio of described 3rd insulating barrier and the second insulating barrier polishing speed is 30 ~ 100.
Preferably, in step (7), Systems for optical inspection installed by the polishing block carrying out chemico-mechanical polishing, and burnishing parameters is: the pressure being loaded into silicon chip back side is 1.0 ~ 3.0psi; Polishing disk is identical with the rotating speed of rubbing head, is 30 ~ 90 revs/min; Polishing fluid flow can be 100 ~ 500 ml/min, and polishing pad can adopt IC1000 series.
Preferably, the ratio of the light reflected intensity of described second insulating barrier and the light reflected intensity of the 3rd insulating barrier is 1.2-1.6:1.
Preferred, the ratio of the light reflected intensity of described second insulating barrier and the light reflected intensity of the 3rd insulating barrier is 1.3:1.
Preferably, the ratio of the described light reflected intensity of the 3rd insulating barrier and the light reflected intensity of the second insulating barrier is 1.2-1.6:1.
Preferred, the described light reflected intensity of the 3rd insulating barrier and the optical reflection intensity ratio of the second insulating barrier are 1.3:1.
Technique effect of the present invention and advantage are: by devising the second insulating barrier and the 3rd insulating barrier two kinds of different insulative dielectric materials, remove in unnecessary insulation dielectric and conductive film material process in employing CMP (Chemical Mechanical Polishing) process, utilize the difference of the optical reflection intensity of different electric insulating medium material, the polishing end point of electric insulating medium material is obtained.Such one side avoids the technique controlling polishing end point by polishing time and causes excessive polishing or directional polish, thus greatly improves the yield of device; On the other hand, improve the uniformity of annular electrode height in silicon chip, the distribution of resistance in phase transition process is narrowed, improve the stability of device.
Accompanying drawing explanation
Fig. 1 Semiconductor substrate, the first electric edge layer and the second insulating barrier schematic diagram;
The electric edge layer of Fig. 2 second and groove I schematic diagram;
Fig. 3 bottom electrode filling groove I schematic diagram (before polishing);
Fig. 4 bottom electrode filling groove I polishing schematic diagram (after polishing);
Fig. 5 bottom electrode eat-backs and forms groove II schematic diagram;
Fig. 6 conductive membrane layer forms schematic diagram;
Fig. 7 the 3rd insulating barrier fills schematic diagram (before polishing);
Fig. 8 the 3rd insulating barrier polishing schematic diagram (after polishing);
In Fig. 9 polishing process, the removal of the 3rd insulating dielectric materials is transitioned into the optical signalling end point determination curve at the second insulating dielectric materials interface
Reference numeral:
11, silicon substrate; 12, first insulating barrier; 13, second insulating barrier; 14, tungsten material; 15, conductive membrane layer; 16, three insulating barrier.
Embodiment
Below by way of specific instantiation, technical scheme of the present invention is described.Should be understood that one or more method steps that the present invention mentions do not repel and before and after described combination step, also to there is additive method step or can also insert additive method step between these steps clearly mentioned; Should also be understood that these embodiments are only not used in for illustration of the present invention to limit the scope of the invention.And, except as otherwise noted, the numbering of various method steps is only the convenient tool differentiating various method steps, but not be ordering or the enforceable scope of restriction the present invention of restriction various method steps, the change of its relativeness or adjustment, when changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Embodiment 1
A preparation method for annular phase change memory electrode structure, comprises the following steps:
Step (1): as shown in Figure 1, silicon substrate 11 utilizes chemical vapor deposition method (growth temperature 400 DEG C) form the first insulating barrier 12 and be positioned at the second insulating barrier 13 on the first insulating barrier 12; The material of silicon substrate 11 is Si; First insulating barrier 12 material is SiO
2, its thickness can be 100 ~ 300nm; Second insulating barrier 13 material is SiN or SiON, and thickness can be 50 ~ 150nm; In the present embodiment, the thickness of the first insulating barrier 12 is 150nm, and the thickness of the second insulating barrier 13 is 100nm.
Step (2): as shown in Figure 2, photoetching and dry etch process is utilized to etch described first insulating barrier and the second insulating barrier, and automatically end at the upper surface of silicon substrate, formed and run through the first insulating barrier 12 and the second insulating barrier 13 and bottom surface is the circular hole groove I of silicon substrate 11 upper surface; The diameter of described groove I can be 50 ~ 200nm; The diameter of groove I described in the present embodiment is 80nm.
Step (3): as shown in Figure 3 and Figure 4, utilize chemical vapor deposition method, at 400 DEG C, deposits tungsten material 14 in described groove I, and making described tungsten material be covered in (as Fig. 3) on the upper surface of the second insulating barrier, tungsten material embryo deposit total height can be 1.5-2.5 times of groove I height; Then removed the tungsten material on described second insulating barrier upper surface by cmp method (adopting the acid polishing slurry of pH=2-6), final tungsten material and the second insulating barrier upper surface flush, as Fig. 4; The embryo deposit total height of the material of tungsten described in the present embodiment is 2 times of the groove I degree of depth.
Step (4): as shown in Figure 5, dry etchback (Dry Etch Back) technique is utilized to etch the tungsten material 14 be filled in described groove I, until be filled in the upper surface of the tungsten material 14 in described groove I and the upper surface flush of the first insulating barrier 12, form the circular hole groove II that bottom is tungsten material 14, sidewall is the second insulating barrier 12, the tungsten material of bottom is then as bottom electrode.
Step (5): as shown in Figure 6, utilize chemical vapor deposition method, physical gas-phase deposition or ald (ALD, Atomic layer Deposition) technique depositing electrically conductive thin layer 15 on the inner surface of described groove II and the upper surface of the second insulating barrier 13; The material of described conductive membrane layer 15 is selected from TiN, TiSiN and TiON, and conductivity is 1 × 10
3Ω
-1m
-1~ 1 × 10
6Ω
-1m
-1, the thickness of conductive membrane layer 15 can be 5 ~ 15nm.In the present embodiment, the material of described conductive membrane layer 15 is TiN, and thickness is 10nm.
Step (6): as shown in Figure 7, adopts high-aspect-ratio (High Aspect Ratio Process, HARP) chemical vapor deposition method, utilizes tetraethoxysilane (Si (C
2h
5o)
4) and ozone reaction, growth material is SiO
2the 3rd insulating barrier 16 pairs of groove II fill, and be covered on conductive membrane layer 15 completely; The initial packed height of the 3rd insulating barrier 16 should be 3 to 6 times of the groove II degree of depth.(namely light reflected intensity between described 3rd insulating barrier 16 and the second insulating barrier 13 has the difference of 20 ~ 60%, the ratio of the light reflected intensity of the second insulating barrier 13 and the light reflected intensity of the 3rd insulating barrier 16 is 1.2-1.6:1, or the ratio of the light reflected intensity of the light reflected intensity of the 3rd insulating barrier 16 and the second insulating barrier 13 is 1.2-1.6:1).In this routine implementation process, the initial packed height of the 3rd insulating barrier 16 is 3.5 times of the groove II degree of depth, and the second insulating barrier 13 and the 3rd insulating barrier 16 optical reflection intensity ratio are 1.3:1.
Step (7): as shown in Figure 7, utilize pH be 8 ~ 11 alkalescence polishing liquid, the polishing block being configured with Systems for optical inspection carries out chemico-mechanical polishing to the 3rd insulating barrier 16 and conductive film material 15, and (burnishing parameters is: the pressure being loaded into silicon chip back side is 1.0 ~ 3.0psi, polishing disk is identical with the rotating speed of rubbing head and be 30 ~ 90 revs/min, polishing fluid flow can be 100 ~ 500 ml/min, polishing pad can adopt IC1000 series, by the method adopting optical end point to detect, remove the outer unnecessary material of groove II, because the optical reflectivity of the 3rd insulating barrier 16 and the second insulating barrier 13 is different, when optical signalling is transitioned into the second insulating barrier 13 from the 3rd insulating barrier 16, curve can be undergone mutation, catastrophe point is set to polishing terminating point (as shown in Figure 9), last polishing stops on the second insulating barrier 13 automatically.The present embodiment adopts pH value to be the alkalescence polishing liquid of 9 ~ 11, and the Selection radio of polishing speed (polishing speed of the 3rd insulating barrier 16 is divided by the polishing speed of the second insulating barrier 13) is between 30 to 100.First remove successively from top layer the 3rd insulating barrier 16, conductive membrane layer 15 material, finally automatically stop on the second insulating barrier 13.Because conductive membrane layer 15 material thickness only has 10nm, the conductive film layer material 15 in a short period of time outside groove II has just been removed, and does not have obvious optical signalling to change, can ignore in this enforcement; And in groove II remaining conductive membrane layer as top electrode.
In sum, the electrode structure of phase transition storage of the present invention and preparation method, utilize growth small-size annular electrode, the annular electrode structure be namely made up of conductive membrane layer 15 material adopts prepares annular electrode when bottom electrode (i.e. tungsten material formed tungsten electrode) size is given.By devising the second insulating barrier 13 and the 3rd insulating barrier 16 two kinds of different insulative dielectric materials, in employing chemico-mechanical polishing, remove unnecessary insulation dielectric and conductive film material.Utilize optical means to carry out controlling the terminal of polishing, avoid the technique controlling polishing end point by polishing time and cause excessive polishing or directional polish, thus greatly improve the yield of device.On the other hand, improve the uniformity of annular electrode height in silicon chip, the distribution of resistance in phase transition process is narrowed, improve the stability of device.The present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Claims (8)
1. a preparation method for phase change memory electrode structure, comprises the following steps:
(1) utilize chemical vapor deposition method to form the first insulating barrier on a silicon substrate and be positioned at the second insulating barrier on the first insulating barrier;
(2) utilize photoetching and dry etch process etching described first insulating barrier and the second insulating barrier, and automatically end at the upper surface of silicon substrate, form through first insulating barrier and the second insulating barrier and bottom surface is the circular hole groove I of silicon substrate upper surface;
(3) chemical vapor deposition method deposits tungsten material in described groove I is utilized, and make described tungsten material be covered in the upper surface of the second insulating barrier, then the tungsten material on described second insulating barrier upper surface is removed by cmp method, final tungsten material and the second insulating barrier upper surface flush;
(4) dry etchback technique is utilized to etch the tungsten material be filled in described groove I, until be filled in the upper surface of the tungsten material in described groove I and the upper surface flush of the first insulating barrier, form the circular hole groove II that bottom is tungsten material, sidewall is the second insulating barrier, the tungsten material of bottom is then as bottom electrode;
(5) chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process depositing electrically conductive thin layer on the inner surface of described groove II and the upper surface of the second insulating barrier is utilized;
(6) utilize chemical vapor deposition method to fill groove II, form the 3rd insulating barrier, and make the 3rd insulating layer material be covered on described conductive membrane layer completely;
(7) end-point detecting system of optical means is adopted, the 3rd insulating layer material and conductive membrane layer unnecessary on the second insulating barrier upper surface is removed in chemico-mechanical polishing, and automatically terminate in the second insulating barrier upper surface, and in groove II remaining conductive membrane layer as top electrode;
Wherein, the ratio of the light reflected intensity of described second insulating barrier and the light reflected intensity of the 3rd insulating barrier is the ratio of 1.2-1.6:1 or the described light reflected intensity of the 3rd insulating barrier and the light reflected intensity of the second insulating barrier is 1.2-1.6:1.
2. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (1), the material of described first insulating barrier is SiO
2, thickness is 100 ~ 300nm; The material of described second insulating barrier is SiN or SiON, and the thickness of the second insulating barrier is 50 ~ 150nm; The growth temperature of described chemical vapor deposition method is 350-500 DEG C.
3. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (2), the diameter of described groove I is 50 ~ 200nm.
4. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (3), the growth temperature of described chemical vapor deposition method is 350 ~ 500 DEG C; The initial packed height of described tungsten material is 1.5-2.5 times of the degree of depth of groove I; The polishing fluid of described chemico-mechanical polishing is acid polishing slurry, and its pH is 2-6.
5. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (5), the material of described conductive membrane layer is selected from TiN, TiSiN and TiON, and the conductivity of conductive membrane layer is 1 × 10
3Ω
-1m
-1~ 1 × 10
6Ω
-1m
-1, the thickness of conductive membrane layer is 5 ~ 15nm.
6. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (6), described chemical vapor deposition method is high-aspect-ratio chemical vapor deposition method; The material of described 3rd insulating barrier is SiO
2; The initial packed height of described 3rd insulating barrier is 3 to 6 times of the degree of depth of groove II.
7. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, is characterized in that, in step (7), the polishing fluid of described chemico-mechanical polishing is alkalescence polishing liquid, and pH is 9 ~ 11; During chemico-mechanical polishing, the ratio of described 3rd insulating barrier and the second insulating barrier polishing speed is 30 ~ 100.
8. the preparation method of a kind of phase change memory electrode structure as claimed in claim 1, it is characterized in that, in step (7), Systems for optical inspection installed by the polishing block carrying out chemico-mechanical polishing, and burnishing parameters is: the pressure being loaded into silicon chip back side is 1.0 ~ 3.0psi; Polishing disk is identical with the rotating speed of rubbing head, is 30 ~ 90 revs/min; Polishing fluid flow is 100 ~ 500 ml/min, and polishing pad adopts IC1000 series.
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| CN101197317A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Phase change memory cell with thermal barrier and method for fabricating the same |
| CN101866942A (en) * | 2009-04-20 | 2010-10-20 | 旺宏电子股份有限公司 | Ring-shaped electrode and manufacturing method for same |
| CN102664236A (en) * | 2012-05-16 | 2012-09-12 | 中国科学院上海微系统与信息技术研究所 | Ring electrode structure for low-power-consumption phase change memory and preparation method |
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| EP0735565B1 (en) * | 1995-03-31 | 1999-06-02 | International Business Machines Corporation | Method and apparatus for monitoring the dry etching of a dielectric film to a given thickness |
| EP1171920B1 (en) * | 1999-03-25 | 2006-11-29 | OVONYX Inc. | Electrically programmable memory element with improved contacts |
| US7394088B2 (en) * | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
| CN103219462B (en) * | 2013-03-27 | 2014-11-05 | 中国科学院半导体研究所 | Preparation method of phase change memory with annular vertical structure |
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| CN101197317A (en) * | 2006-12-06 | 2008-06-11 | 旺宏电子股份有限公司 | Phase change memory cell with thermal barrier and method for fabricating the same |
| CN101866942A (en) * | 2009-04-20 | 2010-10-20 | 旺宏电子股份有限公司 | Ring-shaped electrode and manufacturing method for same |
| CN102664236A (en) * | 2012-05-16 | 2012-09-12 | 中国科学院上海微系统与信息技术研究所 | Ring electrode structure for low-power-consumption phase change memory and preparation method |
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