CN105655357A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN105655357A CN105655357A CN201610177257.3A CN201610177257A CN105655357A CN 105655357 A CN105655357 A CN 105655357A CN 201610177257 A CN201610177257 A CN 201610177257A CN 105655357 A CN105655357 A CN 105655357A
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- film transistor
- tft
- thin film
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- base palte
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention discloses an array substrate and a manufacturing method thereof, and relates to the technical field of display. The array substrate and the manufacturing method thereof aim at solving the problem that in the array substrate manufacturing process, the probability of occurrence of the ESD phenomenon is high. The array substrate comprises at least one ESD structure. Each ESD structure comprises a first thin film transistor and a second thin film transistor, wherein a gate insulation layer of the first thin film transistor is provided with a first via hole, a first connecting medium is arranged in the first via hole and used for connecting the control end of the first thin film transistor with the input end of the second thin film transistor, a gate insulation layer of the second thin film transistor is provided with a second via hole, and a second connecting medium is arranged in the second via hole and used for connecting the control end of the second thin film transistor with the input end of the first thin film transistor. The manufacturing method of the array substrate is used for manufacturing the array substrate in the technical scheme. The array substrate is applied to TFT-LCDs.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof.
Background technology
Development along with Display Technique, Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay, hereinafter referred to as TFT-LCD) more and more it is applied in the middle of the life of people, in order to meet the higher market demand, production firm is in the process making TFT-LCD, it is necessary to improve the production yield of TFT-LCD. And in the manufacturing process of TFT-LCD, each making link is likely to produce static discharge (ElectrostaticDischarge, hereinafter referred to as ESD) phenomenon, cause the TFT-LCD that produces can not normal operation, reduce the production yield of TFT-LCD.
In order to avoid this due to ESD event cause reduce TFT-LCD produce yield problem, prior art is generally adopted esd protection structure by make TFT-LCD process in produce electric charge uniformly spread, avoid the generation of ESD event. But the esd protection structure of employing is all just formed after the array base palte making in TFT-LCD terminates in prior art; this allows for produced electric charge in the manufacturing process of array base palte and uniformly can not be spread by esd protection structure; namely, in the manufacturing process of array base palte, ESD event still has higher Probability.
Summary of the invention
It is an object of the invention to provide a kind of array base palte and preparation method thereof, for solving in the manufacturing process of array base palte, the problem that ESD event has higher Probability.
To achieve these goals, the present invention provides following technical scheme:
A kind of array base palte, including at least one ESD structure, described ESD structure includes the first film transistor and the second thin film transistor (TFT), the end that controls of described the first film transistor is connected with the input of described the first film transistor, and be connected with the holding wire in described array base palte, the input of described the first film transistor is connected with the outfan of described second thin film transistor (TFT), and the outfan of described the first film transistor is connected with the input of described second thin film transistor (TFT);The end that controls of described second thin film transistor (TFT) is connected with the input of described second thin film transistor (TFT), and is connected with the public electrode in described array base palte; The gate insulator of described the first film transistor is provided with the first via, is provided with the first connection medium in described first via, and described first connects medium for connecting the input controlling end and described the first film transistor of described the first film transistor; The gate insulator of described second thin film transistor (TFT) is provided with the second via, is provided with the second connection medium in described second via, and described second connects medium for connecting the input controlling end and described second thin film transistor (TFT) of described second thin film transistor (TFT).
The present invention also provides for the manufacture method of a kind of array base palte, comprises the following steps:
One underlay substrate is provided, described underlay substrate makes tft array and ESD structure;
When the first film transistor made in described ESD structure, after forming the gate insulator of described the first film transistor, before forming the semiconductor layer of described the first film transistor, the gate insulator of described the first film transistor forms the first via;
After forming the semiconductor layer of described the first film transistor, described first via forms the first connection medium;
When the second thin film transistor (TFT) made in described ESD structure, after forming the gate insulator of described second thin film transistor (TFT), before forming the semiconductor layer of described second thin film transistor (TFT), the gate insulator of described second thin film transistor (TFT) forms the second via;
After forming the semiconductor layer of described second thin film transistor (TFT), described second via forms the second connection medium.
In array base palte provided by the invention, including at least one ESD structure, the gate insulator of the first film transistor in this ESD structure is provided with the first via, and in the first via, it is provided with the first connection medium, the gate insulator of the second thin film transistor (TFT) in ESD structure is provided with the second via, and in the second via, is provided with the second connection medium; So after in array base palte, the source and drain metal level of tft array, the input of the first film transistor, the outfan of the first film transistor, the input of the second thin film transistor (TFT) and the outfan of the second thin film transistor (TFT) deposit simultaneously, first connects medium just can connect the input controlling end and the first film transistor of the first film transistor, second connects medium just can connect the input controlling end and the second thin film transistor (TFT) of the second thin film transistor (TFT), namely defines complete ESD structure. When array substrate carries out the follow-up etching of source and drain metal level, via mask and pixel electrode mask so again, the electrostatic of generation just can well be discharged by ESD structure, thus reducing ESD event occurrence probability in array base palte manufacturing process.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the present invention, and the schematic description and description of the present invention is used for explaining the present invention, is not intended that inappropriate limitation of the present invention. In the accompanying drawings:
The sectional view of the ESD structure that Fig. 1 provides for the embodiment of the present invention;
The schematic diagram of the ESD structure that Fig. 2 provides for the embodiment of the present invention;
The top view of the ESD structure that Fig. 3 provides for the embodiment of the present invention;
The first schematic diagram in the manufacture method of the ESD structure that Fig. 4 provides for the embodiment of the present invention;
The second schematic diagram in the manufacture method of the ESD structure that Fig. 5 provides for the embodiment of the present invention;
The 3rd schematic diagram in the manufacture method of the ESD structure that Fig. 6 provides for the embodiment of the present invention.
Accompanying drawing labelling:
1-underlay substrate, the gate insulator of 2-the first film transistor,
The semiconductor layer of 3-the first film transistor, the control end of 4-the first film transistor,
The input of 5-the first film transistor, the outfan of 6-the first film transistor,
The gate insulator of 7-the second thin film transistor (TFT), the semiconductor layer of 8-the second thin film transistor (TFT),
The control end of 9-the second thin film transistor (TFT), the input of 10-the second thin film transistor (TFT),
The outfan of 11-the second thin film transistor (TFT), 12-the first via,
13-the second via, 14-photoresist,
15-the first outer lead, 16-the second outer lead,
17-public electrode, 18-the 3rd via.
Detailed description of the invention
In order to further illustrate array base palte of embodiment of the present invention offer and preparation method thereof, it is described in detail below in conjunction with Figure of description.
Refer to Fig. 1, Fig. 2 and Fig. 3, the array base palte that the embodiment of the present invention provides includes at least one ESD structure, ESD structure includes the first film transistor and the second thin film transistor (TFT), the end 4 that controls of the first film transistor is connected with the input 5 of the first film transistor and forms the first outer lead 15, first outer lead 15 is connected with the holding wire (gate line or data wire) in array base palte, the input 5 of the first film transistor is connected with the outfan 11 of the second thin film transistor (TFT), the outfan 6 of the first film transistor is connected with the input 10 of the second thin film transistor (TFT), the end 9 that controls of the second thin film transistor (TFT) is connected with the input 10 of the second thin film transistor (TFT) and forms the second outer lead 16, and the second outer lead 16 is connected with the public electrode 17 in array base palte (the second outer lead 16 is connected with public electrode 17 by the 3rd via 18), being provided with the first via 12 on the gate insulator 2 of the first film transistor, be provided with the first connection medium in the first via 12, first connects medium for connecting the input 5 controlling end 4 and the first film transistor of the first film transistor, being provided with the second via 13 on the gate insulator 7 of the second thin film transistor (TFT), be provided with the second connection medium in the second via 13, second connects medium for connecting the input 10 controlling end 9 and the second thin film transistor (TFT) of the second thin film transistor (TFT).
The concrete electrostatic protection process of the ESD structure in array base palte is: when have be applied to the first outer lead 15 higher than the voltage of the first film transistor threshold voltage time, the first film transistor turns, the second outer lead 16 and the first outer lead 15 is made to be in isoelectric level state, namely when accumulation of static electricity is when the first outer lead 15, can by this ESD structural transmission to the second outer lead 16; When have be applied to the second outer lead 16 higher than the voltage of the first film transistor threshold voltage time; second thin film transistor (TFT) conducting; the first outer lead 15 and the second outer lead 16 is made to be in isoelectric level state; namely when accumulation of static electricity is when the second outer lead 16; can by this ESD structural transmission to the first outer lead 15; the electrostatic that such ESD structure just can produce in array substrate realizes bidirectional shunt, thus array substrate is protected.
In the array base palte that the embodiment of the present invention provides, including at least one ESD structure, the gate insulator 2 of the first film transistor in this ESD structure is provided with the first via 12, and in the first via 12, it is provided with the first connection medium, the gate insulator 7 of the second thin film transistor (TFT) in ESD structure is provided with the second via 13, and in the second via 13, is provided with the second connection medium;So after the source and drain metal level of tft array in array base palte, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) deposit simultaneously, first connects medium just can connect the input 5 controlling end 4 and the first film transistor of the first film transistor, second connects medium just can connect the input 10 controlling end 9 and the second thin film transistor (TFT) of the second thin film transistor (TFT), namely defines complete ESD structure. When array substrate carries out the follow-up etching of source and drain metal level, via mask and pixel electrode mask so again, the electrostatic of generation just can well be discharged by ESD structure, thus reducing ESD event occurrence probability in array base palte manufacturing process.
Please continue to refer to Fig. 1, source and drain metal level that above-described embodiment provides, first connect medium, second connect medium, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) and all can adopt multiple conductive material, as long as being capable of its conducting function.
In the process of the ESD structure in actual fabrication array base palte, it is preferred that first connects medium and second connects the conductive material that medium employing is identical; Source and drain metal level, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) all adopt identical conductive material. This makes it possible to concurrently form the first connection medium and second and connect medium by being once deposited with operation, and the input 10 of outfan 6, second thin film transistor (TFT) of source and drain metal level, the input 5 of the first film transistor, the first film transistor and the outfan 11 of the second thin film transistor (TFT) can be concurrently formed in a patterning processes.
It is more highly preferred to, by source and drain metal level, first connects medium, second connects medium, the input 5 of the first film transistor, the outfan 6 of the first film transistor, the input 10 of the second thin film transistor (TFT) and the outfan 11 of the second thin film transistor (TFT) all adopt identical conductive material, source and drain metal level while of this makes it possible in a patterning processes, form the first connection medium, second connects medium, the input 5 of the first film transistor, the outfan 6 of the first film transistor, the input 10 of the second thin film transistor (TFT) and the outfan 11 of the second thin film transistor (TFT), thus well improve production efficiency, reduce production cost. the kind of the conductive material that above-described embodiment is mentioned has a lot, for instance: transparent metal-oxide, metal, but it is not limited only to this. below with the material of both types illustrate when source and drain metal level, first connect medium, second connect medium, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) select different conductive material, the different-effect having.
When source and drain metal level, first connect medium, second connect medium, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) all select this conductive material of transparent metal-oxide time, it is possible to the transparent metal-oxides such as selective oxidation indium stannum (ITO), aluminium-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO);Preferably, source and drain metal level, first connect medium, second connect medium, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) and all select this conductive material of ITO, there is good electric conductivity and transparency due to ITO, ITO is used to can be good at improving the aperture opening ratio of TFT-LCD as conductive material, so that TFT-LCD realizes better display effect; And the pixel electrode in TFT-LCD it is also commonly used as due to ITO, so when ESD structure is applied in TFT-LCD, can by source and drain metal level, first connect medium, second connect the outfan 11 of input the 10, second thin film transistor (TFT) of outfan the 6, second thin film transistor (TFT) of medium, the input 5 of the first film transistor, the first film transistor and pixel electrode is formed in a patterning processes, further save production cost, improve production efficiency. It should be noted that, owing to ITO has higher resistivity, when source and drain metal level adopts ITO as conductive material, be not suitable for making large-sized array base palte, otherwise can there is the phenomenon of signal delay, namely, when source and drain metal level adopts ITO as conductive material, it is more suitable for making in some array base paltes to the relatively low small-medium size of resistance requirements.
When selecting metal as conductive material, the various metals such as Al, Mo, Mg, Ag can be selected, owing to the resistivity of metal self is very low, can be good at avoiding the phenomenon of signal delay, therefore, adopt metal as conductive material, it is possible to make large-sized array base palte that resistance requirements is higher.
Please continue to refer to Fig. 1, the embodiment of the present invention additionally provides the manufacture method of a kind of array base palte, for making the array base palte that above-described embodiment provides, comprises the following steps:
One underlay substrate 1 is provided, described underlay substrate 1 makes tft array and ESD structure;
When the first film transistor made in ESD structure, after forming the gate insulator 2 of the first film transistor, before forming the semiconductor layer 3 of the first film transistor, the gate insulator 2 of the first film transistor forms the first via 12; After forming the semiconductor layer 3 of the first film transistor, the first via 12 forms the first connection medium;
When the second thin film transistor (TFT) made in ESD structure, after forming the gate insulator 7 of the second thin film transistor (TFT), before forming the semiconductor layer 8 of the second thin film transistor (TFT), the gate insulator 7 of the second thin film transistor (TFT) forms the second via 13; After forming the semiconductor layer 8 of the second thin film transistor (TFT), the second via 13 forms the second connection medium.
Concrete, structure due to the thin film transistor (TFT) in tft array, identical with the structure of the first film transistor in ESD structure and the second thin film transistor (TFT), therefore, it can make the thin film transistor (TFT) in tft array and the first film transistor in ESD structure and the second thin film transistor (TFT) simultaneously. So in the process making array base palte, it is possible to concurrently form the gate insulator 7 of the gate insulator in tft array, the gate insulator 2 of the first film transistor and the second thin film transistor (TFT) in a patterning processes; As shown in Figure 4, in a patterning processes, then concurrently form the first via 12 and the second via 13; As shown in Figure 5 and Figure 6, then in a patterning processes, concurrently form the semiconductor layer 8 of the semiconductor layer in tft array, the semiconductor layer 3 of the first film transistor and the second thin film transistor (TFT), and the semiconductor layer 8 institute raceway groove one to one of the semiconductor layer 3 of semiconductor layer in tft array, the first film transistor and the second thin film transistor (TFT);Then in the first via 12, form the first connection medium, the second via 13 is formed the second connection medium; As shown in Figure 1; then the input 10 of outfan 6, second thin film transistor (TFT) of source and drain metal level, the input 5 of the first film transistor, the first film transistor and the outfan 11 of the second thin film transistor (TFT) are deposited; so that the ESD structure in array base palte is formed; and it is capable of electrostatic protection function; finally according to carrying out the etching of source and drain metal level, via mask and pixel electrode mask, complete the making of array base palte.
It should be noted that multiple technologies can be adopted to form the semiconductor layer 8 of semiconductor layer the 3, second thin film transistor (TFT) of first via the 12, second via 13, the first film transistor and the raceway groove of correspondence, it is preferred that utilize intermediate tone mask technology; Owing to this intermediate tone mask technology can save one exposure process, extra number of mask will not be increased, save production cost to a great extent. Additionally, the generally individually bi-material that includes of semiconductor layer 8 of the semiconductor layer 3 of the first film transistor and the second thin film transistor (TFT), one is polysilicon, another kind is n+��-Si, by n+The etching of ��-Si forms corresponding raceway groove.
In the manufacture method of the array base palte that above-described embodiment provides, after having deposited the source and drain metal level of tft array, the input of the first film transistor, the outfan of the first film transistor, the input of the second thin film transistor (TFT) and the outfan of the second thin film transistor (TFT), namely define complete ESD structure; When carrying out etching and stripping photoresist 14, via mask and the pixel electrode mask of follow-up source and drain metal level, the electrostatic of generation just can well be discharged by ESD structure, thus reducing ESD event occurrence probability in array base palte manufacturing process.
The the first connection medium provided due to above-described embodiment and the second connection medium act primarily as the effect of conducting, namely the material having only to be selected to conduction forms the first connection medium and the second connection medium, preferably, by source and drain metal level, first connects medium, the input 5 of the first film transistor, the outfan 6 of the first film transistor, second connects medium, the input 10 of the second thin film transistor (TFT) and the outfan 11 of the second thin film transistor (TFT) all adopt identical conductive material, and in a patterning processes, concurrently form source and drain metal level, first connects medium, the input 5 of the first film transistor, the outfan 6 of the first film transistor, second connects medium, the input 10 of the second thin film transistor (TFT) and the outfan 11 of the second thin film transistor (TFT), namely need not increase extra the first connection medium and second that makes and connect the step of medium, while improve production efficiency, also a saving production cost.
Source and drain metal level that above-described embodiment provides, first connect medium, second connect the conductive material that medium, the input 5 of the first film transistor, the input 10 of outfan the 6, second thin film transistor (TFT) of the first film transistor and the outfan 11 of the second thin film transistor (TFT) can select and have a variety of, such as: transparent metal-oxide or metal, the effect that different materials brings is adopted specifically to refer to the description of structure division.
In the description of above-mentioned embodiment, specific features, structure, material or feature can combine in an appropriate manner in any one or more embodiments or example.
The above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (9)
1. an array base palte, including at least one ESD structure, described ESD structure includes the first film transistor and the second thin film transistor (TFT), the end that controls of described the first film transistor is connected with the input of described the first film transistor, and be connected with the holding wire in described array base palte, the input of described the first film transistor is connected with the outfan of described second thin film transistor (TFT), and the outfan of described the first film transistor is connected with the input of described second thin film transistor (TFT); The end that controls of described second thin film transistor (TFT) is connected with the input of described second thin film transistor (TFT), and is connected with the public electrode in described array base palte, it is characterised in that
The gate insulator of described the first film transistor is provided with the first via, is provided with the first connection medium in described first via, and described first connects medium for connecting the input controlling end and described the first film transistor of described the first film transistor;
The gate insulator of described second thin film transistor (TFT) is provided with the second via, is provided with the second connection medium in described second via, and described second connects medium for connecting the input controlling end and described second thin film transistor (TFT) of described second thin film transistor (TFT).
2. array base palte according to claim 1, it is characterized in that, described first connect medium, described second connect the source and drain metal level of tft array in medium, the input of described the first film transistor, the outfan of described the first film transistor, the input of described second thin film transistor (TFT), the outfan of described second thin film transistor (TFT) and described array base palte and all adopt identical conductive material.
3. array base palte according to claim 2, it is characterised in that described conductive material is transparent metal-oxide.
4. array base palte according to claim 2, it is characterised in that described conductive material is metal.
5. the manufacture method of array base palte as according to any one of claim 1-4, it is characterised in that comprise the following steps:
One underlay substrate is provided, described underlay substrate makes tft array and ESD structure;
When the first film transistor made in described ESD structure, after forming the gate insulator of described the first film transistor, before forming the semiconductor layer of described the first film transistor, the gate insulator of described the first film transistor forms the first via;
After forming the semiconductor layer of described the first film transistor, described first via forms the first connection medium;
When the second thin film transistor (TFT) made in described ESD structure, after forming the gate insulator of described second thin film transistor (TFT), before forming the semiconductor layer of described second thin film transistor (TFT), the gate insulator of described second thin film transistor (TFT) forms the second via;
After forming the semiconductor layer of described second thin film transistor (TFT), described second via forms the second connection medium.
6. the manufacture method of array base palte according to claim 5, it is characterized in that, form described first by patterning processes and connect medium, the input of described the first film transistor, the outfan of described the first film transistor, the second source and drain metal level connecting medium, the input of described second thin film transistor (TFT), the outfan of described second thin film transistor (TFT) and described tft array.
7. the manufacture method of array base palte according to claim 6, it is characterised in that described conductive material is transparent metal-oxide.
8. the manufacture method of array base palte according to claim 6, it is characterised in that described conductive material is metal.
9. the manufacture method of array base palte according to claim 6, it is characterised in that concurrently form the gate insulator of described the first film transistor and the gate insulator of described second thin film transistor (TFT) in a patterning processes;
A patterning processes concurrently forms described first via and described second via;
A patterning processes concurrently forms the semiconductor layer of described the first film transistor and the semiconductor layer of described second thin film transistor (TFT).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106200172A (en) * | 2016-07-14 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| WO2020019908A1 (en) * | 2018-07-25 | 2020-01-30 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display apparatus |
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| US20040188682A1 (en) * | 2003-03-24 | 2004-09-30 | Katsura Hirai | Thin-film transistor, thin-film transistor sheet and their manufacturing method |
| CN202183003U (en) * | 2011-08-19 | 2012-04-04 | 北京京东方光电科技有限公司 | Anti-static structure of array substrate |
| CN203218262U (en) * | 2013-03-06 | 2013-09-25 | 京东方科技集团股份有限公司 | Electrostatic protection unit, electrostatic protection structure, array base plate and display panel |
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| US20040188682A1 (en) * | 2003-03-24 | 2004-09-30 | Katsura Hirai | Thin-film transistor, thin-film transistor sheet and their manufacturing method |
| CN202183003U (en) * | 2011-08-19 | 2012-04-04 | 北京京东方光电科技有限公司 | Anti-static structure of array substrate |
| CN203218262U (en) * | 2013-03-06 | 2013-09-25 | 京东方科技集团股份有限公司 | Electrostatic protection unit, electrostatic protection structure, array base plate and display panel |
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| CN106200172A (en) * | 2016-07-14 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
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| US11296074B2 (en) | 2018-07-25 | 2022-04-05 | Boe Technology Group Co., Ltd. | Electrostatic protection circuit and manufacturing method thereof, array substrate and display apparatus |
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Application publication date: 20160608 |