CN105633254B - A kind of high pressure flip chip structure and preparation method thereof - Google Patents
A kind of high pressure flip chip structure and preparation method thereof Download PDFInfo
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- CN105633254B CN105633254B CN201511024194.XA CN201511024194A CN105633254B CN 105633254 B CN105633254 B CN 105633254B CN 201511024194 A CN201511024194 A CN 201511024194A CN 105633254 B CN105633254 B CN 105633254B
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- 238000002955 isolation Methods 0.000 claims abstract description 14
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
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- 238000005516 engineering process Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 238000000576 coating method Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
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- 229910052594 sapphire Inorganic materials 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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Abstract
A kind of high pressure flip chip structure and preparation method thereof, the chip structure is disposed with substrate, N-type GaN layer, Quantum well active district, p-type GaN layer, reflection layer and metal barrier from top to bottom, it is provided with P electrode in p-type GaN layer, it is provided with N electrode in N-type GaN layer, place on reflection layer except P electrode and N electrode is provided with the barrier layers TiW, TiW is provided with insulating layer on barrier layer, the bottom of P electrode and N electrode is provided with the poles N pad by electrode metal film, and insulating layer between pad is provided between the poles P pad and the poles N pad；Preparation method includes the following steps：It prepares insulating layer between epitaxial wafer, vapor deposition reflection layer, deposited metal barrier layer, plated electrode metal film, cutting isolation channel, depositing insulating layer, plating FC metal films, making pad and is cut into.The present invention realizes big voltage driving, it is therefore prevented that the metal of reflection layer is diffused, good insulating, improves the stability and reliability of chip and device.
Description
Technical field
The present invention relates to a kind of structures and preparation method thereof of high pressure flip-chip, belong to LED (light emitting diode) chip
Preparing technical field.
Background technology
As global electronic personalization of product, the luxuriant demand lightly changed are agitation, encapsulation technology, which has improved, arrives CSP (Chip
Size Package).It reduces the size of chip package shape, it is much to accomplish that naked core chip size has, package dimension just has more
Greatly.CSP encapsulation not only meets chip I/ever-increasing needs of O pins, but also the ratio between chip area and package area
It is worth very little, greatly shortens delay time.Therefore flip chip fabrication process cause industry note that even have it is many in the industry
Personage predicts the mainstream technology that this technique will encapsulate as the following LED.
The positive cartridge chips of LED are the chip structures occurred earliest and the chip structure that is generally used in small-power chip.It should
Structure is as shown in Figure 1, electrode above, is followed successively by P electrode 5, current extending 6, p-type GaN layer 4, Quantum Well from top to bottom has
Source region 3, N-type GaN layer 2, N electrode 7, substrate 1, substrate 1 are connected to by crystal-bonding adhesive 4 on substrate 9.Because electrode squeezes in positive cartridge chip
Light-emitting area is accounted for constrain its luminous efficiency, while the heat of the chip PN junction of positive assembling structure is led by Sapphire Substrate 1
It goes out, thermally conductive pathways are long, and sapphire thermal coefficient is low compared with metal material, while LED chip thermal resistance leads to greatly device
Hot property is poor, and P electrode 5 blocks some light.With the power, light extraction efficiency and heat of the packed LED chip packaging
Performance is affected.
In order to solve the problems, such as that above-mentioned traditional packed LED chip exists, industry is proposed a kind of flip LED chips (abbreviation
FC, Flip-Chip), structure is as shown in Fig. 2, substrate 1 is located at the top of LED chip, in the lower section of substrate 1 successively equipped with N
Type GaN layer 2, Quantum well active district 3, p-type GaN layer 4, current extending 6 and reflection layer 10；It is etched using ICP lithographic techniques
N electrode 7 is formed to the areas N, reflection layer bottom makes P electrode 5；N electrode 7 and P electrode 5 pass through metal salient point 11,12 and solder
Layer 13 is welded with substrate 9.Light is sent out from substrate 1 in the flip LED chips structure, and light-emitting area increases, but in the structure
PN junction heat is conducted by metal salient point 11,12 in substrate 9, and extreme temperatures herein are caused, when LED chip increases power,
The heat of generation timely and effective can not shed, and luminous efficiency is made to decline, while temperature raising can cause LED life to reduce.Separately
Outside due to it is referred to above to positive cartridge chip and flip-chip be all by complete epitaxial wafer disk carry out tube core technique making
Independent junior unit one by one is cut into after the completion, and each unit is a LED chip, and there are one anode, one on every chips
A cathode, the voltage of single LED chip is generally in 3V or so, so if needing that single envelope can only be carried out when increasing voltage
Dress is connected again, can inevitably increase the difficulty of encapsulation and application, and technology difficulty increases, and makes the less reliable of entire chip.
Disclosed in Chinese patent literature CN103872195A《Novel inverted high-voltage chip epitaxial wafer》, it is proposed that a kind of use
The light-emitting film of chip technology can be incorporated as insulating layer, for solving in high pressure flip-chip insulation layer process, the sky left
Influence of the hole to light emission luminance, and electric leakage danger.But the upside-down mounting high-voltage chip epitaxial wafer is still using traditional gold
It is conductive to belong to salient point, when working under larger current, the heat that heat or the LED chip work of welding generate can make LED chip temperature
Degree increases, and influences LED chip functional reliability, the heat conduction of LED chip and stability problem are not still resolved.
Invention content
For a kind of insufficient existing for traditional positive cartridge chip and existing flip LED chips technology, welding of present invention offer
The high pressure flip chip structure that face is big, thermal diffusivity is good, reliability is high, while a kind of preparation method of the structure being provided.
The high pressure flip chip structure of the present invention, using following technical scheme：
The structure is disposed with substrate, N-type GaN layer, Quantum well active district, p-type GaN layer, reflection layer from top to bottom
And metal barrier, P electrode is provided in p-type GaN layer, is provided with N electrode in N-type GaN layer, in P electrode and N on reflection layer
Place except electrode is provided with the barrier layers TiW, and insulating layer, the bottom setting of P electrode and N electrode are provided on the barrier layers TiW
There is electrode metal film, the poles P pad is provided on the electrode metal film of P electrode bottom, is arranged on the electrode metal film of N electrode bottom
There is the poles N pad, insulating layer between pad is provided between the poles P pad and the poles N pad.
The thickness of the reflection layer is 1500-2000 angstroms.
The metal barrier uses two kinds of element mass ratioes 2 of Ti and W:1 mixture, thickness are 800-1000 angstroms.
The electrode metal film is Al, Cr and Ni mass ratio 5:2:1 mixture, thickness are 8000-10000 angstroms.
The thickness of insulating layer is 3000-5000 angstroms between the pad.
The preparation method of above-mentioned high pressure flip chip structure, includes the following steps：
(1) epitaxial wafer is prepared；
It grows N-type GaN layer, Quantum well active district and p-type GaN layer successively on substrate, forms epitaxial wafer；
(2) reflection layer is deposited；
Reflection layer is deposited on the p-type GaN layer surface of epitaxial wafer, photoresist is recycled to do mask, prepare P electrode figure and
The reflection layer covered on N electrode figure, erosion removal P electrode figure and N electrode figure, then remove photoresist mask；
(3) deposited metal barrier layer；
Depositing Ti W barrier layer on the basis of step (2)；It recycles photoresist to do mask, prepares P electrode figure and N electricity
Pole figure shape, the metal barrier then covered on erosion removal P electrode figure and N electrode figure finally remove photoresist mask；
(4) plated electrode metal film；
Mask is done using photoresist, makes P electrode figure and N electrode figure；The etching removal p-type GaN on N electrode figure
Layer and Quantum well active district make N-type GaN layer expose, and form N electrode, p-type GaN layer, the p-type of exposing are etched on P electrode figure
GaN layer is P electrode；One layer of electrode metal film is deposited on surface again, peels off the electrode metal film except P electrode and N electrode,
Only retain the electrode metal film in P electrode and N electrode；
(5) isolation channel is cut；
It is cut, forms single chip unit, be cut at substrate, make to form isolation channel between adjacent chips unit；
(6) depositing insulating layer；
Deposit SiO2Insulating layer, the filler using in the protective layer and isolation channel as chip unit surface, corrosion are gone
Except the SiO in P electrode and N electrode2Insulating layer；
(7) FC metal films are plated；
Evaporated metal layer again makes the poles P pad and the poles N pad plate FC metal films, while making every row adjacent chips unit
Between carry out the poles P and the poles N metallization connection, realize the series connection of chip；
FC (English refers to Flip-Chip) is abbreviation of the industry to upside-down mounting welding core, referred to herein as FC metal coatings：When for
It is distinguished with (4) step electrode metal plated film；Second is that related with purposes, metal coating is in order to which the chip of falling stake is welded in base at this
On plate.
(8) insulating layer between making pad；
Deposition SiO is carried out again2, the SiO on erosion removal P pole pads and the poles N pad2, make between the poles P pad and the poles N pad
Fill SiO2Insulating layer；
(9) required high pressure flip-chip is cut into along isolation channel.
FC metal coatings in the step (7) use Au, Cr, Ti and Ni mass ratio for 4:2:1:1 mixed metal is thick
3000-5000 angstroms of degree.
The invention has the characteristics that：
1. the present invention connects in advance from flip LED chips manufacturing process, high pressure flip-chip is formed, realizes big electricity
Pressure driving, while avoid single chip is packaged connect again caused by waste of raw materials problem；
2. one aspect of the present invention prevents the metal of reflection layer from being expanded on one layer of barrier layer of external sediment of reflection layer
It dissipates, makes preferably to insulate between P, N electrode, on the other hand the secondary setting SiO between the pad of the pole P, N2Insulating layer, avoids down
Short circuit problem when cartridge chip die bond greatly improves the stability of chip and device.
3. invention increases the P electrode of flip-chip and N electrode bonding pad area, so that chip preferably radiates, drop
Low required precision of the high-power flip-chip to Welding Technology and Equipment, while improving the reliability of chip.
Description of the drawings
Fig. 1 is the structural schematic diagram of existing packed LED chip.
Fig. 2 is the structural schematic diagram of existing flip LED chips.
Fig. 3 is the cross-sectional view of the high pressure flip LED chips of the present invention.
Fig. 4 is the schematic bottom view of high pressure flip LED chips before being cut in the present invention.
Fig. 5 is the schematic bottom view of single high pressure flip LED chips in the present invention.
In figure：1, substrate, 2, N-type GaN layer, 3, Quantum well active district, 4, p-type GaN layer, 5, P electrode, 6, current expansion
Layer, 7, N electrode, 8, crystal-bonding adhesive, 9, substrate, 10, reflection layer, 11, N electrode metal salient point, 12, P electrode metal salient point, 13,
Solder layer, 14, metal linking bar, 15, SiO2Insulating layer, 16, electrode metal film, the isolation channel between 17, chip, 18, the weldering of the poles P
Disk, 19, the poles N pad, 20, the barrier layers TiW, SiO between 21, pad2Insulating layer.
Specific implementation mode
The high pressure flip chip structure of the present invention, structure as shown in figure 3, be disposed with substrate 1, N-type from top to bottom
GaN layer 2, Quantum well active district 3, p-type GaN layer 4, reflection layer 10 and the barrier layers TiW 20 are provided with P electrode in p-type GaN layer 4
5, it is provided with N electrode 7 in N-type GaN layer 2, the place on reflection layer 10 except P electrode 5 and N electrode 7 is provided with TiW blockings
Layer 20.It is provided with SiO on the barrier layers TiW 202Insulating layer 15.The bottom of P electrode 5 and N electrode 7 is provided with electrode metal layer 16, P
It is provided with the poles P pad 18 on the electrode metal layer of 5 bottom of electrode, the poles N pad is provided on the electrode metal layer of 7 bottom of N electrode
It is provided with SiO between pad between 19, P pole pads 18 and the poles N pad 192Insulating layer 21.
The thickness of reflection layer 10 is 1500-2000 angstroms.The thickness on the barrier layers TiW 20 is 800-1000 angstroms.Electrode metal
The thickness of layer 16 is 8000-10000 angstroms.SiO between pad2The thickness of insulating layer 21 is 3000-5000 angstroms.
The preparation method of above-mentioned high pressure flip chip structure, includes the following steps：
(1) epitaxial wafer is prepared
As shown in figure 3, using sapphire as substrate 1, in 1 growing epitaxial layers of substrate, epitaxial wafer is formed；Epitaxial layer by down toward
On be followed successively by N-type GaN layer 2, Quantum well active district 3 and p-type GaN layer 4.
(2) reflection layer 10 is deposited
It is 1500-2000 angstroms that a layer thickness, which is deposited, in the p-type GaN layer 4 on epitaxial wafer surface using electron beam evaporation platform
Reflection layer 10, the reflection layer 10 are that Ag and Ti mass ratioes are 5:2 mixture.It recycles photoresist to do mask, prepares P electricity
Then pole figure shape and N electrode figure are removed the reflection layer 10 covered on P electrode figure and N electrode figure using wet etching
It removes, finally removes photoresist mask.
(3) deposited metal barrier layer 20
The metal Ag elements of reflection layer 10 are diffused in order to prevent, are made preferably exhausted between P electrode 5 and N electrode 7
Edge is used using the physical vaporous deposition barrier layers TiW 20 that deposition thickness is 800-1000 angstroms on the basis of step (2)
Ti and W mass ratioes 2:1 mixture.It recycles photoresist to do mask, prepares P electrode figure and N electrode figure, then utilize wet
Method corrosion removes the barrier layers TiW 20 covered on P electrode figure and N electrode figure, finally removes photoresist mask.
(4) plated electrode metal film
On the basis of step (3), mask is done using photoresist, makes P electrode figure and N electrode figure.In N electrode figure
Using ICP etching removal p-types GaN layer 4 and Quantum well active district 3, etching depth 1.3-1.5um in shape, N-type GaN layer 2 is made to reveal
Go out, forms N electrode 7.P-type GaN layer 4 is etched on P electrode figure, P electrode 5 is the p-type GaN layer 4 exposed.On this basis
Layer of metal film is deposited in deposited by electron beam evaporation platform, then uses lift-off technology by the metal removal except P electrode 5 and N electrode 7,
Only retain electrode metal film 16.The electrode metal film of vapor deposition be 8000-10000 angstroms of thickness Al, Cr and Ni mixed metal, three kinds
The mass ratio of element is 5:2:1.Form the high pressure flip LED chips before Fig. 3 and segmentation shown in Fig. 4.
(5) isolation channel 17 is cut
In conjunction with Fig. 3 and high pressure flip LED chips shown in Fig. 4, is cut on the basis of step (4), be cut to lining
At bottom 1, isolation channel 17 is formed between adjacent chips unit, the depth of isolation channel 17 is 5.5-6.5um.
(6) SiO is deposited2Insulating layer 15
By metal-organic chemical vapor deposition equipment method (PECVD), deposition thickness is 850-950 on the basis of step (5)
Angstrom SiO2Insulating layer 15, using as chip unit surface protective layer and isolation channel 17 in filler, utilize wet method rotten
It loses the SiO in P electrode 5 and N electrode 72Removal.
(7) FC metal films are plated
In order to increase bonding pad area to solve the heat dissipation problem of chip, using Photolithography Technology, 18 He of the poles P pad is made
19 figure of the poles N pad, the area of the visible poles P pad 18 and the poles N pad 19 is than the area of P electrode 5 and N electrode 7 bigger according to fig. 3
It is more.Electrode evaporation metal, i.e. the FC metal coatings of 3000-5000 angstroms of thickness again on the basis of step (6), using Au, Cr,
The mass ratio of Ti and Ni mixed metals, four kinds of elements is 4:2:1:1.Using lift-off technology, make the poles P pad 18 and the poles N pad 19
Metal is plated, while the P electrode 5 between every row adjacent chips unit being made to be connected by metal linking bar 14 with N electrode 7, it is real
The series connection of existing chip (referring to Fig. 3).
(8) between the poles P pad 18 and the poles N pad 19 make pad between SiO2Insulating layer 21
Occurs the possibility of short circuit between the poles P pad 18 and the poles N pad 19 in order to prevent, on the basis of step (7) again
Carry out deposition SiO2, using wet etching by the SiO on the poles P pad 18 and the poles N pad 192Removal makes the poles P pad 18 and the poles N weld
The SiO that 19 filling thickness of disk are 3000-5000 angstroms2Insulating layer 21.
(9) required single high pressure shown in fig. 5 is cut into according to the requirement (voltage, power, brightness etc.) of encapsulation client
Flip-chip.
Claims (2)
1. a kind of high pressure flip chip structure is disposed with substrate, N-type GaN layer, Quantum well active district, p-type from top to bottom
GaN layer and reflection layer, characterized in that be provided with P electrode in p-type GaN layer, N electrode, reflection layer are provided in N-type GaN layer
On place except P electrode and N electrode be provided with metal barrier, insulating layer, P electrode and N are provided on metal barrier
The bottom of electrode is provided with electrode metal film, and the poles P pad, the electricity of N electrode bottom are provided on the electrode metal film of P electrode bottom
It is provided with the poles N pad on the metal film of pole, insulating layer between pad is provided between the poles P pad and the poles N pad；The reflection layer
Thickness is 1500-2000 angstroms；The metal barrier uses two kinds of element mass ratioes 2 of Ti and W:1 mixture, thickness 800-
1000 angstroms；The electrode metal film is Al, Cr and Ni mass ratio 5:2:1 mixture, thickness are 8000-10000 angstroms；The institute
The thickness for stating insulating layer between pad is 3000-5000 angstroms.
2. the preparation method of high pressure flip chip structure described in a kind of claim 1, characterized in that include the following steps：
（1）Prepare epitaxial wafer；
It grows N-type GaN layer, Quantum well active district and p-type GaN layer successively on substrate, forms epitaxial wafer；
（2）Reflection layer is deposited；
Reflection layer is deposited on the p-type GaN layer surface of epitaxial wafer, photoresist is recycled to do mask, prepares P electrode figure and N electricity
The reflection layer covered on pole figure shape, erosion removal P electrode figure and N electrode figure, then remove photoresist mask；
（3）Deposited metal barrier layer；
In step（2）On the basis of depositing Ti W barrier layer；It recycles photoresist to do mask, prepares P electrode figure and N electrode figure
Shape, the metal barrier then covered on erosion removal P electrode figure and N electrode figure finally remove photoresist mask；
（4）Plated electrode metal film；
In step（3）On the basis of, mask is done using photoresist, makes P electrode figure and N electrode figure；On N electrode figure
Etching removal p-type GaN layer and Quantum well active district, make N-type GaN layer expose, and form N electrode, p-type GaN is etched on P electrode figure
Layer, the p-type GaN layer of exposing is P electrode；One layer of electrode metal film is deposited on surface again, peels off except P electrode and N electrode
Electrode metal film, only retain the electrode metal film in P electrode and N electrode；
（5）Cut isolation channel；
It is cut, forms single chip unit, be cut at substrate, make to form isolation channel between adjacent chips unit；
（6）Depositing insulating layer；
Deposit SiO2Insulating layer, the filler using in the protective layer and isolation channel as chip unit surface, erosion removal P electricity
SiO on pole and N electrode2Insulating layer；
（7）Plate FC metal films；
Evaporated metal layer again makes the poles P pad and the poles N pad plate FC metal films, while making between every row adjacent chips unit
The poles P and the metallization connection of the poles N are carried out, realizes the series connection of chip；
（8）Insulating layer between making pad；
Deposition SiO is carried out again2, the SiO on erosion removal P pole pads and the poles N pad2, make to fill between the poles P pad and the poles N pad
SiO2Insulating layer；
（9）Required high pressure flip-chip is cut into along isolation channel；
The step（7）In FC metal films use Au, Cr, Ti and Ni mass ratio for 4:2:1:1 mixed metal, thickness
3000-5000 angstroms.
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| CN105914582B (en) * | 2016-06-03 | 2019-06-11 | 武汉华工正源光子技术有限公司 | A kind of production method and monolithic integrated device of monolithic integrated device |
| CN107452846B (en) * | 2017-09-25 | 2024-05-14 | 广东工业大学 | Ultraviolet LED flip chip |
| CN108110126A (en) * | 2017-12-26 | 2018-06-01 | 杭州士兰明芯科技有限公司 | The production method of pad structure and the production method of flip LED chips |
| CN108091753B (en) * | 2018-01-22 | 2023-08-25 | 扬州大学 | Light source element |
| CN108807621B (en) * | 2018-06-29 | 2024-11-01 | 华南理工大学 | Two-dimensional photonic crystal LED flip chip shared by illumination and communication and preparation method thereof |
| CN116364816B (en) * | 2023-05-31 | 2023-08-25 | 南昌凯捷半导体科技有限公司 | Thermoelectric separation AlGaInP LED chip and manufacturing method |
| CN117810318B (en) * | 2024-02-29 | 2024-05-07 | 江西兆驰半导体有限公司 | High-voltage Micro-LED chip and preparation method thereof |
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| CN103489983A (en) * | 2012-06-11 | 2014-01-01 | 铼钻科技股份有限公司 | Flip-chip light emitting diode and manufacturing method and application thereof |
| CN104733600A (en) * | 2013-12-20 | 2015-06-24 | 晶能光电（江西）有限公司 | Flip LED chip and preparing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103489983A (en) * | 2012-06-11 | 2014-01-01 | 铼钻科技股份有限公司 | Flip-chip light emitting diode and manufacturing method and application thereof |
| CN104733600A (en) * | 2013-12-20 | 2015-06-24 | 晶能光电（江西）有限公司 | Flip LED chip and preparing method thereof |
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