CN105633057A - Thin film transistor structure, display panel, array substrate and manufacturing method thereof - Google Patents
Thin film transistor structure, display panel, array substrate and manufacturing method thereof Download PDFInfo
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- CN105633057A CN105633057A CN201410580594.8A CN201410580594A CN105633057A CN 105633057 A CN105633057 A CN 105633057A CN 201410580594 A CN201410580594 A CN 201410580594A CN 105633057 A CN105633057 A CN 105633057A
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Abstract
The invention provides a thin film transistor array substrate, which comprises a plurality of scan lines, a plurality of data lines in insulated intersection with the plurality of scan lines, and a plurality of pixels. The scan lines are composed of first scan lines. The data lines are composed of first data lines and second data lines, wherein the first data lines and the second data lines are mutually insulated and are overlapped with each other. The thin film transistor array substrate further comprises a first thin film transistor used for driving pixels on one side of the first scan lines, and a second thin film transistor used for driving pixels on the other side of the first scan lines. The first thin film transistor is electrically connected with the first scan lines and the first data lines. The second thin film transistor is electrically connected with the first scan lines and the second data lines. The thin film transistor array is capable of effectively improving the aperture ratio of a display panel. The invention also provides a manufacturing method of the thin film transistor array substrate, a display panel and a thin film transistor structure.
Description
Technical field
The present invention relates to the manufacture method of a kind of thin-film transistor structure, thin-film transistor array base-plate, display floater and this thin-film transistor array base-plate.
Background technology
Display floater, such as: display panels, organic LED display panel generally adopt thin-film transistor array base-plate as active circuits layer. Wherein, described thin-film transistor array base-plate includes the staggered multi-strip scanning holding wire of transverse and longitudinal and a plurality of data signal line. Each scan signal line arranges a thin film transistor (TFT) to control a sub-pixel with data signal line intersection. But, the opaque holding wire in above-mentioned thin film transistor (TFT) array can cause that the aperture opening ratio of display floater is not high.
Summary of the invention
In consideration of it, be necessary to provide a kind of thin-film transistor array base-plate, it includes a plurality of data lines and the multiple pixel that multi-strip scanning line intersects with the insulation of described scanning line. Described scanning line includes scan line. Described data wire includes mutually insulated and the first data wire overlapped and the second data wire. This thin-film transistor array base-plate farther includes for driving the first film transistor being positioned at this scan line side pixel and for driving the second thin film transistor (TFT) being positioned at this scan line opposite side pixel. Scan line described in described the first film transistor AND gate and the first data wire are electrically connected. Described second thin film transistor (TFT) is electrically connected with described scan line and the second data wire.
There is a need to provide a kind of display floater. This display floater includes described thin-film transistor array base-plate.
There is a need to provide the manufacture method of a kind of thin-film transistor array base-plate, the method comprises the steps:
Substrate is provided, and forms the second source electrode, the second drain electrode on the substrate and be electrically connected the second data wire of this second source electrode;
Described second source electrode, the second drain electrode and substrate are formed two ends and is covered each by described second source electrode and the second channel layer of the second drain electrode;
Form the second grid insulating barrier covering described second source electrode, the second drain electrode, the second data wire, second channel layer and substrate;
Described second grid insulating barrier is formed the grid of corresponding described second channel layer and electrically connects the scan line of this grid;
Described second grid insulating barrier is formed the first grid insulating barrier covering described grid and scan line;
Described first grid insulating barrier is formed the first passage layer of corresponding described grid; And
Described first grid insulating barrier with first passage layer are formed and is respectively overlay in first source electrode at described first passage layer two ends, the first drain electrode and is electrically connected the first data wire of this first source electrode.
There is a need to provide the manufacture method of a kind of thin-film transistor array base-plate, the method comprises the steps:
Substrate is provided, and forms second channel layer on the substrate;
Described second channel layer is formed and is respectively overlay in second source electrode at described second channel layer two ends, the second drain electrode and electrically connects the second data wire of this second source electrode;
Form the second grid insulating barrier covering described second source electrode, the second drain electrode, the second data wire, second channel layer and substrate;
Not by the grid of described second source electrode and the second channel layer of the second drain electrode covering and the scan line electrically connecting this grid described in forming position correspondence on described second grid insulating barrier;
Described second grid insulating barrier is formed the first grid insulating barrier covering described grid and scan line;
The first passage layer of the corresponding described grid of forming position on described first grid insulating barrier; And
It is respectively overlay in first source electrode at described first passage layer two ends, the first drain electrode at described first grid insulating barrier with first passage layer is formed and electrically connects the first data wire of this first source electrode.
There is a need to provide a kind of thin-film transistor structure, it includes the first film transistor AND gate the second thin film transistor (TFT) that stacking is arranged, and a grid shared by the second thin film transistor (TFT) described in described the first film transistor AND gate.
Compared to prior art, display floater provided by the present invention, thin-film transistor array base-plate and preparation method thereof corresponding can control two pixel regions due to a data line, it is possible to be effectively improved the aperture opening ratio of display floater.
Accompanying drawing explanation
The schematic diagram of the display floater that Fig. 1 provides for the specific embodiment of the invention.
Fig. 2 is the top view of thin-film transistor array base-plate in Fig. 1.
Fig. 3 is the first embodiment of thin-film transistor array base-plate of the present invention sectional view of III-III line of cut along Fig. 2.
Fig. 4 is the second embodiment of thin-film transistor array base-plate of the present invention sectional view of III-III line of cut along Fig. 2.
Fig. 5 is the flow chart of the manufacture method of thin-film transistor array base-plate in Fig. 3.
Fig. 6-17 is each step decomposing schematic representation in Fig. 5 flow chart.
Figure 18 is the flow chart of the manufacture method of thin-film transistor array base-plate in Fig. 4.
Figure 19-30 is each step decomposing schematic representation in Figure 18 flow chart.
Main element symbol description
| Display floater | 100 |
| First substrate, thin-film transistor array base-plate | 110 |
| Second substrate, opposite substrate | 120 |
| Liquid crystal layer | 130 |
| Scanning line | SL |
| Data wire | DL |
| Pixel region | P |
| Scan line | SLa |
| Second scanning line | SLb |
| First data wire | DLa |
| Second data wire | DLb |
| The first film transistor | 111 |
| Second thin film transistor (TFT) | 112 |
| Substrate | 113 |
| Pixel electrode | 114 |
| Grid | 111a |
| First passage layer | 111b |
| First source electrode | 111c |
| First drain electrode | 111d |
| First grid insulating barrier | 111e |
| Second channel layer | 112b |
| Second source electrode | 112c |
| Second drain electrode | 112d |
| Second grid insulating barrier | 112e |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Refer to Fig. 1, for the schematic diagram of the display floater that the specific embodiment of the invention provides. In the present embodiment, described display floater 100 is display panels. Described display floater 100 includes first substrate 110, second substrate 120 and is located in the liquid crystal layer 130 between described first substrate 110 and second substrate 120. Described first substrate 110 is thin-film transistor array base-plate 110, and described second substrate 120 is opposite substrate 120. Described first substrate 110 rotates with the liquid crystal molecule in liquid crystal layer 130 described in second substrate 120 co-controlling.
Refer to Fig. 2, for the top view of thin-film transistor array base-plate in Fig. 1 110. Described thin-film transistor array base-plate 110 includes multi-strip scanning line SL, a plurality of data lines DL, and described multi-strip scanning line SL and a plurality of data lines DL is mutually perpendicular to. Two adjacent scanning line SL and two adjacent data line DL minimum units defined define a pixel region P. The corresponding pixel of one pixel region P, each pixel includes pixel electrode 114. Described scanning line SL includes a scan line SLa and adjacent with this scan line and insulation setting the second scanning line SLb. Described data wire DL includes the first data wire DLa and the second data wire DLb. Described first data wire DLa and the second data wire DLb mutually insulated and overlap. Wherein, this is provided with for driving the first film transistor 111 and one second thin film transistor (TFT) 112 being positioned at this scan line SLa both sides pixel. This second scanning line SLb does not electrically connect with this first film transistor 111 and this second thin film transistor (TFT) 112. In the present embodiment, this scan line SLa and the second scanning line SLb defines one group of scanline groups, and the scanline groups organizing repeated arrangement constitute the scanning line SL of this thin-film transistor array base-plate 110 more. In the present embodiment, line SLb is as a redundant line in this second scanning, except for coordinating the black matrix (BLACKMATRIX, BM) on object substrate to prevent outside light leak, meanwhile, also can when broken string occurs in scan line SLa as the patch cord of this scan line SLa. Described the first film transistor 111 is electrically connected with described scan line SLa and the first data wire DLa. Described second thin film transistor (TFT) 112 is electrically connected with described scan line SLa and the second data wire DLb. In the present embodiment, this first film transistor 111 is arranged on this scan line SLa with this second thin film transistor (TFT) 112 stacking. In other embodiments, this second scanning line SLb can omit, to optimize the aperture opening ratio of this thin film transistor (TFT) array further.
See also Fig. 3, for the first embodiment sectional view of III-III line of cut along Fig. 2 of thin-film transistor array base-plate 110 of the present invention. Described thin-film transistor array base-plate 110 also includes substrate 113, first grid insulating barrier 111e and second grid insulating barrier 112e. Described the first film transistor 111 includes grid 111a, first passage layer 111b, the first source electrode 111c and the first drain electrode 111d. Described second thin film transistor (TFT) 112 includes described grid 111a, second channel layer 112b, the second source electrode 112c and the second drain electrode 112d. That is, described the first film transistor 111 shares described grid 111a with described second thin film transistor (TFT) 112. In the present embodiment, this grid 111a is a part of this scan line SLa. It is appreciated that this grid 111a is alternatively the branch being connected with this scan line SLa.
In the present embodiment, described the first film transistor 111 is bottom gate polar form thin film transistor (TFT), and described second thin film transistor (TFT) 112 is top grid film transistor. Specifically, described second source electrode 112c, the second drain electrode 112d and second channel layer 112b are formed in described substrate 113, and the two ends of described second channel layer 112b are respectively overlay on described second source electrode 112c and the second drain electrode 112d. Described second grid insulating barrier 112e covers described second source electrode 112c, the second drain electrode 112d and second channel layer 112b. Described grid 111a is formed on described second grid insulating barrier 112e, and corresponding with the position of described second channel layer 112b. Described first grid insulating barrier 111e is formed on described second grid insulating barrier 112e, and covers described grid 111a. Described first source electrode 111c, the first drain electrode 111d and first passage layer 111b are formed on described first grid insulating barrier 111e, the corresponding described grid 111a in the position of described first channel layer 111b, and described first source electrode 111c and the first 111d that drains is respectively overlay in described two ends relative for first passage layer 111b. It is appreciated that described thin-film transistor array base-plate 110 can also include the common structure of the thin-film transistor array base-plates such as channel layer protective layer, passivation layer, does not repeat them here.
The grid 111a and described scan line SLa of described the first film transistor 111 is electrically connected. First source electrode 111c of described the first film transistor 111 is electrically connected with described first data wire DLa. First drain electrode 111d and one's pixel electrode 114 of described the first film transistor 111 is electrically connected. The grid 111a and described scan line SLa of described second thin film transistor (TFT) 112 is electrically connected. Second source electrode 112c of described second thin film transistor (TFT) 112 is electrically connected with described second data wire DLb. Second drain electrode 112d of described second thin film transistor (TFT) 112 is electrically connected with another pixel electrode 114. Thus, described the first film transistor 111 can control with described first data wire DLa by described scan line SLa, and described second thin film transistor (TFT) 112 can control with described second data wire DLb by described scan line SLa.
Therefore, described scan line SLa can coordinate described first data wire DLa and described second data wire DLb to control the pixel region P of described scan line SLa both sides respectively, thereby reduce the quantity of the scan line SLa being connected to pixel electrode 114, thus promoting the aperture opening ratio of this display floater 100. Experiment proves that, display floater 100 provided by the present invention can promote at least 10% compared to traditional display floater aperture opening ratio.
See also Fig. 4, for the second embodiment sectional view of III-III line of cut along Fig. 2 of thin-film transistor array base-plate 110 of the present invention. In the present embodiment, described the first film transistor 111 is bottom gate polar form thin film transistor (TFT), and described second thin film transistor (TFT) 112 is top grid film transistor. Specifically, described second channel layer 112b is formed in described substrate 113. Described second source electrode 112c, the second drain electrode 112d are formed on described second channel layer 112b and are respectively overlay in the two ends of described second channel layer 112b. Described second grid insulating barrier 112e covers described second source electrode 112c, the second drain electrode 112d and second channel layer 112b. Described grid 111a is formed on described second grid insulating barrier 112e, and corresponding with the position that described second channel layer 112b is not covered by described second source electrode 112c and the second drain electrode 112d. Described first grid insulating barrier 111e is formed on described second grid insulating barrier 112e, and covers described grid 111a. Described first source electrode 111c, the first drain electrode 111d and first passage layer 111b are formed on described first grid insulating barrier 111e, and described first source electrode 111c and the first drain electrode 111d is respectively overlay in described two ends relative for first passage layer 111b. It is appreciated that described thin-film transistor array base-plate 110 can also include the common structure of the thin-film transistor array base-plates such as channel layer protective layer, passivation layer, does not repeat them here.
Refer to Fig. 5, for the flow chart of manufacture method of the first embodiment of thin-film transistor array base-plate 110 of the present invention. Described manufacture method comprises the steps:
Step S201, refers to Fig. 6 and Fig. 7, it is provided that substrate 113, and forms the second source electrode 112c, the second drain electrode 112d and the second data wire DLb electrically connected with this second source electrode 112c in described substrate 113. Specifically, described second source electrode 112c, the second drain electrode 112d and the second data wire DLb forming method be in substrate 113, first form a metal level, then by modes such as gold-tinted developments, this metal layer patterning is formed.
Step S202, refers to Fig. 8 and Fig. 9, forms second channel layer 112b in described second source electrode 112c, the second drain electrode 112d and substrate 113, and the two ends of described second channel layer 112b are covered each by described second source electrode 112c and the second drain electrode 112d. In the present embodiment, the material of described second channel layer 112b is preferably and aoxidizes quasiconductor. In other embodiments, the material of described second channel layer 112b is further selected from the semi-conducting material such as non-crystalline silicon, polysilicon.
Step S203, refers to Figure 10, forms the second grid insulating barrier 112e covering described second source electrode 112c, the second drain electrode 112d, the second data wire DLb, second channel layer 112b and substrate 113.
Step S204, refers to Figure 11 and Figure 12, forms grid 111a and electrically connect the scan line SLa of this grid 111a on described second grid insulating barrier 112e. Wherein, the corresponding described second channel layer 112b in the position of described grid 111a. First described grid 111a and scan line SLa forms a metal level on second grid insulating barrier 112e, then this metal layer patterning is formed by modes such as gold-tinted developments. Preferably, while forming described grid 111a and scan line SLa, patterning forms the second scanning line SLb in the lump.
Step S205, refers to Figure 13, forms the first grid insulating barrier 111e covering described grid 111a on described second grid insulating barrier 112e. It is appreciated that described second grid insulating barrier 112e also covers described scan line SLa and the second scanning line SLb.
Step S206, refers to Figure 14 and Figure 15, forms the corresponding described grid 111a in position of first passage layer 111b, described first channel layer 111b on described first grid insulating barrier 111e. In the present embodiment, the material of described first channel layer 111b is oxidation quasiconductor. In other embodiments, the material of described first channel layer 111b is further selected from the semi-conducting material such as non-crystalline silicon, polysilicon.
Step S207, refers to Figure 16 and Figure 17, forms the first source electrode 111c, the first drain electrode 111d and the first data wire DLa on described first grid insulating barrier 111e and first passage layer 111b. Wherein, described first source electrode 111c and the first drain electrode 111d is covered each by described two ends relative for first passage layer 111b. Described first data wire DLa electrically connects described source electrode 111c. First described first source electrode 111c, the first drain electrode 111d and the first data wire DLa form a metal level on first grid insulating barrier 111e and first passage layer 111b, then this metal layer patterning are formed by modes such as gold-tinted developments.
It is appreciated that after forming described first source electrode 111c, the first drain electrode 111d and the first data wire DLa, it is also possible to form the common manufacture method including the thin-film transistor array base-plates such as channel protective layer, passivation layer, pixel electrode, do not repeat them here.
Refer to Figure 18, for the flow chart of manufacture method of the second embodiment of thin-film transistor array base-plate 110 of the present invention. Described manufacture method comprises the steps:
Step S301, refers to Figure 19 and Figure 20, it is provided that substrate 113, and forms second channel layer 112b in described substrate 113. In the present embodiment, the material of described second channel layer 112b is oxidation quasiconductor. In other embodiments, the material of described second channel layer 112b is further selected from the semi-conducting material such as non-crystalline silicon, polysilicon.
Step S302, refers to Figure 21 and Figure 22, forms the second source electrode 112c, the second drain electrode 112d and the second data wire DLb electrically connected with this second source electrode 112c on described second channel layer 112b. Specifically, described second source electrode 112c and the second drain electrode 112d is respectively overlay in the two ends of described second channel layer 112b. The forming method of described second source electrode 112c and the second drain electrode 112d is first to form a metal level on second channel layer 112b, then this metal layer patterning is formed by modes such as gold-tinted developments.
Step S303, refers to Figure 23, forms the second grid insulating barrier 112e covering described second source electrode 112c, the second drain electrode 112d, the second data wire DLb, second channel layer 112b and substrate 113.
Step S304, refers to Figure 24 and Figure 25, forms grid 111a and electrically connect the scan line SLa of this grid 111a on described second grid insulating barrier 112e. Wherein, the corresponding described second channel layer 112b in the position of described grid 111a. Described grid 111a is first form a metal level on second grid insulating barrier 112e in scan line SLa, then this metal layer patterning is formed by modes such as gold-tinted developments. Preferably, while forming described grid 111a and scan line SLa, patterning forms the second scanning line SLb in the lump.
Step S305, refers to Figure 26, forms the first grid insulating barrier 111e covering described grid 111a on described second grid insulating barrier 112e. It is appreciated that described second grid insulating barrier 112e also covers described scan line SLa and the second scanning line SLb.
Step S306, refers to Figure 27 and Figure 28, forms the corresponding described grid 111a in position of first passage layer 111b, described first channel layer 111b on described first grid insulating barrier 111e. In the present embodiment, the material of described first channel layer 111b is oxidation quasiconductor. In other embodiments, the material of described first channel layer 111b is further selected from the semi-conducting material such as non-crystalline silicon, polysilicon.
Step S307, refers to Figure 29 and Figure 30, forms the first source electrode 111c, the first drain electrode 111d and the first data wire DLa on described first grid insulating barrier 111e and first passage layer 111b. Wherein, described first source electrode 111c and the first drain electrode 111d is covered each by described two ends relative for first passage layer 111b. Described first data wire DLa electrically connects described source electrode 111c. First described first source electrode 111c, the first drain electrode 111d and the first data wire DLa form a metal level on first grid insulating barrier 111e and first passage layer 111b, then this metal layer patterning are formed by modes such as gold-tinted developments.
It is appreciated that after forming described first source electrode 111c, the first drain electrode 111d and the first data wire DLa, it is also possible to form the common manufacture method including the thin-film transistor array base-plates such as channel protective layer, passivation layer, pixel electrode, do not repeat them here.
Above example is only in order to illustrate technical scheme and unrestricted, although the present invention being described in detail with reference to preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent replacement, without deviating from the spirit and scope of technical solution of the present invention.
Claims (15)
1. a thin-film transistor array base-plate, it includes multi-strip scanning line, the a plurality of data lines intersected with the insulation of described scanning line and multiple pixel, it is characterized in that: described scanning line includes scan line, described data wire includes mutually insulated and the first data wire overlapped and the second data wire, this thin-film transistor array base-plate farther includes for driving the first film transistor being positioned at this scan line side pixel and for driving the second thin film transistor (TFT) being positioned at this scan line opposite side pixel, scan line described in described the first film transistor AND gate and the first data wire are electrically connected, described second thin film transistor (TFT) is electrically connected with described scan line and the second data wire.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that: the second thin film transistor (TFT) stacking described in described the first film transistor AND gate is arranged.
3. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that: a grid shared by described the first film transistor AND gate the second thin film transistor (TFT).
4. thin-film transistor array base-plate as claimed in claim 3, it is characterized in that: described the first film transistor also includes first passage layer, first source electrode and the first drain electrode, described second thin film transistor (TFT) also includes second channel layer, second source electrode and the second drain electrode, described first source electrode and the first data wire are electrically connected, described second source electrode is electrically connected with described second data wire, described thin-film transistor array base-plate also includes substrate, first grid insulating barrier and second grid insulating barrier, described second source electrode, second drain electrode and second channel layer are formed on the substrate, the two ends of described second channel layer are respectively overlay in described second source electrode and the second drain electrode, described second grid insulating barrier covers described second source electrode, second drain electrode and second channel layer, described grid is formed on described second grid insulating barrier and corresponding with the position of described second channel layer, described first grid insulating barrier is formed on described second grid insulating barrier and covers described grid, described first source electrode, first drain electrode and first passage layer are formed on described first grid insulating barrier, the corresponding described grid in the position of described first channel layer, described first source electrode and the first drain electrode are respectively overlay in the two ends of described first passage layer.
5. thin-film transistor array base-plate as claimed in claim 3, it is characterized in that: described the first film transistor also includes first passage layer, first source electrode and the first drain electrode, described second thin film transistor (TFT) also includes second channel layer, second source electrode and the second drain electrode, described first source electrode and the first data wire are electrically connected, described second source electrode is electrically connected with described second data wire, described thin-film transistor array base-plate also includes substrate, first grid insulating barrier and second grid insulating barrier, described second channel layer is formed on the substrate, described second source electrode, second drain electrode is formed on described second channel layer and is respectively overlay in the two ends of described second channel layer, described second grid insulating barrier covers described second source electrode, second drain electrode and second channel layer, the formation of described grid is not corresponding by the position of described second source electrode and the second drain electrode covering on described second grid insulating barrier and with described second channel layer, described first grid insulating barrier is formed on described second grid insulating barrier and covers described grid, described first source electrode, first drain electrode and first passage layer are formed on described first grid insulating barrier, the corresponding described grid in the position of described first channel layer, described first source electrode and the first drain electrode are respectively overlay in the two ends of described first passage layer.
6. thin-film transistor array base-plate as claimed in claim 3, it is characterised in that: described grid is a part for this scan line.
7. thin-film transistor array base-plate as claimed in claim 3, it is characterized in that: this multi-strip scanning line farther includes adjacent with this scan line and insulation setting the second scanning line, this scan line and this second scanning this multi-strip scanning line of the alternately arranged composition of line, and the Minimum Area that defines of this adjacent with this scan line of this scan line the second scanning line and adjacent data wire is to should the region at pixel place.
8. a display floater, it includes the thin-film transistor array base-plate as described in claim 1-7 any one.
9. a manufacture method for thin-film transistor array base-plate, the method comprises the steps:
Substrate is provided, and forms the second source electrode, the second drain electrode on the substrate and be electrically connected the second data wire of this second source electrode;
Described second source electrode, the second drain electrode and substrate are formed two ends and is covered each by described second source electrode and the second channel layer of the second drain electrode;
Form the second grid insulating barrier covering described second source electrode, the second drain electrode, the second data wire, second channel layer and substrate;
Described second grid insulating barrier is formed the grid of corresponding described second channel layer and electrically connects the scan line of this grid;
Described second grid insulating barrier is formed the first grid insulating barrier covering described grid and scan line;
Described first grid insulating barrier is formed the first passage layer of corresponding described grid; And
Described first grid insulating barrier with first passage layer are formed and is respectively overlay in first source electrode at described first passage layer two ends, the first drain electrode and is electrically connected the first data wire of this first source electrode.
10. the manufacture method of thin-film transistor array base-plate as claimed in claim 9, it is characterised in that: described first data wire and the second data wire overlap.
11. a manufacture method for thin-film transistor array base-plate, the method comprises the steps:
Substrate is provided, and forms second channel layer on the substrate;
Described second channel layer is formed and is respectively overlay in second source electrode at described second channel layer two ends, the second drain electrode and electrically connects the second data wire of this second source electrode;
Form the second grid insulating barrier covering described second source electrode, the second drain electrode, the second data wire, second channel layer and substrate;
Not by the grid of described second source electrode and the second channel layer of the second drain electrode covering and the scan line electrically connecting this grid described in forming position correspondence on described second grid insulating barrier;
Described second grid insulating barrier is formed the first grid insulating barrier covering described grid and scan line;
The first passage layer of the corresponding described grid of forming position on described first grid insulating barrier; And
It is respectively overlay in first source electrode at described first passage layer two ends, the first drain electrode at described first grid insulating barrier with first passage layer is formed and electrically connects the first data wire of this first source electrode.
12. the manufacture method of thin-film transistor array base-plate as claimed in claim 11, it is characterised in that: described first data wire and the second data wire overlap.
13. a thin-film transistor structure, it includes the first film transistor AND gate the second thin film transistor (TFT) that stacking is arranged, and a grid shared by the second thin film transistor (TFT) described in described the first film transistor AND gate.
14. thin-film transistor structure as claimed in claim 13, it is characterized in that: described the first film transistor also includes first passage layer, first source electrode and the first drain electrode, described second thin film transistor (TFT) also includes second channel layer, second source electrode and the second drain electrode, described thin-film transistor structure also includes substrate, first grid insulating barrier and second grid insulating barrier, described second source electrode, second drain electrode and second channel layer are formed on the substrate, the two ends of described second channel layer are respectively overlay in described second source electrode and the second drain electrode, described second grid insulating barrier covers described second source electrode, second drain electrode and second channel layer, described grid is formed on described second grid insulating barrier and corresponding with the position of described second channel layer, described first grid insulating barrier is formed on described second grid insulating barrier and covers described grid, described first source electrode, first drain electrode and first passage layer are formed on described first grid insulating barrier, the corresponding described grid in the position of described first channel layer, described first source electrode and the first drain electrode are respectively overlay in the two ends of described first passage layer.
15. thin-film transistor structure as claimed in claim 13, it is characterized in that: described the first film transistor also includes first passage layer, first source electrode and the first drain electrode, described second thin film transistor (TFT) also includes second channel layer, second source electrode and the second drain electrode, described thin-film transistor structure also includes substrate, first grid insulating barrier and second grid insulating barrier, described second channel layer is formed on the substrate, described second source electrode, second drain electrode is formed on described second channel layer and is respectively overlay in the two ends of described second channel layer, described second grid insulating barrier covers described second source electrode, second drain electrode and second channel layer, the formation of described grid is not corresponding by the position of described second source electrode and the second drain electrode covering on described second grid insulating barrier and with described second channel layer, described first grid insulating barrier is formed on described second grid insulating barrier and covers described grid, described first source electrode, first drain electrode and first passage layer are formed on described first grid insulating barrier, the corresponding described grid in the position of described first channel layer, described first source electrode and the first drain electrode are respectively overlay in the two ends of described first passage layer.
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| CN110534577A (en) * | 2019-08-12 | 2019-12-03 | 福建华佳彩有限公司 | A kind of thin film transistor (TFT) and preparation method |
| CN110832394A (en) * | 2017-07-14 | 2020-02-21 | 夏普株式会社 | Liquid crystal panel and liquid crystal display device |
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| US20130214279A1 (en) * | 2010-04-30 | 2013-08-22 | Jun Nishimura | Circuit board and display device |
| CN102707524A (en) * | 2012-05-02 | 2012-10-03 | 京东方科技集团股份有限公司 | Array substrate, display device and driving method of display device |
| CN103217846A (en) * | 2013-04-23 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN110832394A (en) * | 2017-07-14 | 2020-02-21 | 夏普株式会社 | Liquid crystal panel and liquid crystal display device |
| CN110832394B (en) * | 2017-07-14 | 2022-04-29 | 夏普株式会社 | Liquid crystal panel and liquid crystal display device |
| CN110534577A (en) * | 2019-08-12 | 2019-12-03 | 福建华佳彩有限公司 | A kind of thin film transistor (TFT) and preparation method |
| CN110534577B (en) * | 2019-08-12 | 2024-02-23 | 福建华佳彩有限公司 | Thin film transistor and preparation method thereof |
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| CN105633057B (en) | 2019-02-26 |
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