CN105633034A - 半导体晶圆凸点结构 - Google Patents
半导体晶圆凸点结构 Download PDFInfo
- Publication number
- CN105633034A CN105633034A CN201511000180.4A CN201511000180A CN105633034A CN 105633034 A CN105633034 A CN 105633034A CN 201511000180 A CN201511000180 A CN 201511000180A CN 105633034 A CN105633034 A CN 105633034A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- layer
- wafer
- reproduces
- reproduce
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002161 passivation Methods 0.000 claims abstract description 80
- 239000002861 polymer material Substances 0.000 claims abstract description 38
- 239000013078 crystal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 13
- 238000013316 zoning Methods 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920002577 polybenzoxazole Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 19
- 238000012360 testing method Methods 0.000 abstract description 8
- 238000005520 cutting process Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 abstract 3
- 239000012790 adhesive layer Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 230000001172 regenerating effect Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000178 monomer Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004026 adhesive bonding Methods 0.000 description 3
- 230000005260 alpha ray Effects 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229960001866 silicon dioxide Drugs 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供了一种半导体晶圆凸点结构,其包括:晶圆;形成于晶圆上表面的再造钝化层;形成于晶圆下表面的聚合物材料层;形成于聚合物材料层的各裸露面上的背胶层。与现有技术相比,本发明提供的半导体晶圆凸点结构的形成方法,能够削弱晶圆翘曲,从而有利于切割前的测试、打印、植球等工序的制造。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体晶圆凸点结构。
背景技术
近年来,半导体器件在成本降低和前道晶圆制造工艺的提升的共同促进下,实现了同样功能的半导体器件的单体芯片尺寸越来越小的目标,可以直接在半导体晶圆上形成直接可以应用在印刷电路板上安装的球状凸点。由于半导体晶圆制造工艺局限性或者设计者出于同一款集成电路多种用途的考虑,在半导体晶圆级封装时需要对传输电信号的输入端子重新定义位置形成球状凸点,这就需要金属再布线结构。然而,在半导体晶圆凸点结构在再布线金属层厚度超过10um时,在封装过程中容易形成翘曲,翘曲度在2mm以上,甚至能够达到4mm,无法实现半导体晶圆级封装制造的大生产需求;同时,在后续的恶化试验时容易形成再造钝化层底部与再布线金属层顶部之间的分层,这种产品容易造成后续的电性能失效;另外,对于高速专用半导体器件而言,这种封装结构虽然在结构上满足了倒装芯片封装结构的要求,但是没有在最大程度上避免金属焊料中α射线对半导体芯片内电路的影响导致的半导体器件失效。
发明内容
鉴于现有技术中的上述缺陷或不足,本发明提供一种半导体晶圆凸点结构。
本发明提供了一种半导体晶圆凸点结构,包括:
晶圆;
形成于晶圆上表面的再造钝化层;
形成于晶圆下表面的聚合物材料层;
形成于聚合物材料层的各裸露面上的背胶层。
与现有技术相比,本发明提供的半导体晶圆凸点结构,通过在晶圆的下表面形成聚合物材料层,在封装的过程中,由于聚合物材料层热膨胀也会产生应力,能够抵消全部或者大部分再造钝化层热膨胀产生的应力,削弱了应力释放造成的晶圆翘曲,翘曲度仅为0.4~1mm,从而有利于切割前的测试、打印、植球等工序的制造,在测试时再造钝化层底部与再布线金属层顶部之间不会分层,从而避免了电性能失效;另外,对于高速专用半导体器件而言,这种封装结构不仅在结构上满足了倒装芯片封装结构的要求,而且在最大程度上避免金属焊料中α射线对半导体芯片内电路的影响导致的半导体器件失效。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明提供的半导体晶圆凸点结构的一种实施例的截面结构示意图;
图2-图9为本发明提供的半导体晶圆凸点结构的形成方法的一种实施例的工艺示意图。
图中标记示意为:101、101X-晶圆;102-电极;103-钝化层;104-第一开口部;310b-第一间隙;610-胶层;110-第一再造钝化层;210-再布线金属层;310-第二再造钝化层;710-聚合物材料层;710a-第三开口部;310a-第二开口部;710b-第二间隙;410-凸点下金属层;510-球形凸点;810、810a、810b-背胶层;700-晶圆级封装的单体。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释相关发明,而非对该发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与发明相关的部分。
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
参照图1,本发明实施例的半导体晶圆凸点结构包括:
晶圆101X;
形成于晶圆101X上表面的再造钝化层;
形成于晶圆101X下表面的聚合物材料层710;
形成于聚合物材料层710的各裸露面上的背胶层810。
本实施例中,进一步地,所述晶圆101X上表面具有电极102及钝化层103,所述钝化层103具有裸露所述电极102的第一开口部104;
所述再造钝化层包括第一再造钝化层110和第二再造钝化层310;
所述第一再造钝化层110形成于所述钝化层103上;
在所述第一再造钝化层110上形成有再布线金属层210;
所述第二再造钝化层310,形成于所述再布线金属层210的各裸露面上,所述第二再造钝化层310上具有第二开口部310a;
所述第二开口部310a中形成有凸点下金属层410;
所述凸点下金属层410上形成有球形凸点510。
进一步地,所述聚合物材料层的厚度为第一再造钝化层与第二再造钝化层厚度之和,并且第一再造钝化层与第二再造钝化层热膨胀系数差值小于5具体实施时热膨胀系数最好相同,以便在封装的过程中,聚合物材料层710热膨胀与第一再造钝化层110和第二再造钝化层310热膨胀释放相同或基本相当的应力,更大程度上削弱应力释放造成的晶圆翘曲。
作为一种可选的实施方案,所述第一再造钝化层110与第二再造钝化层310的主要材质均与聚合物材料层710主要材质相同,以便三者具有相同的热膨胀系数,具体实施中,第一再造钝化层110、第二再造钝化层310、聚合物材料层710材质可以均为
聚酰亚胺或均为聚苯并恶唑。
可选的,所述聚合物材料层710上具有与所述第二开口部310a位置对应的第三开口部710a,并且所述第二开口部310a与第三开口部710a形状相同,所述形状相同为形状基本相同,具有为第二开口部310a深度与第二再造钝化层310厚度相同,第三开口部710a深度与聚合物材料层710深度相同,此处的形状基本相同指纵截面形状及尺寸是基本相同,第二开口部310a的侧面优选为斜面,而第三开口部710a的侧面可为斜面,可为与晶圆101X垂直的面,由于第一再造钝化层110厚度薄于聚合物材料层710厚度,所以第二开口部310a与第三开口部710a深度并不相同,形成第三开口部710a的目的主要是使聚合物材料层710与第二钝化层310形状比较一致,以便在封装过程中产生相当的应力释放,更大程度地削弱应力释放造成的晶圆翘曲。并且在所述第三开口部710a中也形成有背胶层810。
可选的,所述晶圆101具有多个分区单元,晶圆101上各分区单元之间具有不形成钝化层103的第一间隙310b,优选在所述第一间隙310b中形成有胶层610,以便对晶圆101进行更好的密封,所述胶层材质优选为氮化硅。
与晶圆101上各分区单元之间具有不形成钝化层103的第一间隙310b位置相对应,在聚合物材料层710上形成形状相同的第二间隙710b,以使聚合物材料层710形状与第二钝化层310形状更加一致,能够进一步削弱应力释放造成的晶圆翘曲,此处的形状相同也是指纵截面形状相同,深度并不相同。
作为一种可选的实施方式,所述晶圆的厚度为380~750μm。
应该理解,所述第一再造钝化层、第二再造钝化层及聚合材料层材质均为聚酰亚胺或均为聚苯并恶唑。
在本实施例中,可选的,所述背胶层厚度为15~45μm。
可选的,所述第一再造钝化层厚度为4~6μm,所述第二再造钝化层厚度为7~15μm。
可选的,所述再布线金属层厚度为3~11μm,材质为铜或铝。
进一步,参见2-9,结合本发明的半导体晶圆凸点结构的实施例的具体的形成方法对本发明的半导体晶圆凸点结构进行进一步地介绍。
参照图2-9,本发明公开了一种半导体晶圆凸点结构的形成方法,包括:
S10、提供上表面具有电极及钝化层的晶圆,所述钝化层具有裸露所述电极的第一开口部;
S20、在所述钝化层上形成第一再造钝化层;
S30、在所述第一再造钝化层上形成再布线金属层;
S40、在所述再布线金属层的各裸露面形成第二再造钝化层,所述第二再造钝化层上具有第二开口部;
S50、在晶圆的下表面形成聚合物材料层;
S60、在所述第二开口部中形成凸点下金属层,并在凸点下金属层上形成球形凸点;
S70、在聚合物材料层的各裸露面上及第三开口部中形成背胶层;
S80、切割后形成晶圆级封装的单体。
首先进行步骤S10,参见图2,提供上表面具有电极102及钝化层103的晶圆101,所述钝化层103具有裸露所述电极102的第一开口部104。
然后进行步骤S20、参见图3,在所述钝化层103上形成第一再造钝化层110;优选通过涂胶、曝光、显影和固化的方法在所述钝化层103上形成第一再造钝化层110。
进行步骤S30、参见图4,在所述第一再造钝化层110上形成再布线金属层210。
在一种可选的实施方式中,在步骤S30后接着进行步骤S35:从晶圆110下表面对晶圆110的厚度进行减薄,减薄优选采用打磨的方式,打磨后的晶圆101X结构参见图5。
在一种可选的实施方式中,从晶圆101的下表面对晶圆101的厚度进行减薄后,晶圆101X的厚度为150~380μm。
进行步骤S40、参见图6,在所述再布线金属层210的各裸露面形成第二再造钝化层310,所述第二再造钝化层310上具有第二开口部310a。优选通过涂胶、曝光、显影和固化的方法在再布线金属层210的各裸露面形成第二再造钝化层310。
接着进行步骤S50、继续参见图6,在晶圆101的下表面形成聚合物材料层710。
作为一种可选的实施方案,通过涂胶、曝光、显影和固化的方法在在晶圆101的下表面形成聚合物材料层710。
在一种可选的实施方式中,在晶圆101的下表面形成聚合物材料层710后,还包括对聚合物材料层710进行打磨减薄的步骤,以便获得更加平整并且厚度合适的聚合物材料层710,使聚合物材料层710的形成更加方便。
然后再进行步骤S60、在所述第二开口部310a中形成凸点下金属层410,参见图7,并在凸点下金属层410上形成球形凸点510,参见图8。进一步的,球形凸点510优选为锡球。
在一种可选的实施方式中,通过溅射、光刻、电镀或腐蚀的方法形成凸点下金属层410。
作为一种可选的实施方式,通过植球回流的方法形成球形凸点510。
进行步骤S70、参见图9,在聚合物材料层710的各裸露面上及第三开口部710a中形成背胶层810,背胶层810包括两部分,一部分为聚合物材料层710的各裸露面上的背胶层810b,一部分为第三开口部710a中的背胶层810a。
可选的,所述背胶层810材质为环氧树脂、丙烯酸树脂、二氧化硅、炭黑及溶剂的混合物,当然也可以为其它能形成胶层的材质。
最后进行步骤S80、切割后形成晶圆级封装的单体。
在一种可选的实施方式中,在步骤S80“在聚合物材料层710的各裸露面上及第三开口部710a中形成背胶层810”及步骤S90“切割后形成晶圆级封装的单体”之间还包括测试及打印的步骤。所述测试及打印均采用常规的测试及打印技术,因此不再赘述。
与现有技术相比,本发明提供的半导体晶圆凸点结构的形成方法,通过在晶圆的下表面形成有聚合物材料层,在封装的过程中,由于聚合物材料层热膨胀也会产生应力,能够抵消全部或者大部分再造钝化层热膨胀产生的应力,削弱了应力释放造成的晶圆翘曲,从而有利于切割前的测试、打印、植球等工序的制造,在测试时再造钝化层底部与再布线金属层顶部之间不会分层,从而避免了电性能失效;另外,对于高速专用半导体器件而言,这种封装结构不仅在结构上满足了倒装芯片封装结构的要求,而且在最大程度上避免金属焊料中α射线对半导体芯片内电路的影响导致的半导体器件失效。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解,本申请中所涉及的发明范围,并不限于上述技术特征的特定组合而成的技术方案,同时也应涵盖在不脱离所述发明构思的情况下,由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
Claims (10)
1.一种半导体晶圆凸点结构,其特征在于,包括:
晶圆;
形成于晶圆上表面的再造钝化层;
形成于晶圆下表面的聚合物材料层;
形成于聚合物材料层的各裸露面上的背胶层。
2.根据权利要求1所述的半导体晶圆凸点结构,其特征在于,
所述晶圆上表面具有电极及钝化层,所述钝化层具有裸露所述电极的第一开口部;
所述再造钝化层包括第一再造钝化层和第二再造钝化层;
所述第一再造钝化层形成于所述钝化层上;
在所述第一再造钝化层上形成有再布线金属层;
所述第二再造钝化层,形成于所述再布线金属层的各裸露面上,所述第二再造钝化层上具有第二开口部;
所述第二开口部中形成有凸点下金属层;
所述凸点下金属层上形成有球形凸点。
3.根据权利要求2所述的半导体晶圆凸点结构,其特征在于,所述聚合物材料层的厚度为第一再造钝化层与第二再造钝化层厚度之和,并且第一再造钝化层与第二再造钝化层热膨胀系数差值小于5。
4.根据权利要求3所述的半导体晶圆凸点结构,其特征在于,所述第一再造钝化层及第二再造钝化层主要材质均与聚合物材料层主要材质相同。
5.根据权利要求2-3任一项所述的半导体晶圆凸点结构,其特征在于,所述聚合物材料层上具有与所述第二开口部位置对应的第三开口部,所述第二开口部与第三开口部形状相同,并且在所述第三开口部中也形成有背胶层。
6.根据权利要求2-3任一项所述的导体晶圆凸点结构,其特征在于,所述晶圆上具有多个分区单元,晶圆上各分区单元之间具有不形成钝化层的第一间隙。
7.根据权利要求6所述的半导体晶圆凸点结构,其特征在于,与第一间隙位置相对应,在聚合物材料层上形成形状相同的第二间隙。
8.根据权利要求4所述的半导体晶圆凸点结构,其特征在于,所述第一再造钝化层、第二再造钝化层及聚合材料层材质均为聚酰亚胺或均为聚苯并恶唑。
9.根据权利要求1-3任一项所述的半导体晶圆凸点结构,其特征在于,所述背胶层厚度为15~45μm。
10.根据权利要求2所述的半导体晶圆凸点结构,其特征在于,所述第一再造钝化层厚度为4~6μm,所述第二再造钝化层厚度为7~15μm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201511000180.4A CN105633034B (zh) | 2015-12-25 | 2015-12-25 | 半导体晶圆凸点结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201511000180.4A CN105633034B (zh) | 2015-12-25 | 2015-12-25 | 半导体晶圆凸点结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105633034A true CN105633034A (zh) | 2016-06-01 |
CN105633034B CN105633034B (zh) | 2018-03-27 |
Family
ID=56047812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201511000180.4A Active CN105633034B (zh) | 2015-12-25 | 2015-12-25 | 半导体晶圆凸点结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105633034B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113097168A (zh) * | 2021-03-26 | 2021-07-09 | 武汉新芯集成电路制造有限公司 | 半导体装置及其形成方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7439170B1 (en) * | 2008-03-07 | 2008-10-21 | International Business Machines Corporation | Design structure for final via designs for chip stress reduction |
CN102099909A (zh) * | 2008-07-16 | 2011-06-15 | 皇家飞利浦电子股份有限公司 | 半导体器件以及制造方法 |
US20110241222A1 (en) * | 2010-03-31 | 2011-10-06 | Recai Sezi | Semiconductor Package and Manufacturing Method |
US20130175705A1 (en) * | 2012-01-11 | 2013-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress Compensation Layer for 3D Packaging |
CN204391088U (zh) * | 2014-12-11 | 2015-06-10 | 南通富士通微电子股份有限公司 | 散热式全包封半导体芯片 |
US9385102B2 (en) * | 2012-09-28 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
-
2015
- 2015-12-25 CN CN201511000180.4A patent/CN105633034B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7439170B1 (en) * | 2008-03-07 | 2008-10-21 | International Business Machines Corporation | Design structure for final via designs for chip stress reduction |
CN102099909A (zh) * | 2008-07-16 | 2011-06-15 | 皇家飞利浦电子股份有限公司 | 半导体器件以及制造方法 |
US20110241222A1 (en) * | 2010-03-31 | 2011-10-06 | Recai Sezi | Semiconductor Package and Manufacturing Method |
US20130175705A1 (en) * | 2012-01-11 | 2013-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress Compensation Layer for 3D Packaging |
US9385102B2 (en) * | 2012-09-28 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
CN204391088U (zh) * | 2014-12-11 | 2015-06-10 | 南通富士通微电子股份有限公司 | 散热式全包封半导体芯片 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113097168A (zh) * | 2021-03-26 | 2021-07-09 | 武汉新芯集成电路制造有限公司 | 半导体装置及其形成方法 |
WO2022198785A1 (zh) * | 2021-03-26 | 2022-09-29 | 武汉新芯集成电路制造有限公司 | 半导体装置及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN105633034B (zh) | 2018-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102208409B (zh) | 集成电路结构 | |
KR100511728B1 (ko) | 복수의 반도체 칩을 고밀도로 실장할 수 있는 소형 반도체장치 및 그의 제조 방법 | |
US7148560B2 (en) | IC chip package structure and underfill process | |
US8785317B2 (en) | Wafer level packaging of semiconductor chips | |
TWI236721B (en) | Leadframe for leadless flip-chip package and method for manufacturing the same | |
US8729700B2 (en) | Multi-direction design for bump pad structures | |
TW200713549A (en) | Semiconductor element with conductive bumps and fabrication method thereof | |
CN105280599A (zh) | 用于半导体器件的接触焊盘 | |
KR101605600B1 (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
GB2438788B (en) | Structure and method for fabricating flip chip devices | |
CN104037133B (zh) | 一种圆片级芯片扇出封装方法及其封装结构 | |
MY151533A (en) | Substrate and process for semiconductor flip chip package | |
CN104716103A (zh) | 具有间隙的底部填充图案 | |
CN103050473A (zh) | 具有可再造底部填充物的晶圆级芯片尺寸封装件 | |
CN104851816A (zh) | 一种多芯片高密度封装方法 | |
DE102013109095A1 (de) | Halbleitergehäusevorrichtung mit passiven energiebauteilen | |
US20100155937A1 (en) | Wafer structure with conductive bumps and fabrication method thereof | |
CN105489564B (zh) | 电子单体及其制法 | |
CN105633034A (zh) | 半导体晶圆凸点结构 | |
US7170167B2 (en) | Method for manufacturing wafer level chip scale package structure | |
CN105633033A (zh) | 半导体晶圆凸点结构的形成方法 | |
TWI352411B (en) | Thinning method for fabricating dies arrangement p | |
CN105023882A (zh) | 半导体中介板及封装结构 | |
CN105304507A (zh) | 扇出晶圆级封装方法 | |
US9190370B2 (en) | Semiconductor device utilizing redistribution layers to couple stacked die |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
COR | Change of bibliographic data | ||
GR01 | Patent grant | ||
GR01 | Patent grant |