CN105632918A - Method for removing native oxide layer of FinFet device before source-drain epitaxy - Google Patents
Method for removing native oxide layer of FinFet device before source-drain epitaxy Download PDFInfo
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- CN105632918A CN105632918A CN201410601934.0A CN201410601934A CN105632918A CN 105632918 A CN105632918 A CN 105632918A CN 201410601934 A CN201410601934 A CN 201410601934A CN 105632918 A CN105632918 A CN 105632918A
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- 238000000034 method Methods 0.000 title abstract description 30
- 238000000407 epitaxy Methods 0.000 title abstract description 8
- 230000007797 corrosion Effects 0.000 claims abstract description 13
- 238000005260 corrosion Methods 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims description 26
- 238000005516 engineering process Methods 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 239000003085 diluting agent Substances 0.000 claims description 7
- 230000003197 catalytic effect Effects 0.000 claims description 5
- 229910052756 noble gas Inorganic materials 0.000 claims description 4
- 238000010926 purge Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 abstract description 21
- 235000001674 Agaricus brunnescens Nutrition 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910004156 TaNx Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000010186 staining Methods 0.000 description 2
- 229910001868 water Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910019897 RuOx Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 235000003642 hunger Nutrition 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000037351 starvation Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
The invention provides a method for removing a natural oxide layer of a FinFet device before source-drain epitaxy, which comprises the following steps: RCA cleaning is carried out; and removing the native oxide layer by anhydrous HF gas phase corrosion. The method has better process controllability, can better interrupt the contact between oxygen and the surface of the wafer, effectively remove the natural oxide layer, simultaneously reduce the loss of dielectric layers in other areas, and avoid the generation of mushroom defects in the subsequent selective epitaxy process.
Description
Technical field
The present invention relates to field of semiconductor device preparation, particularly to the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension.
Background technology
Fin-FET is the transistor with fin channel structure, and it utilizes several surfaces of thin fin as raceway groove, such that it is able to prevent the short-channel effect in conventional transistor, can increase operating current simultaneously.
At present, in the device fabrication of FinFet, in order to increase the mobility of carrier to meet the requirement of device speed, in the source and drain areas of NMOS and PMOS transistor, generally introduce different materials, so that pressure is introduced raceway groove. Common practice is, for PMOS device, the source and drain areas Epitaxial growth at fin goes out the stressor layers of SiGe, and owing to SiGe lattice paprmeter is more than Si, therefore channel region can be applied pressure by this stressor layers; For nmos device, the source and drain areas Epitaxial growth at fin goes out the stressor layers of Si:C, and owing to the lattice paprmeter of Si:C is less than Si, therefore channel region is provided tension force by this stressor layers.
Epitaxy technique is the method growing the strain gauge materials such as SiGe, Ge, SiC, GeSn on semi-conducting material. In the source-drain area epitaxy technique of FinFet, it is selective epitaxial stress thin film on the source and drain areas of fin, before carrying out extension, it is necessary to the natural oxidizing layer of epi region (the Si region of exposure) is removed.
At present, before the source-drain area epitaxy technique of FinFet, HF-last is adopted to process technique, namely, before entering epitaxial reaction chamber room, silicon chip is positioned in the HF dilute solution of certain proportioning, erosion removal natural oxidizing layer, then with deionized water rinsing and dry, and quickly put into reaction chamber and carry out epitaxy technique.
But, remove in the technique of natural oxidizing layer, with reference to shown in Fig. 1 and Fig. 3, the region being exposed to has: the SiO of the high spreadability of 3-D solid structure2Material side wall (spacer) 110, the SiO that top portions of gates plasma enhancing (PE) deposits2Mask layer 109 (Fig. 1 is not shown), the shallow-trench isolation silicon oxide (STISiO of high compactness2) isolation 104 and the source-drain area at SiFin102 two ends. Process in technique at HF-last, usually by controlling etch period, thoroughly remove natural oxidizing layer, if but problematically, rinsing time is long, the loss that can make side wall 110 and mask layer 109 is too much, false grid grid 108 is exposed, selective epitaxial process can form the defect of " mushroom (mushroom) " 109, with reference to, shown in Fig. 3, source and drain being connected the inefficacy in turn resulting in device.
Summary of the invention
In view of this, the invention provides the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension, effectively remove natural oxidizing layer, reduce defect and produce.
The minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension, including step:
Carry out RCA cleaning;
In the way of anhydrous HF gaseous corrosion, carry out the removal of natural oxidizing layer.
Optionally, after carrying out the removal of natural oxidizing layer, further comprise the steps of: with high-purity H2Or N2Or noble gas carries out the purging of wafer and dries.
Optionally, being also mixed with diluent gas and catalytic gas in anhydrous HF gas, shared by anhydrous HF gas, the ratio of total gas flow rate is less than 20%.
Optionally, during anhydrous HF gaseous corrosion, the temperature of reaction chamber is 35-65 DEG C.
Optionally, during anhydrous HF gaseous corrosion, the pressure of reaction chamber is 5-150Torr.
Optionally, diluent gas includes H2Or N2��
Optionally, the step carrying out RCA cleaning includes: carry out the cleaning of SPM and SC2.
The minimizing technology of natural oxidizing layer before FinFet device source and drain extension provided by the invention, adopt the mode of anhydrous HF gaseous corrosion, carry out the removal of natural oxidizing layer, compare wet etching, the method has a better technology controlling and process, and can better break off contacting of oxygen and wafer surface, effectively removes while natural oxidizing layer, reduce the loss of other Region Medium layer, it is to avoid the generation of " mushroom " defect in subsequent selective epitaxial process.
Accompanying drawing explanation
Fig. 1 is the structural representation before the source and drain extension of FinFet device;
Fig. 2 is the structural representation delayed outside the source and drain of FinFet device;
Fig. 3 is the schematic cross-section of the FinFet device producing " mushroom " defect in prior art;
Fig. 4 be the FinFet device according to the present invention source and drain extension before the flow chart of minimizing technology of natural oxidizing layer.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of invention, feature and advantage to become apparent from, below the specific embodiment of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment.
Providing the minimizing technology of natural oxidizing layer before a kind of FinFet device source and drain extension in the present invention, namely before needs carry out source and drain epitaxy technique, remove the natural oxidizing layer on the surface of the fin exposed, common, in this step, device includes: fin; Isolation between fin; Grid on fin; Side wall on gate lateral wall; And, the mask layer at the top of fin. Now, the two ends of fin are the formation region of source and drain, in subsequent steps, it is necessary to carry out selective epitaxial at this source and drain areas, to strengthen the stress effect of raceway groove, before this, it is necessary to got rid of by the natural oxidizing layer of source and drain areas silicon face.
In order to be better understood from technical scheme and technique effect, it is described in detail below with reference to flow chart 1 and specific embodiment.
Before carrying out the removal of natural oxidizing layer, first, it is provided that FinFet device architecture, with reference to shown in Fig. 1.
In the present embodiment, as shown in Figure 1, concrete, first, substrate 100 is provided, substrate 100 can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc. In other embodiments, described Semiconductor substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., other epitaxial structures all right, for instance SGOI (silicon germanium on insulator) etc. In the present embodiment, substrate 100 is body silicon substrate.
Then, lithographic technique is adopted, for instance the method for RIE (reactive ion etching), etched substrate 100 forms fin 102.
Then, being filled with the isolated material of silicon dioxide, and carry out flatening process, it is possible to use wet etching, use the certain thickness isolated material of Fluohydric acid. erosion removal, the isolated material of member-retaining portion is between fin 102, thus defining isolation 104.
Then, deposit gate dielectric material and grid material respectively, gate dielectric material can be thermal oxide layer or high K medium material, high K medium material such as hafnio oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., grid material can include metal gates or polysilicon, for instance may include that Ti, TiAlx��TiN��TaNx��HfN��TiCx��TaCx��HfCx��Ru��TaNx��TiAlN��WCN��MoAlN��RuOx, polysilicon or other suitable materials, or their combination. Then, deposit mask layer (not shown go out), such as the mask layer of the silicon dioxide of plasma enhancing (PE), and perform etching, be formed across gate dielectric layer 106 and the grid 108 of fin 102. Finally, it is possible to by silicon oxide deposition, then carry out RIE (reactive ion etching) and form side wall 110.
So, the device architecture before FinFet device source and drain extension it is the formation of.
Then, it is possible to carry out the removal of natural oxidizing layer before FinFet device source and drain extension.
First, in step S01, carry out RCA cleaning.
In this step, carry out RCA cleaning, to remove staining of wafer surface. In the present embodiment, first carry out SPM (H2SO4/H2O2/H2O) clean, to remove staining of wafer surface carbon containing, such as organic residue etc. Then, SC2 (HCl/H is carried out2O2/H2O) cleaning, to remove the metallic of wafer surface trace, and it is dry to carry out drying.
Then, in step S02, in the way of anhydrous HF gaseous corrosion, carry out the removal of natural oxidizing layer.
In the present embodiment, being mixed with diluent gas and catalytic gas in anhydrous HF (vHF), diluent gas is N such as2Or H2Deng noble gas, the alcohols gas such as catalytic gas such as methanol (MeOH) or ethanol, wherein, shared by anhydrous HF gas, the ratio of total gas flow rate is less than 20%. The temperature of reaction chamber is 35-65 DEG C, and the pressure of reaction chamber is 5-150Torr.
In a preferred embodiment, the ratio of total gas flow rate shared by anhydrous HF gas is 15%, and the temperature of reaction chamber is 50 DEG C, and the pressure of reaction chamber is 50Torr, under these process conditions, to the corrosion rate of native oxide layer about 15-30 angstrom min.
Method has better technology controlling and process, by mixing gas and catalytic gas and the process conditions such as temperature, pressure, it is easy to the eliminating of the speed of control corrosion rate and the time of corrosion and byproduct of reaction, additionally, N2Or H2Diluent gas can better by the isolation of oxygen and wafer, it is to avoid reoxidation.
After carrying out vHF gaseous corrosion, it is also possible to carry out the purging of wafer with noble gas, for instance with H high-purity in a large number2Or N2, the inert gas purge wafer surface such as Ar, with starvation, play suppression native oxide layer and again generate. High-purity gas refers to that in gas, oxygen content is less than 1ppb herein.
Then, it is possible to carry out source and drain epitaxial growth, form the epitaxial layer 112 of source-drain area, with reference to shown in Fig. 2.
In one embodiment, it is possible to carry out the selective epitaxial growth of SiGe or Si:C, grow epitaxial layer with the source and drain areas at the two ends at fin, to strengthen the stress effect of raceway groove, improve the carrier mobility of device.
The minimizing technology of the natural oxidizing layer of the present invention, effectively removes the natural oxidizing layer of fin source and drain areas silicon face in the short period of time, decrease the loss of the media such as other zone oxidation silicon, efficiently avoid the generation of mushroom in source-drain area selective epitaxial growth process process, it is to avoid the inefficacy of device.
Although the present invention is described in conjunction with above example, but the present invention is not limited to above-described embodiment, and it being only limited by the restriction of claims, it easily can be modified and change by those of ordinary skill in the art, but and without departing from the essential idea of the present invention and scope.
Claims (7)
1. the minimizing technology of natural oxidizing layer before a FinFet device source and drain extension, it is characterised in that include step:
Carry out RCA cleaning;
In the way of anhydrous HF gaseous corrosion, carry out the removal of natural oxidizing layer.
2. minimizing technology according to claim 1, it is characterised in that after carrying out the removal of natural oxidizing layer, further comprises the steps of: with high-purity H2��N2Or noble gas carries out the purging of wafer and dries.
3. minimizing technology according to claim 1, it is characterised in that being also mixed with diluent gas and catalytic gas in anhydrous HF gas, shared by anhydrous HF gas, the ratio of total gas flow rate is less than 20%.
4. minimizing technology according to claim 3, it is characterised in that during anhydrous HF gaseous corrosion, the temperature of reaction chamber is 35-65 DEG C.
5. minimizing technology according to claim 4, it is characterised in that during anhydrous HF gaseous corrosion, the pressure of reaction chamber is 5-150Torr.
6. minimizing technology according to claim 3, it is characterised in that diluent gas includes H2Or N2��
7. minimizing technology according to claim 1, it is characterised in that the step carrying out RCA cleaning includes: carry out the cleaning of SPM and SC2.
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| CN201410601934.0A CN105632918A (en) | 2014-10-30 | 2014-10-30 | Method for removing native oxide layer of FinFet device before source-drain epitaxy |
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| CN201410601934.0A CN105632918A (en) | 2014-10-30 | 2014-10-30 | Method for removing native oxide layer of FinFet device before source-drain epitaxy |
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|---|---|---|---|---|
| CN101068002A (en) * | 2006-05-04 | 2007-11-07 | 硅电子股份公司 | Method for preparing polished semiconductor |
| CN101183684A (en) * | 2006-11-17 | 2008-05-21 | 国际商业机器公司 | Semiconductor structure and method for fabrication thereof |
| CN101191252A (en) * | 2006-11-20 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
| CN101276746A (en) * | 2007-03-28 | 2008-10-01 | 株式会社东芝 | Surface treatment method, etching treatment method and manufacturint method of electronic apparatus |
| CN102637586A (en) * | 2011-02-12 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
| CN103328688A (en) * | 2011-01-24 | 2013-09-25 | 梅姆斯塔有限公司 | Vapour etch of silicon dioxide with improved selectivity |
-
2014
- 2014-10-30 CN CN201410601934.0A patent/CN105632918A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101068002A (en) * | 2006-05-04 | 2007-11-07 | 硅电子股份公司 | Method for preparing polished semiconductor |
| CN101183684A (en) * | 2006-11-17 | 2008-05-21 | 国际商业机器公司 | Semiconductor structure and method for fabrication thereof |
| CN101191252A (en) * | 2006-11-20 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
| CN101276746A (en) * | 2007-03-28 | 2008-10-01 | 株式会社东芝 | Surface treatment method, etching treatment method and manufacturint method of electronic apparatus |
| CN103328688A (en) * | 2011-01-24 | 2013-09-25 | 梅姆斯塔有限公司 | Vapour etch of silicon dioxide with improved selectivity |
| CN102637586A (en) * | 2011-02-12 | 2012-08-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
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