CN101191252A - Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth - Google Patents
Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth Download PDFInfo
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- CN101191252A CN101191252A CNA2006101184968A CN200610118496A CN101191252A CN 101191252 A CN101191252 A CN 101191252A CN A2006101184968 A CNA2006101184968 A CN A2006101184968A CN 200610118496 A CN200610118496 A CN 200610118496A CN 101191252 A CN101191252 A CN 101191252A
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- oxidizing layer
- natural oxidizing
- silicon chip
- gas
- epitaxy growth
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Abstract
The invention discloses a method for removing natural oxidizing layer before low temperature epitaxial growth of silicon slice; the method of the invention can be carried out in relatively short time and under relatively low temperature, thereby the invention has the advantages of simplifying process, lowering cost and avoiding the damage on the surface of the silicon. The invention includes following procedures: (1) the reaction cavity of the silicon slice is charged with the gases (ClF3 and H2); (2) after the oxidizing reaction of the charged gas and the natural oxidizing layer, the SiOF or Si2OF6 generated by the natural oxidizing layer is volatilized. The parameters of the gases(ClF3 and H2) are that the flow rates of the ClF3 and the H2 are less than 1slm and 5 to 100slm respectively, the time is 30 to 120s, the temperature is lower than 700 DEG C, the pressure is less than 700Torr; (3) the reaction cavity of the silicon slice is charged with the mixed gas(H2) again to expel the remained gas(ClF3).
Description
Technical field
The present invention relates to a kind of method of before silicon chip low-temperature epitaxy growth, removing natural oxidizing layer.
Background technology
Single crystal epitaxial materials such as present low temperature (less than 700 ℃) epitaxy method grown silicon or germanium silicon, holder's consequence in semiconducter device is made, but the complicated and difficult control of technology, especially before deposit low temperature silicon or germanium and silicon epitaxial, need the natural oxidizing layer and the metal impurities on surface are fully removed, to guarantee low-temperature epitaxy direct growth on monocrystalline substrate, not so the crystalline quality of low-temperature epitaxy will variation, is grown to serve as noncrystal or polycrystal, thereby influences the performance of device.Existing removal method is generally:
The first step, gas drivings such as use argon gas are for your plasma bombardment silicon chip surface, to remove surface oxide layer.
Second step increased germane air-flow his-and-hers watches top blast and sweeps, because the germanium oxide volatilization is very fast, it is very fast to remove surface oxide layer.
The 3rd step, use HF-LAST (using hydrofluoric acid treatment at last) to clean, at high temperature continue hot pre-treatment of long period then, and the hydrogenation air-blowing is swept.
In the 4th step, use low flow silicon line with the formation silicon monoxide, thereby make desorption accelerate.
But there is following problem in above-mentioned technology:
1, the argon gas ion bombardment can form damage or pollution at silicon face.
2, the germane gas flow purging germanium film of can growing on the surface, thus device performance influenced.
3, the pyritous hydrogen treat can increase the diffusion again of dopant in the substrate, makes device electrical performance change.
Except that above-mentioned distinct disadvantage, the whole process flow complexity, the operating time is long, and cost is higher.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of removing natural oxidizing layer before silicon chip low-temperature epitaxy growth, it can carry out under short period and lesser temps, and then simplified technology, and reduced cost, also avoided damage in addition to silicon chip surface.
In order to solve above technical problem, the invention provides a kind of method of before silicon chip low-temperature epitaxy growth, removing natural oxidizing layer, it comprises the steps: the first step, feeds gas ClF in the reaction chamber of silicon chip
3And H
2In second step, after feeding gas and natural oxidizing layer oxidizing reaction, wherein natural oxidizing layer generates SiOF or Si
2OF
6Volatilization.
At the described ClF of the first step
3And H
2Gas standard is as follows: flow: H
2Be 5slm-100slm, ClF
3Less than 1slm; Time: 30s-120s; Temperature is less than 700 ℃; Pressure is less than 700Torr.
It also comprised for the 3rd step, fed H once more
2Mixed gas is with residual ClF
3Gas is driven away.
Because the present invention adopts ClF
3(chlorine trifluoride) and H
2The surface purges just can finish the removal natural oxidizing layer, compare with the rapid treatment process of multistep in the prior art, simplified technology, compare with argon gas ion bombardment in the prior art, avoided the damage to silicon face, continued hot pre-treatment of long period down with high temperature of the prior art, the present invention can finish under short period (60s-120s) and lesser temps, so just shorten the process time, and then reduced cost.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the method flow synoptic diagram that the present invention removes natural oxidizing layer;
Fig. 2 is the operating process synoptic diagram of Fig. 1 correspondence.
Embodiment
As shown in Figure 1, it is the method flow synoptic diagram that the present invention removes natural oxidizing layer, describes in conjunction with Fig. 2, and Fig. 2 is the operating process synoptic diagram of Fig. 1 correspondence.It comprises the steps:
Because entire treatment temperature of the present invention can remain on below 700, has so just reduced the influence of high temperature to silicon chip, and can shorten the time of waiting for cooling, and simple to operate than prior art, work simplification.
Claims (5)
1. a method of removing natural oxidizing layer before silicon chip low-temperature epitaxy growth is characterized in that it comprises the steps:
The first step feeds gas CIF in the reaction chamber of silicon chip
3And H
2
In second step, after feeding gas and natural oxidizing layer oxidizing reaction, wherein natural oxidizing layer generates SiOF or Si
2OF
6Volatilization.
2. the method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth as claimed in claim 1 is characterized in that it also comprised for the 3rd step, feeds H once more
2Mixed gas is with residual CIF
3Gas is driven away.
3. the method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth as claimed in claim 1 or 2 is characterized in that, comprises also that before carrying out the first step silicon chip is carried out RCA to be cleaned.
4. the method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth as claimed in claim 1 is characterized in that, described low-temperature epitaxy growth is silicon single crystal or the monocrystalline germanium silicon in growth below 700 ℃.
5. the method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth as claimed in claim 1 is characterized in that, at the described CIF of the first step
3And H
2Gas standard is as follows: flow: H
2Be 5slm-100slm, CIF
3Less than 1slm; Time: 30s-120s; Temperature is less than 700 ℃; Pressure is less than 700Torr.
Priority Applications (1)
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CNA2006101184968A CN101191252A (en) | 2006-11-20 | 2006-11-20 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
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CNA2006101184968A CN101191252A (en) | 2006-11-20 | 2006-11-20 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
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CN101191252A true CN101191252A (en) | 2008-06-04 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103928319A (en) * | 2014-04-08 | 2014-07-16 | 上海华力微电子有限公司 | Germanium-silicon epitaxy growing method |
CN105632888A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Removing method of native oxide layer of FinFet device before source-drain epitaxy |
CN105632918A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Removing method of native oxide layer of FinFet device before source-drain epitaxy |
CN108538780A (en) * | 2018-04-18 | 2018-09-14 | 睿力集成电路有限公司 | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film |
-
2006
- 2006-11-20 CN CNA2006101184968A patent/CN101191252A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103928319A (en) * | 2014-04-08 | 2014-07-16 | 上海华力微电子有限公司 | Germanium-silicon epitaxy growing method |
CN105632888A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Removing method of native oxide layer of FinFet device before source-drain epitaxy |
CN105632918A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Removing method of native oxide layer of FinFet device before source-drain epitaxy |
CN108538780A (en) * | 2018-04-18 | 2018-09-14 | 睿力集成电路有限公司 | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film |
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Open date: 20080604 |