CN108447772A - A kind of manufacturing method of COOLMOS silicon epitaxial wafers - Google Patents

A kind of manufacturing method of COOLMOS silicon epitaxial wafers Download PDF

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Publication number
CN108447772A
CN108447772A CN201810244647.7A CN201810244647A CN108447772A CN 108447772 A CN108447772 A CN 108447772A CN 201810244647 A CN201810244647 A CN 201810244647A CN 108447772 A CN108447772 A CN 108447772A
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silicon
manufacturing
epitaxial
flows
polishing
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CN108447772B (en
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刘勇
邓雪华
孙健
杨帆
任凯
石卓亚
骆红
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NANJING GUOSHENG ELECTRONIC CO Ltd
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NANJING GUOSHENG ELECTRONIC CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

The present invention relates to a kind of COOLMOS manufacturing methods of Multi-layer Epitaxial Silicon piece, technical matters is：It using monolithic normal pressure silicon epitaxy equipment, first has to that suitable H2 flows, temperature and time is selected to carry out baking processing to silicon substrate, removes the natural oxidizing layer on surface, ensure pre-epitaxy surface quality.Secondly it uses low discharge HCL, low polishing speed to carry out gas polishing to substrate surface, reduces photoetching and injection link is damaged caused by silicon chip surface.Epitaxial growth：Using SiHCl3 as silicon source, using higher temperature, while main H2 flows are increased, to reduce growth rate, growth meets the epitaxial layer of COOLMOS requirement on devices.

Description

A kind of manufacturing method of COOLMOS silicon epitaxial wafers
Technical field
The present invention relates to silicon epitaxial wafers, the especially manufacturing method of COOLMOS silicon epitaxial wafers.
Background technology
When making COOLMOS devices in the method that multiple extension and ion implanting are combined, delayed since silicon chip is outer every time Primary ions injection and photoetching will be carried out, slight damage often is generated to silicon chip surface, again before extension, to damaging layer Processing is crucial.The method routinely used is to be passed through the progress gas polishing of HCl gases, if HCl polishing speeds in existing method It crosses and causes production efficiency low slowly, the too fast circuitous pattern that can lead to photoetching of polishing speed damages.Last multiple extension simultaneously Afterwards, there is certain distortion in photoetching rotating savings, influences litho machine to mark, therefore picture distortion control is also key.
In summary, it is necessary to design a kind of manufacturing method for COOLMOS silicon epitaxies, ensure efficient throwing Under optical speed, silicon chip epitaxial layer quality is improved, while effectively control single layer epitaxy layer thickness reduces picture distortion.
Invention content
For problems of the prior art, according to epitaxy technique method, surface damage removing method and weaken figure The method of shape distortion, the present invention proposes a kind of manufacturing method of novel epitaxial wafer can compared with conventional epitaxial method Optimized epitaxial layer surface quality, reducing damage influences epitaxial layer, while optimized epitaxial layer thickness reduces picture distortion, meets Requirement of the COOLMOS devices to extension.
In order to achieve the above objectives, following technical solution can be used in the present invention：
A kind of manufacturing method of COOLMOS silicon epitaxial wafers, includes the following steps：
A kind of manufacturing method of COOLMOS silicon epitaxial wafers, which is characterized in that include the following steps：
(1), surface clean is carried out to silicon chip；
(2), HC1 high-temperature process is carried out to pedestal, removes reactant remaining on pedestal；
(3), it is loaded into silicon substrate after cooling base；
(4), heating carries out silicon chip H2Baking；
(5), gas attack polishes silicon chip surface；
(6), it heats up after polishing, while doped source is exclusive, exclusive flow is determined according to the resistivity demand of epitaxial layer；
(7), epitaxial growth controls epitaxy layer thickness.
In the step of gas attack of above-mentioned steps (5) polishes silicon chip surface, it is passed through the HCl gas of 0.5-1slm flows The H2 of body and 60-100slm flows is polished, and polishing speed is 0.1-0.15 μm/min, polishing time 1-3min, polishing Thickness is 0.2-0.5 μm, polish temperature and H in step (4)2Toast equality of temperature；Epitaxial layer is controlled in above-mentioned steps (7) epitaxial growth In thickness step, TCS, H2 and doped source are passed through reaction cavity simultaneously and carry out epitaxial growth.
Advantageous effect：The manufacturing method of the COOLMOS silicon epitaxial wafers of the present invention, it is excellent compared with conventional epitaxial method Change epi-layer surface quality, reducing damage influences epitaxial layer, while can optimized epitaxial layer thickness, reduce picture distortion, it is full Requirement of the sufficient COOLMOS devices to extension.Especially before epitaxial growth, smaller flow HCl and H2 is passed through, it is therefore an objective to eliminate table The damaging layer in face；When epitaxial growth, the growth rate of every layer of extension is strictly controlled, it is therefore an objective to it is consistent to increase each layer of parameter Property, reduce picture distortion.
Preferably, in step (2), high temperature range is 1150-1190 DEG C
Preferably, in step (3), cooling base is to 850 DEG C.
Preferably, in step (4), 1100-1130 DEG C of baking temperature, time 20-40 second of baking toasts H2Flow 120- 180slm。
Preferably, in step (6), temperature rises to 1150-1190 DEG C after polishing.
Preferably, the H2, growth rate 1.5- of TCS the and 60-120slm flows of 4-8g flows are passed through in step (7) 2.5μm/min。
Description of the drawings
Fig. 1 is the flow chart of silicon epitaxial wafer manufacturing method of the present invention；
Fig. 2 is ASM E2000 reaction chamber structure figures；
Fig. 3 is before extension and repeatedly outer to delay to comparing figure at mark.
Specific implementation mode
The invention discloses a kind of manufacturing method of COOLMOS silicon epitaxial wafers, specific implementation mode is as follows.
Embodiment one：
A kind of manufacturing method of COOLMOS silicon epitaxial wafers of the present embodiment includes the following steps：
For ultra-clean chamber environmental Kuznets Curves at 10 grades, environment temperature is 20 ± 1 DEG C, and for humid control 50 ± 10%, extension selects ASM E2000 monolithic epitaxial furnaces, substrate select N<100>, the back sides Sb SiO2 back of the body envelopes.As shown in figure 3, the ASM E2000 growing epitaxial silicons Equipment includes pedestal 1, the base ring 2 on pedestal 1, the center thermocouple 3 being arranged in base ring 2, equally also includes front end heat Even 4, rear end thermocouple 5, side thermocouple 6, side assist thermocouple 7.Pedestal is for high purity graphite pedestal and as infrared heating body, mainly Carrier gas H2 purity is 99.9999% or more.
Reative cell cleans：The silica article used in quartz bell cover and reative cell must be carefully clear before carrying out extension It washes, thoroughly removes the deposit residue on quartz bell cover inner wall and quartz piece.
The first step：Acid solution surface clean is carried out to silicon chip, cleaning solution is ammonium hydroxide+hydrogen peroxide+deionized water.
Second step：Reative cell high-temperature process：Before each epitaxial growth, graphite base must carry out high-temperature process, removal Remaining reactant on pedestal.
Third walks：Cooling reaction chamber is loaded into silicon substrate to low temperature.
4th step：Heating carries out silicon chip H2Baking reduces epitaxial layer defects.
5th step：Gas attack polishes silicon chip surface, is passed through the H2 of the HCl gases and 100slm flows of 0.5slm flows It is polished, polishing speed is 0.1 μm/min, and polishing time 1min, polishing thickness is 0.1 μm, polish temperature and step the 4th H in step2Toast equality of temperature.
6th step：Temperature rises to 1150 DEG C after polishing, while doped source is exclusive, and exclusive flow is according to the resistivity of epitaxial layer Demand is determined
7th step：Epitaxial growth controls epitaxy layer thickness：It is outer that TCS, H2 and doped source are passed through reaction cavity progress simultaneously Epitaxial growth, is passed through the H2 of the TCS and 120slm flows of 4g flows, and growth rate is 1.5 μm/min.Source flux is adulterated according to extension The demand of layer resistivity is determined.
Embodiment two
Preceding four step is the same as described in embodiment one.
5th step：Gas attack to silicon chip surface polish, be passed through 1slm flows HCl gases and 60slm flows H2 into Row polishing, polishing speed are 0.15 μm/min, and polishing time 3min, polishing thickness is 0.45 μm, polish temperature and step the 4th H in step2Toast equality of temperature.
6th step：Temperature rises to 1190 DEG C after polishing, while doped source is exclusive, and exclusive flow is according to the resistivity of epitaxial layer Demand is determined
7th step：Epitaxial growth controls epitaxy layer thickness：It is outer that TCS, H2 and doped source are passed through reaction cavity progress simultaneously Epitaxial growth, is passed through the H2 of the TCS and 60slm flows of 8g flows, and growth rate is 2.5 μm/min.Source flux is adulterated according to extension The demand of layer resistivity is determined.
Embodiment three
Preceding four step is the same as described in embodiment one.
5th step：Gas attack polishes silicon chip surface, is passed through the H2 of the HCl gases and 80slm flows of 0.8slm flows It is polished, polishing speed is 0.12 μm/min, and polishing time 2min, polishing thickness is 0.24 μm, polish temperature and step the H in four steps2Toast equality of temperature.
6th step：Temperature rises to 1170 DEG C after polishing, while doped source is exclusive, and exclusive flow is according to the resistivity of epitaxial layer Demand is determined
7th step：Epitaxial growth controls epitaxy layer thickness：It is outer that TCS, H2 and doped source are passed through reaction cavity progress simultaneously Epitaxial growth, is passed through the H2 of the TCS and 80slm flows of 6g flows, and growth rate is 2 μm/min.Source flux is adulterated according to epitaxial layer The demand of resistivity is determined.
Above operating procedure is shown in attached drawing 1.
It tests and can obtain by the silicon epitaxial wafer manufactured to the method by embodiment one, two, three, outside made silicon It is intact to prolong piece lattice structure, surface-brightening is without thin bright spot, no alice and edge crystalline polamer, and consistency is preferable between layers, Picture distortion is small, fully meets the requirement of element manufacturing.
The present invention implement the technical solution method and approach it is very much, the above be only the present invention preferred implementation Mode.It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, also Several improvements and modifications can be made, these improvements and modifications also should be regarded as protection scope of the present invention.It is unknown in the present embodiment The available prior art of true each component part is realized.

Claims (6)

1. a kind of manufacturing method of COOLMOS silicon epitaxial wafers, which is characterized in that include the following steps：
(1), surface clean is carried out to silicon chip；
(2), HC1 high-temperature process is carried out to pedestal, removes reactant remaining on pedestal；
(3), it is loaded into silicon substrate after cooling base；
(4), heating carries out silicon chip H2Baking；
(5), gas attack polishes silicon chip surface；
(6), it heats up after polishing, while doped source is exclusive, exclusive flow is determined according to the resistivity demand of epitaxial layer；
(7), epitaxial growth controls epitaxy layer thickness.
In the step of gas attack of above-mentioned steps (5) polishes silicon chip surface, be passed through 0.5-1slm flows HCl gases and The H2 of 60-100slm flows is polished, and polishing speed is 0.1-0.15 μm/min, polishing time 1-3min, polishing thickness It is 0.2-0.5 μm, polish temperature and H in step (4)2Toast equality of temperature；Epitaxy layer thickness is controlled in above-mentioned steps (7) epitaxial growth In step, TCS, H2 and doped source are passed through reaction cavity simultaneously and carry out epitaxial growth.
2. the manufacturing method of silicon epitaxial wafer according to claim 1, which is characterized in that in step (2), high temperature range is 1150-1190℃。
3. the manufacturing method of silicon epitaxial wafer according to claim 1, which is characterized in that in step (3), cooling base is extremely 850℃。
4. the manufacturing method of silicon epitaxial wafer according to claim 1, which is characterized in that in step (4), baking temperature 1100-1130 DEG C, time 20-40 second of baking toasts H2Flow 120-180slm.
5. the manufacturing method of silicon epitaxial wafer according to any one of claim 1 to 4, which is characterized in that in step (6), Temperature rises to 1150-1190 DEG C after polishing.
6. the manufacturing method of silicon epitaxial wafer according to any one of claim 1 to 4, which is characterized in that lead in step (7) Enter the H2 of the TCS and 60-120slm flows of 4-8g flows, growth rate is 1.5-2.5 μm/min.
CN201810244647.7A 2018-03-23 2018-03-23 Manufacturing method of silicon epitaxial wafer for COO L MOS Active CN108447772B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022100408A1 (en) * 2020-11-12 2022-05-19 重庆万国半导体科技有限公司 Multilayer reduced pressure epitaxial growth method
CN116525419A (en) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 Preparation method of silicon epitaxial wafer for COOLMOS

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472718A (en) * 1990-07-13 1992-03-06 Nec Corp Epitaxial growth method
JP2004327800A (en) * 2003-04-25 2004-11-18 Sumitomo Mitsubishi Silicon Corp Method for manufacturing epitaxial wafer
CN1936109A (en) * 2005-09-22 2007-03-28 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101814428A (en) * 2009-02-25 2010-08-25 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN103247576A (en) * 2013-04-27 2013-08-14 河北普兴电子科技股份有限公司 Preparation method of P-layer silicon epitaxial wafer on P++ substrate
CN104576307A (en) * 2013-10-10 2015-04-29 有研新材料股份有限公司 Method for eliminating micro particle aggregation on surface of 12-inch monocrystalline silicon epitaxial wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472718A (en) * 1990-07-13 1992-03-06 Nec Corp Epitaxial growth method
JP2004327800A (en) * 2003-04-25 2004-11-18 Sumitomo Mitsubishi Silicon Corp Method for manufacturing epitaxial wafer
CN1936109A (en) * 2005-09-22 2007-03-28 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101814428A (en) * 2009-02-25 2010-08-25 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN103247576A (en) * 2013-04-27 2013-08-14 河北普兴电子科技股份有限公司 Preparation method of P-layer silicon epitaxial wafer on P++ substrate
CN104576307A (en) * 2013-10-10 2015-04-29 有研新材料股份有限公司 Method for eliminating micro particle aggregation on surface of 12-inch monocrystalline silicon epitaxial wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022100408A1 (en) * 2020-11-12 2022-05-19 重庆万国半导体科技有限公司 Multilayer reduced pressure epitaxial growth method
CN116525419A (en) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 Preparation method of silicon epitaxial wafer for COOLMOS
CN116525419B (en) * 2023-06-09 2024-02-13 中电科先进材料技术创新有限公司 Preparation method of silicon epitaxial wafer for COOLMOS

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