CN105631081B - A kind of insertion method of FinFET dummy pattern - Google Patents
A kind of insertion method of FinFET dummy pattern Download PDFInfo
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- CN105631081B CN105631081B CN201410705663.3A CN201410705663A CN105631081B CN 105631081 B CN105631081 B CN 105631081B CN 201410705663 A CN201410705663 A CN 201410705663A CN 105631081 B CN105631081 B CN 105631081B
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Abstract
The present invention relates to a kind of insertion methods of FinFET dummy pattern, the described method includes: step S1: designing the virtual hierarchical element with fin grid, the virtual hierarchical element includes active area dummy pattern, wherein active area dummy pattern is located on the fin grid；Step S2: defining the lesser fin virtual boundary layer pattern of size, and fin virtual boundary layer pattern also has the feature on standard fin grid；Step S3: the virtual hierarchical element is inserted into configurations fin boundary；Step S4: the white space in domain other than configurations fin boundary is continuously inserted into the lesser fin virtual boundary layer pattern of size, to form the fin boundary layer region of the continuous one of fin grid, the virtual hierarchical element is inserted into according to the fin grid in the integrated fin boundary layer region, so that the active area dummy pattern in the virtual hierarchical element is located on the fin grid.The method makes entire domain obtain more uniform fin grid.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of insertion method of FinFET dummy pattern.
Background technique
With the continuous development of semiconductor technology, in order to improve the performance of device, need constantly to reduce integrated circuit device
Size promote three dimensional design such as FinFET (FinFET) with the continuous diminution of cmos device size
Development.
Relative to existing planar transistor, the FinFET is in the side such as channel control and reduction shallow ridges channel effect
Face has more superior performance；Planar gate is set to above the channel, and the grid described in FinFET is surround
The fin setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
When the dimensions of semiconductor devices is contracted to Nano grade, manufacturability design (Design for
Manufacturing, DFM) in semi-conductor industry nano-engineer flow and method have become more and more important.The DFM is
Refer to the rule by the production efficiency of fast lifting chip yield and for the purpose of reducing production cost, in the design of Unify legislation chip
Then, tool and method is work in a kind of predictable manufacturing process thus preferably duplication of the control integrated circuit to physics wafer
The design of skill changeability, so that reaching optimization from the whole process that wafer manufactures is designed into.
It is automatically added to dummy pattern (dummy) during the DFM to become more and more important, the dummy pattern can be with
The Density Distribution for helping improve target pattern keeps the device performance more uniform, increases process window when photoetching, etching
Deng.
For FinFET, when being inserted into dummy pattern, need to design active area domain (AA layout) in fin
On the fin grid in boundary layer (Fin Boundary layer), but in the white space other than configurations fin boundary
When being inserted into dummy pattern, do not ensure that the dislocation of fin grid does not occur for the dummy pattern of insertion, it is therefore desirable to virtual graph
The insertion method of case is improved further, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology the present invention, provides a kind of insertion side of FinFET dummy pattern
Method, comprising:
Step S1: the virtual hierarchical element with fin grid is designed, the virtual hierarchical element includes that active area is virtual
Pattern, wherein the active area dummy pattern is located on the fin grid；
Step S2: the lesser fin virtual boundary layer pattern of size is defined, is had in the fin virtual boundary layer pattern
The fin grid；
Step S3: the virtual hierarchical element is inserted into configurations fin boundary；
Step S4: it is lesser that the white space in domain other than configurations fin boundary is continuously inserted into the size
Fin virtual boundary layer pattern, to form the fin boundary layer region of the continuous one of fin grid, on the integrated fin boundary
The virtual hierarchical element is inserted into according to the fin grid in layer region, so that the active area in the virtual hierarchical element is empty
Quasi- pattern is located on the fin grid.
Optionally, the design coincidence pattern figure layer design rule of virtual hierarchical element described in the step S1.
Optionally, virtual hierarchical element described in the step S1 includes lamination boundary layer, described virtual folded for defining
The size of layer unit, each pattern in the virtual hierarchical element are located in the lamination boundary layer.
Optionally, the lamination boundary layer is located on the fin grid.
Optionally, active area dummy pattern described in the step S1 covers fin grid described in several rows, and up and down
Boundary is located on the fin grid.
Optionally, the definition of fin virtual boundary layer pattern described in the step S2 meets design rule.
Optionally, there is the fin grid in configurations fin boundary described in the step S3.
Optionally, with the lower left corner on configurations fin boundary, the lower right corner, the upper left corner or the right side in the step S3
The virtual hierarchical element is inserted into as initial point in upper angle, so that the active area dummy pattern in the hierarchical element is positioned at described
On the fin grid of configurations fin boundary figure layer.
Optionally, very close to each other between fin virtual boundary layer pattern described in the step S4 to be interconnected to form one
Body.
Optionally, the fin Grid Align in fin fictitious line interlayer described in the step S4 is interconnected to form fin
Grid is continuously integrated.
Optionally, with the lower left corner, the lower right corner, the upper left corner of the integrated fin boundary layer region in the step S4
Or the virtual hierarchical element is inserted into as initial point in the upper right corner.
In order to solve the problems in the existing technology the present invention, provides a kind of insertion side of FinFET dummy pattern
Method, the virtual hierarchical element being inserted into the method in order to prevent occur the dislocation of fin grid, define fin virtual boundary first
Layer, the fin fictitious line interlayer has the size of very little, and has fin grid, then on configurations fin side
It is inserted into the fin fictitious line interlayer in white space other than boundary, the fin fictitious line interlayer is made to be linked to be the very big fin of area
Sheet border layer region, the fin boundary layer region have the fin grid background of consistent dislocation-free, are with the fin grid
Reference is inserted into the virtual hierarchical element, is located at the virtual hierarchical element on fin grid.The present invention cleverly solves
The problem of dummy pattern fin grid dislocation, occurs for the white space different location other than configurations fin boundary, makes entire version
Figure obtains more uniform fin grid, in favor of technique manufacture.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the structural schematic diagram in configurations fin of the present invention boundary；
Fig. 2 a-2e is the process schematic that virtual hierarchical element is inserted into the embodiment of the invention；
Fig. 2 f is to be not inserted into virtual hierarchical element in the embodiment of the invention to make the signal of the entire domain
Figure；
Fig. 3 is the process flow chart that virtual hierarchical element is inserted into the embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate side of the present invention
Method.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor field is familiar with.Of the invention is preferable
Embodiment is described in detail as follows, however other than these detailed descriptions, the present invention can also have other embodiments.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.
Embodiment 1
In order to solve the problems in the existing technology the present invention, provides a kind of insertion side of FinFET dummy pattern
Method, comprising:
Step S1: the virtual hierarchical element with fin grid is designed, the virtual hierarchical element includes that active area is virtual
Pattern, wherein the active area dummy pattern is located on the fin grid；
Step S2: defining the lesser fin virtual boundary layer pattern of size, and the fin virtual boundary layer pattern has position
Feature on the standard fin grid；
Step S3: the virtual hierarchical element is inserted into configurations fin boundary；
Step S4: it is lesser that the white space in domain other than configurations fin boundary is continuously inserted into the size
Fin virtual boundary layer pattern, to form the fin boundary layer region of the continuous one of fin grid, on the integrated fin side
The virtual hierarchical element is inserted into according to the fin grid in interlayer region, so that the active area in the virtual hierarchical element
Dummy pattern is located on the fin grid.
The method that the present invention provides a kind of to be inserted into dummy pattern in the domain of FinFET, to help improve target
The Density Distribution of pattern keeps the device performance more uniform, increases the process window etc. when photoetching, etching.
It is the configurations containing FinFET in domain 10 (as shown in Figure 1), is wrapped in the FinFET pattern domain
Containing active area 102, wherein the active area 102 in the configurations has the feature being located on the standard fin grid, institute
It is as shown in phantom in FIG. to state fin grid 101.
The configurations further include pattern layer bounds layer 103, wherein the pattern layer bounds layer 103 also is located at institute
It states on fin grid 101, the active area 102 is located within the pattern layer bounds layer 103.
Wherein, as shown in Figure 1, with arrow direction be it is upper, under being away from arrow direction, the active area 102
On the fin grid 101, can be construed to the active area 102 should be completely covered fin grid, described active
The top edge in area 102 and lower edge cannot be located at white space, can not be located in fin grid, top edge can be only positioned at institute
The top line of the fin grid of covering, lower edge can be only positioned at the bottom line of covered fin grid, be not spy
In the case where different explanation, below all be related to saying that pattern is located on fin grid referring to the explanation.
The method of the invention defines virtual hierarchical element first, and the virtual hierarchical element is set for being inserted into the pattern
Region in meter fin boundary and domain other than configurations fin boundary is made with helping improve the Density Distribution of target pattern
It meets design rule.
Wherein, it is likewise formed with fin grid in the virtual hierarchical element 20, as shown in Figure 2 a, wherein described virtual folded
Layer unit 20 is inserted into subsequent steps in configurations fin boundary, the fin net in the virtual hierarchical element 20
Lattice are identical as fin grid in the configurations (domain 10).
As illustrated in figures 2 a-2b, in the virtual hierarchical element 20, including lamination boundary layer 203, active area dummy pattern
202 and fin grid 201 (dotted line in figure), it can also include other figure layers, such as grid etc., the pattern layer combines to be formed
The virtual hierarchical element 20.
Wherein, the lamination boundary layer of virtual hierarchical element described in the step S1 is located on the fin grid, including
The fin grid of quantitative (on-quantized grid), the lamination boundary layer is for defining the big of the virtual hierarchical element
Small, each pattern in the virtual hierarchical element is located in the lamination boundary layer.
Further, the active area dummy pattern covers fin grid described in several rows, and up-and-down boundary is positioned at described
On fin grid.
The fin virtual boundary layer pattern has lesser size in step s 2, can be the virtual level of minimum dimension
Boundary layer, the fin virtual boundary layer pattern for filling other than configurations fin boundary in subsequent steps
White space guarantees configurations when being inserted into dummy pattern to form the fin boundary layer region of the continuous one of fin grid
Fin grid is aligned as far as possible inside the dummy pattern of white space different location insertion other than fin boundary, prevents net
The problem of lattice misplace, makes entire domain obtain more uniform fin grid, in favor of technique manufacture.
The fin grid in fin grid and the virtual hierarchical element 20 in the fin virtual boundary layer pattern, institute
It is all the same to state fin grid in configurations 10.
Wherein, the definition and design of the fin virtual boundary layer pattern also need to meet design rule.
In the step S3, the virtual hierarchical element in the step S1 is inserted into inside the configurations,
Specifically, it is inserted into the fin boundary layer of the configurations.
Specifically, by the method that virtual hierarchical element is inserted into configurations fin boundary described in step S1 include but
It is not limited to following methods: being inserted into the virtual lamination list using the lower right corner on configurations fin boundary as initial point
Member is located at the dummy pattern in the virtual hierarchical element in the pattern layer bounds layer
On fin grid, as shown in the figure of the lower right Fig. 2 c, the boundary layer and the equal position of active area dummy pattern of the virtual hierarchical element
In on the fin grid on configurations fin boundary.
Optionally, it can also be inserted into using the lower left corner, the upper left corner or the upper right corner of pattern layer bounds layer as initial point
The virtual hierarchical element.
It is described virtual folded being inserted into due to the virtual hierarchical element and pattern figure layer fin grid having the same
It can guarantee the active area dummy pattern when layer unit on the fin grid of pattern figure layer, even if insertion is multiple will not still to be sent out
Raw dislocation (disalignment) problem.
But as shown in Figure 2 c, comprising a large amount of empty between the lower right corner and the configurations fin boundary in the upper left corner
White region, when being inserted into the virtual hierarchical element in a large amount of white spaces, it is difficult to ensure that different white space insertions
Grid where active area dummy pattern in virtual hierarchical element does not misplace.
Therefore, the generation of the above problem in order to prevent, the fin defined in inserting step S2 in a large amount of white spaces
Piece virtual boundary layer pattern, since the fin virtual boundary layer pattern has very small size, in the white space
The middle filling fin virtual boundary layer pattern as much as possible, to form the fin of the continuous one of fin grid as big as possible
Boundary layer region, as shown in Figure 2 d.
Further, in this step, the fin virtual boundary layer pattern, the fin fictitious line interlayer are continuously inserted into
Spacing between pattern is 0, to guarantee that the fin virtual boundary layer pattern is closely adjacent, becomes the biggish a piece of fin of area
Boundary layer region.
Further, the fin Grid Align insertion in the fin virtual boundary layer pattern, the fin Grid Align shape
The longer fin grid of Cheng Yilie length, after being inserted into the fin virtual boundary layer pattern, the white space is formd
With the consistent fin boundary layer region of fin grid background, then according to the institute in the fin grid background inserting step S1
State virtual hierarchical element, the problem of grid dislocation occurs for virtual hierarchical element described in the very good solution prior art.
Optionally, with the lower left corner, the lower right corner, the upper left corner or the upper right of the fin boundary layer region in the step S4
The virtual hierarchical element is inserted into as initial point in angle.It is located at the dummy pattern in the virtual hierarchical element after insertion described
On fin grid in fin boundary layer region, as shown in Figure 2 e, the boundary layer of the virtual hierarchical element and active area are virtual
Pattern is respectively positioned on the fin grid of the fin boundary layer region, so as to avoid the generation of grid dislocation.The present invention in order to
Problems of the prior art are solved, a kind of method for being inserted into FinFET dummy pattern are provided, in order to anti-in the method
Grid dislocation occurs for the virtual hierarchical element being only inserted into, and defines fin virtual boundary layer pattern, the fin virtual boundary first
Layer pattern has the size of very little, and has fin grid, then the blank area other than configurations fin boundary
It is inserted into the fin virtual boundary layer pattern in domain, the fin virtual boundary layer pattern is made to be linked to be the very big fin boundary of area
Layer region, the fin boundary layer region has fin grid background, using the fin grid as reference, is inserted into described virtual folded
Layer unit is located at the virtual hierarchical element on fin grid, cleverly solves the problems, such as grid dislocation, makes entire domain
More uniform fin grid is obtained, in favor of technique manufacture.
The method of the invention has good effect, and wherein attached drawing 2f is the first half for being not carried out step S4 --
White space in domain other than configurations fin boundary is continuously inserted into the lesser fin fictitious line interlayer figure of the size
Case directly executes showing when being inserted into the virtual hierarchical element to form the fin boundary layer region of the continuous one of fin grid
It is intended to, dummy pattern fin occurs for the white space different location other than configurations fin boundary as can be seen from the figure
The problem of piece grid misplaces, as shown in figure arrow and dotted line position, the fin grid for obtaining entire domain is not uniform enough, no
Conducive to technique manufacture.
Wherein, Fig. 3 is the process flow chart that virtual hierarchical element is inserted into the embodiment of the invention, is specifically wrapped
Include following steps:
Step S1: the virtual hierarchical element with fin grid is designed, the virtual hierarchical element includes that active area is virtual
Pattern, wherein the active area dummy pattern is located on the fin grid；
Step S2: defining the lesser fin virtual boundary layer pattern of size, and the fin virtual boundary layer pattern has position
Feature on the standard fin grid；
Step S3: the virtual hierarchical element is inserted into configurations fin boundary；
Step S4: it is lesser that the white space in domain other than configurations fin boundary is continuously inserted into the size
Fin virtual boundary layer pattern, to form the fin boundary layer region of the continuous one of fin grid, on the integrated fin side
The virtual hierarchical element is inserted into according to the fin grid in interlayer region, so that the active area in the virtual hierarchical element
Dummy pattern is located on the fin grid.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of insertion method of FinFET dummy pattern, comprising:
Step S1: designing the virtual hierarchical element with fin grid, and the virtual hierarchical element includes active area dummy pattern,
Wherein, the active area dummy pattern is located on the fin grid；
Step S2: defining the lesser fin virtual boundary layer pattern of size, and the fin virtual boundary layer pattern, which has, is located at institute
State the feature on fin grid；
Step S3: the virtual hierarchical element is inserted into configurations fin boundary；
Step S4: the white space in domain other than configurations fin boundary is continuously inserted into the lesser fin of the size
Virtual boundary layer pattern, to form the fin boundary layer region of the continuous one of fin grid, in the integrated fin boundary layer
The virtual hierarchical element is inserted into according to the fin grid in region, so that the active area in the virtual hierarchical element is virtual
Pattern is located on the fin grid.
2. the method according to claim 1, wherein the design of virtual hierarchical element described in the step S1 accords with
Close pattern figure layer design rule.
3. the method according to claim 1, wherein virtual hierarchical element described in the step S1 includes lamination
Boundary layer, for defining the size of the virtual hierarchical element, each pattern in the virtual hierarchical element is located at the lamination
In boundary layer.
4. according to the method described in claim 3, it is characterized in that, the lamination boundary layer is located on the fin grid.
5. if the method according to claim 1, wherein active area dummy pattern described in the step S1 covers
Fin grid described in dry row, and up-and-down boundary is located on the fin grid.
6. the method according to claim 1, wherein fin virtual boundary layer pattern described in the step S2
Definition meets design rule.
7. the method according to claim 1, wherein having in configurations fin boundary described in the step S3
There is the fin grid.
8. method according to claim 1 or claim 7, which is characterized in that with configurations fin side in the step S3
The virtual hierarchical element is inserted into as initial point in the lower left corner, the lower right corner, the upper left corner or the upper right corner on boundary, so that the lamination
Active area dummy pattern in unit is located on the fin grid of configurations fin boundary figure layer.
9. the method according to claim 1, wherein fin virtual boundary layer pattern described in the step S4 it
Between very close to each other be interconnected to form one.
10. the method according to claim 1, wherein in fin fictitious line interlayer described in the step S4
Fin Grid Align is interconnected to form fin grid continuously one.
11. the method according to claim 1, wherein with the integrated fin boundary in the step S4
The virtual hierarchical element is inserted into as initial point in the lower left corner, the lower right corner, the upper left corner or the upper right corner of layer region.
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| CN201410705663.3A CN105631081B (en) | 2014-11-27 | 2014-11-27 | A kind of insertion method of FinFET dummy pattern |
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| CN201410705663.3A CN105631081B (en) | 2014-11-27 | 2014-11-27 | A kind of insertion method of FinFET dummy pattern |
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| CN105631081B true CN105631081B (en) | 2019-01-22 |
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| CN101123203A (en) * | 2006-08-11 | 2008-02-13 | 东部高科股份有限公司 | Method of forming dummy pattern |
| CN101364595A (en) * | 2007-08-10 | 2009-02-11 | 东部高科股份有限公司 | Semiconductor device layout and method for placing dummy patterns therein |
| CN102468182A (en) * | 2010-11-12 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Method and device for increasing fin device density for unaligned fins |
| CN102799060A (en) * | 2011-05-26 | 2012-11-28 | 联华电子股份有限公司 | Dummy pattern and method for forming same |
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2014
- 2014-11-27 CN CN201410705663.3A patent/CN105631081B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123203A (en) * | 2006-08-11 | 2008-02-13 | 东部高科股份有限公司 | Method of forming dummy pattern |
| CN101364595A (en) * | 2007-08-10 | 2009-02-11 | 东部高科股份有限公司 | Semiconductor device layout and method for placing dummy patterns therein |
| CN102468182A (en) * | 2010-11-12 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Method and device for increasing fin device density for unaligned fins |
| CN102799060A (en) * | 2011-05-26 | 2012-11-28 | 联华电子股份有限公司 | Dummy pattern and method for forming same |
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