CN111259613B - Electronic device and layout method of integrated circuit - Google Patents
Electronic device and layout method of integrated circuit Download PDFInfo
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- CN111259613B CN111259613B CN201811353202.9A CN201811353202A CN111259613B CN 111259613 B CN111259613 B CN 111259613B CN 201811353202 A CN201811353202 A CN 201811353202A CN 111259613 B CN111259613 B CN 111259613B
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Abstract
The invention provides an electronic device and a layout method of an integrated circuit. The layout method of the integrated circuit comprises the following steps: receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit; presetting a plurality of virtual blocks, wherein the virtual blocks have different sizes; selecting at least one of the virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information; performing a layout density check on the updated layout information to obtain a check result; and reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result, and generating output layout information.
Description
Technical Field
The present invention relates to an electronic device and a layout method of an integrated circuit, and more particularly, to an electronic device and a layout method thereof capable of easily adjusting layout density.
Background
In the layout of integrated circuits, layout engineers may prefer to perform the layout of circuits at a relatively high density in order to maximize chip utilization. After completing the layout of the main circuit, the layout engineer performs the filling operation of the dummy blocks with respect to the blank area in the integrated circuit. After all the blank areas are filled with dummy blocks, the integrated circuit may not meet the design/layout specification requirements due to the high layout density. In such a case, the layout engineer can only manually make manual adjustments for each blank area in order to meet the requirements of the design/layout specifications.
The above-mentioned layout adjustment method needs to consume a lot of manpower, and the manual adjustment action of the layout engineer can not be in place at one time, often needs repeated adjustment actions, and can meet the requirements of design/layout specifications, and time and manpower are wasted.
Disclosure of Invention
The invention provides an electronic device and a layout method of an integrated circuit, which can easily adjust layout density.
The layout method of the integrated circuit comprises the following steps: receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit; presetting a plurality of virtual blocks, wherein the virtual blocks have different sizes; selecting at least one of the virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information; performing a layout density check on the updated layout information to obtain a check result; and reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result, and generating output layout information.
The electronic device is used for executing the layout action of the integrated circuit. The electronic device includes a memory and a processor. The memory is used for storing layout information and preset layout information of a plurality of virtual blocks, wherein the virtual blocks have different sizes. The processor is used for: receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit; selecting at least one of the virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information; performing a layout density check on the updated layout information to obtain a check result; the size of the set virtual blocks in the integrated circuit is reduced according to the checking result, and output layout information is generated.
Based on the above, the present invention fills the dummy blocks with different sizes in the blank area of the integrated circuit, and adjusts the size of the set dummy blocks therein to automatically adjust the layout density of the integrated circuit. Therefore, the adjustment of the layout density of the integrated circuit can be completed in an automatic mode, the trouble of manual adjustment is avoided, and the layout density of the integrated circuit can be set more accurately.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart of a layout method of an integrated circuit according to an embodiment of the invention;
FIGS. 2A-2C are schematic diagrams illustrating a plurality of virtual blocks according to embodiments of the present invention;
FIGS. 3A and 3B are schematic diagrams showing a step of a layout method according to an embodiment of the present invention;
FIG. 4 shows a schematic diagram of another step of the layout method of an embodiment of the present invention;
FIG. 5 and FIG. 6 are schematic diagrams illustrating another step of the layout method according to the embodiment of the present invention;
FIG. 7 shows a flow chart of a layout method of another embodiment of the present invention;
fig. 8 shows a schematic diagram of an electronic device according to an embodiment of the invention.
Description of the reference numerals
S110 to S150, S810 to S850: layout step of integrated circuit
100: integrated circuit
110-190, 1100, 1110, 1120: blank area
DA1: first density block
DA2: second density block
210. 220, 230: virtual block
BA1: blank space
DA31 to DA33: third density block
DB1, DB2, DB12, DB13, DB1A, DB1B, DB C: virtual block
DB1A ', DB1D': replacing virtual blocks
900: electronic device
910: processor and method for controlling the same
920: memory device
IGDS: layout information
DBN: virtual block
Detailed Description
Referring to fig. 1, step S110 receives layout information, and obtains a plurality of blank areas in the integrated circuit by parsing the layout information. Here, the layout information may be related information in a graphic data system (Graphic Database System, GDSII) format for recording the geometry of the plane of the integrated circuit layout, text labels, and related information about the structure composition. For the analysis details of the blank area, the first scrambled blank area (as shown in fig. 3A) in the integrated circuit can be obtained according to the layout information, and the first rectangle with the largest area in the first scrambled blank area can be found. Then, the first rectangle is removed from the first disordered blank area to update to obtain a second disordered blank area, and a second rectangle with the largest area is found out from the second disordered blank area. By repeating the above steps until the area of the n+1th rectangle having the largest area is smaller than the predetermined target, the analysis of the blank area can be completed. The first rectangle to the nth rectangle are blank areas.
Referring to fig. 1 and 3B, fig. 3B shows the result of the layout information analysis. In FIG. 3B, a plurality of blank areas 110-190, 1100, 1110, and 1120 in integrated circuit 100 are identified. The identified blank areas 110-190, 1100, 1110, 1120 may be framed in rectangular form. The blank areas 110-190, 1100, 1110, and 1120 may have the same or different dimensions.
Next, in step S120, a plurality of dummy blocks are preset, referring to fig. 1 and fig. 2A to 2C, and in fig. 2A, the dummy blocks 210 may include the first density blocks DA1. The first density block DA1 may be formed by active area elements of an integrated circuit. In this embodiment, the dummy block 210 may include a blank area BA1 with a certain size in addition to the first density block DA1.
In fig. 2B, the dummy block 220 includes a first density block DA1, a second density block DA2, and a blank area BA1. The second density block DA2 is disposed around the first density block DA1 and surrounds the first density block DA1. It should be noted that the size of the dummy block 220 is larger than the size of the dummy block 210. The second density block DA2 may be formed, for example, from a polysilicon layer in an integrated circuit.
In fig. 2C, the dummy block 230 includes a first density block DA1, a second density block DA2, a plurality of third density blocks DA31 to DA33, and a blank area BA1. The second density block DA2 is disposed at the edge of the first density block DA1. Third density blocks DA 31-DA 33 are inserted into second density block DA 2. The first density block DA1 and the third density blocks DA 31-DA 33 may have the same layout density and may be formed by active area elements of the integrated circuit. The second density block DA2 may be formed, for example, from a polysilicon layer in an integrated circuit. In some embodiments of the present invention, the dummy block 230 may not have the second density block DA2 or may not have the third density blocks DA31 to DA33. In addition, in the case where the dummy block 230 includes the third density blocks DA31 to DA33, the number of the third density blocks DA31 to DA33 may be one, two, or more than three, and the number (3) of the third density blocks DA31 to DA33 shown in fig. 2C is merely an example and is not intended to limit the scope of the present invention. It should be noted that the size of the dummy block 230 is larger than the size of the dummy block 220, and the size of the dummy block 220 is larger than the size of the dummy block 210.
In the present embodiment, the dummy blocks 210, 220 and 230 have different layout densities.
Next, referring back to fig. 1, in step S130, at least one of the virtual blocks is selected according to the size of each blank area in the integrated circuit, so as to perform a filling operation on the center position of each blank area, and generate updated layout information. Referring to fig. 1 and 4, in fig. 4, a blank area 140 is taken as an example, and a plurality of dummy blocks DB1 with the same size are filled in the blank area 140. Taking the blank area 110 as an example, the blank area 110 is filled into a plurality of dummy blocks DB1 and a plurality of dummy blocks DB2, wherein the sizes of the dummy blocks DB1 and the dummy blocks DB2 are different.
It should be noted that, regarding the filling operation of the virtual blocks, in the embodiment of the present invention, a plurality of frames may be respectively established according to a plurality of preset virtual blocks, wherein the frames may be established according to the sides of the virtual blocks respectively corresponding thereto. And, when executing filling the virtual block into the blank area, the blank area can be filled by the frame corresponding to the selected virtual block.
Regarding the details of the filling operation of the virtual blocks, N number of the receivable frames can be calculated according to the size of each blank area and the size of a first frame, and N number of the first frames is filled for each blank area, wherein N is an integer not smaller than 0. In detail, the long side and short side dimensions in the rectangular blank area are calculated, the number of the first frames which can be accommodated in the long side (=x) and the number of the first frames which can be accommodated in the short side (=y) are calculated, the maximum number of the first frames (x×y=n) is determined, and the maximum number of frames is filled into the rectangular blank area. Next, each blank area may generate one or more sub-blank areas, and in the embodiment of the present invention, M receivable amounts may be calculated according to the size of the sub-blank area and the size of a second frame. And then sequentially filling M second frames with smaller sizes into the sub-blank areas.
By repeating the above filling operation for each blank area in the integrated circuit, each blank area in the integrated circuit can be filled with virtual blocks, so as to complete step S130 and generate updated layout data.
Referring back to fig. 1, step S140 performs a layout density check on the updated layout data, and if the check result indicates that the layout density of the integrated circuit is higher than a preset threshold value, step S150 is performed to reduce the sizes of a plurality of set virtual blocks in the integrated circuit according to the check result and generate output layout information.
Referring to fig. 1, 5 and 6, in the implementation details of step S150, when the inspection result indicates that the layout density of the integrated circuit is higher than a predetermined threshold, one of the adjacent virtual blocks is a set virtual block. In fig. 5, one of two adjacent dummy blocks is set as a set dummy block. For example, in the integrated circuit 100, the blank area 140 is taken as an example, wherein the dummy block DB1A and the dummy block DB1B are adjacent in the horizontal direction. Therefore, the dummy block DB1A can be set as a set dummy block, and the dummy block DB1B can be set as a non-set dummy block. In addition, the dummy block DB1A and the dummy block DB1C are adjacent in the vertical direction, and the set dummy block has been set in the dummy block DB1A, and thus the dummy block DB1C may be set as a non-set dummy block. Similarly, the dummy block DB1D may be set as a set dummy block.
The threshold values may be obtained from design specifications and/or layout specifications provided by an integrated circuit manufacturing facility.
In fig. 5, the virtual block indicated by the virtual frame is a set virtual block, and the virtual block indicated by the real frame is a non-set virtual block. In the actual setting details, the Graphic Data System (GDS) number may be set for each of the set virtual block and the non-set virtual block. Wherein, the GDS number of all set virtual blocks may be 1, and the GDS number of all non-set virtual blocks may be 0, thereby identifying the type of the virtual block.
Incidentally, the setting manner of setting the dummy blocks may be not particularly limited, either by making one or two of the adjacent three dummy blocks be the setting dummy blocks or making one, two or three of the adjacent four dummy blocks be the setting dummy blocks.
Incidentally, regarding the above-mentioned operations of setting the virtual block and non-setting the virtual block, in other embodiments of the present invention, the operations may be performed with respect to the frame corresponding to the virtual block. When the blank area is filled with the relevant information of the frames, one of the adjacent frames can be set as a set frame, and the other frame is a non-set frame. Correspondingly, the setting operation of the graphic data system number can be performed for the setting frame and the non-setting frame.
Next, in fig. 6, a size reduction operation for setting the virtual block is performed. In the integrated circuit 100, the blank area 140 is taken as an example, the positions of the original set virtual blocks DB1A and DB1D are replaced with the replacement virtual blocks DB1A 'and DB1D' having relatively small dimensions, and the non-set virtual blocks DB1B and DB1C remain unchanged. In the present embodiment, instead of the dummy blocks DB1A 'and DB1D', the dummy block 220 of fig. 2B may be used, and the dummy blocks DB1B and DB1C may be the dummy block 230 of fig. 2C.
By performing the block replacement operation for the set dummy blocks DB1B and DB1C, the positions of the original set dummy blocks DB1B and DB1C can be increased by a large number of blank areas, and therefore, the layout density of the integrated circuit 100 can be automatically reduced.
Incidentally, if the filling operation for the blank area is performed by the frame corresponding to the virtual block, the replacement operation for the virtual block may be performed by the frame corresponding to the virtual block.
After the completion of step S150, the output layout information meeting the specification requirements can be effectively generated.
Incidentally, after the step of producing the output layout information is completed, layout density distribution information of the integrated circuit can be generated according to the output layout information. The layout density distribution information may be presented in a data format and analyzed by a data analysis format to provide for analysis by a layout engineer and/or design engineer.
Further, the output layout information is information that can meet specifications. Thus, output layout information may be provided to fabricate a photomask and to produce a physical integrated circuit from a semiconductor manufacturing facility.
As can be seen from the above description, the layout method according to the embodiment of the present invention can be automatically adjusted to the layout density of the integrated circuit so as to meet the specification. Therefore, the trouble of manual adjustment can be avoided, and the adjustment action of the layout density can be rapidly and accurately completed.
Referring now to fig. 7, fig. 7 is a flowchart illustrating a layout method according to another embodiment of the present invention. Step S810 identifies blank areas in the integrated circuit, and step S820 performs a filling operation of the virtual block according to the center position of each blank area. Step S820 may perform the filling operation according to the frame of the virtual block for the blank area, and after step S820 is completed, step S830 is performed to map the frame of the virtual block with the layout information corresponding thereto, so as to fill the actual layout content of the virtual block into the blank area. After the mapping operation of the frames and the layout information of all the virtual blocks is completed, updated layout information can be generated (step S840).
Step S850 may perform a layout density check, and check whether the layout density of the integrated circuit is too high, and when the layout density of the integrated circuit is too high, step S860 is performed to perform the replacement operation of the virtual block. By replacing the dummy blocks with relatively high density with the replacement dummy blocks with relatively low density, the layout density of the integrated circuit can be effectively reduced. The layout operation of the present embodiment is ended by the repeated inspection operation of the layout density and when the layout density of the integrated circuit meets the specification.
Details of the above steps are described in the foregoing embodiments, and are not repeated herein.
Referring to fig. 8, fig. 8 is a schematic diagram of an electronic device according to an embodiment of the invention. The electronic device 900 includes a processor 910 and a memory 920. Processor 910 and memory 920 are coupled to each other. The memory 920 is used for storing layout information IGDS and information of a plurality of predetermined virtual blocks DBN, wherein the virtual blocks DBN have different sizes. The processor 910 receives the layout information IGDS and the information of the virtual block DBN from the memory 920, and performs the layout method as in the above embodiments, thereby adjusting the layout density of the integrated circuit.
The details of the layout method are described in detail in the foregoing embodiments, and are not repeated herein.
In summary, the present invention presets a plurality of dummy blocks, and makes the dummy blocks perform filling operation according to the center position of the blank area, and then adjusts the layout density of the integrated circuit by replacing the dummy blocks. Therefore, the stopping and adjusting operation of the layout density of the integrated circuit is not needed to be executed in a manual mode, and the automatic execution of the stopping and adjusting operation can be realized, so that the efficiency of layout work is improved.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (12)
1. A layout method of an integrated circuit, comprising:
receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit;
presetting a plurality of virtual blocks, wherein the plurality of virtual blocks have different sizes;
selecting at least one of the plurality of virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information;
performing a layout density check on the updated layout information to obtain a check result; and
reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result and generating output layout information, comprising:
setting at least one of the adjacent virtual blocks in the plurality of virtual blocks in the integrated circuit as a set virtual block; when the inspection result indicates that the layout density of the integrated circuit is higher than a critical value, each of the plurality of set virtual blocks is replaced by a replacement virtual block,
the density of the replaced virtual blocks is smaller than that of the corresponding multiple set virtual blocks.
2. The layout method according to claim 1, wherein the step of selecting at least one of the plurality of virtual blocks to fill in the center position of each of the blank areas according to the size of each of the blank areas comprises:
generating a plurality of frames according to the edges of the virtual blocks; and
selecting at least one of the virtual blocks, and enabling the frame corresponding to the selected virtual block to perform filling action on the central position of each blank area.
3. The layout method according to claim 2, wherein the step of selecting at least one of the plurality of virtual blocks to perform the filling action on the center position of each of the blank areas according to the size of each of the blank areas further comprises:
and calculating N receivable numbers according to the size of each blank area and the size of the first frame, and filling N first frames into each blank area, wherein N is an integer not less than 0.
4. The layout method according to claim 3, wherein after the N first frames are filled into each of the blank areas, generating at least one sub-blank area, selecting at least one of the plurality of virtual blocks according to the size of each of the blank areas, so as to perform the filling action on the center position of each of the blank areas further comprises:
and calculating M receivable numbers according to the sizes of the sub-blank areas and the sizes of the second frames, and filling M second frames into the sub-blank areas, wherein M is an integer not smaller than 0.
5. The layout method of claim 4, wherein the first frame has a size that is larger than a size of the second frame.
6. The layout method of claim 4, wherein the step of reducing the size of the plurality of set virtual blocks in the integrated circuit according to the inspection result comprises:
the plurality of setting frames corresponding to the plurality of setting virtual blocks are replaced by a plurality of second frames respectively,
wherein the size of each of the set frames is larger than the size of each of the second frames.
7. The layout method according to claim 1, wherein the output layout information is provided as information for manufacturing the integrated circuit.
8. The layout method of claim 1, further comprising:
generating layout density distribution information of the integrated circuit according to the output layout information.
9. The layout method of claim 1, wherein each of the dummy blocks comprises a first density block.
10. The layout method of claim 9, wherein each of the dummy blocks further comprises a second density block, wherein the second density block is disposed at an edge of the first density block.
11. The layout method of claim 10, wherein each of the dummy blocks further comprises at least one third density block disposed in the second density block, the at least one third density block having the same density as the first density block.
12. An electronic device for performing layout actions of an integrated circuit, comprising:
the memory is used for storing layout information and information of a plurality of preset virtual blocks, wherein the plurality of virtual blocks have different sizes; and
a processor for:
receiving the layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit;
selecting at least one of the plurality of virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information;
performing a layout density check on the updated layout information to obtain a check result; and
reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result and generating output layout information, comprising:
setting at least one of the adjacent virtual blocks in the plurality of virtual blocks in the integrated circuit as a set virtual block; when the inspection result indicates that the layout density of the integrated circuit is higher than a critical value, each of the plurality of set virtual blocks is replaced by a replacement virtual block,
the density of the replaced virtual blocks is smaller than that of the corresponding multiple set virtual blocks.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004288685A (en) * | 2003-03-19 | 2004-10-14 | Nec Micro Systems Ltd | Method and program for designing layout of semiconductor integrated circuit |
| JP2006179816A (en) * | 2004-12-24 | 2006-07-06 | Sanyo Electric Co Ltd | Method for automatically designing semiconductor integrated circuit |
| JP2007027290A (en) * | 2005-07-14 | 2007-02-01 | Renesas Technology Corp | Method for designing layout of semiconductor integrated circuit |
| JP2007080942A (en) * | 2005-09-12 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Wiring modeling technique and formation method of dummy pattern |
| CN101158805A (en) * | 2006-10-06 | 2008-04-09 | 国际商业机器公司 | Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks |
| CN101178744A (en) * | 2006-11-06 | 2008-05-14 | 茂德科技股份有限公司（新加坡子公司） | Methods of automatically generating dummy fill having reduced storage size |
| JP2009182056A (en) * | 2008-01-29 | 2009-08-13 | Fujitsu Microelectronics Ltd | Design method, design device and program, for semiconductor device |
| JP2011049598A (en) * | 2010-11-30 | 2011-03-10 | Renesas Electronics Corp | Semiconductor device, and method of manufacturing the same |
| CN102169517A (en) * | 2010-02-25 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Method for adjusting local and global pattern density of an integrated circuit design |
| CN105631081A (en) * | 2014-11-27 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | FinFET virtual pattern insertion method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3806016B2 (en) * | 2000-11-30 | 2006-08-09 | 富士通株式会社 | Semiconductor integrated circuit |
| JP4307022B2 (en) * | 2002-07-05 | 2009-08-05 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device design method, semiconductor device design program, and semiconductor device design apparatus |
| FR2866963A1 (en) * | 2004-02-27 | 2005-09-02 | Bull Sa | Dummy surface inserting method for e.g. very large scale integrated circuit, involves processing circuit design by insertion of surface patterns based on insertion hierarchy estimating design hierarchy by processing blocks and units |
| JP2006344176A (en) * | 2005-06-10 | 2006-12-21 | Nec Electronics Corp | Macro arrangement design device with consideration given to density, program, and design method |
| US7801717B2 (en) * | 2007-01-22 | 2010-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for smart dummy insertion to reduce run time and dummy count |
-
2018
- 2018-11-14 CN CN201811353202.9A patent/CN111259613B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004288685A (en) * | 2003-03-19 | 2004-10-14 | Nec Micro Systems Ltd | Method and program for designing layout of semiconductor integrated circuit |
| JP2006179816A (en) * | 2004-12-24 | 2006-07-06 | Sanyo Electric Co Ltd | Method for automatically designing semiconductor integrated circuit |
| JP2007027290A (en) * | 2005-07-14 | 2007-02-01 | Renesas Technology Corp | Method for designing layout of semiconductor integrated circuit |
| JP2007080942A (en) * | 2005-09-12 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Wiring modeling technique and formation method of dummy pattern |
| CN101158805A (en) * | 2006-10-06 | 2008-04-09 | 国际商业机器公司 | Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks |
| CN101178744A (en) * | 2006-11-06 | 2008-05-14 | 茂德科技股份有限公司（新加坡子公司） | Methods of automatically generating dummy fill having reduced storage size |
| JP2009182056A (en) * | 2008-01-29 | 2009-08-13 | Fujitsu Microelectronics Ltd | Design method, design device and program, for semiconductor device |
| CN102169517A (en) * | 2010-02-25 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Method for adjusting local and global pattern density of an integrated circuit design |
| JP2011049598A (en) * | 2010-11-30 | 2011-03-10 | Renesas Electronics Corp | Semiconductor device, and method of manufacturing the same |
| CN105631081A (en) * | 2014-11-27 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | FinFET virtual pattern insertion method |
Non-Patent Citations (1)
| Title |
|---|
| 唐海霞 等.VLSI的电镀和化学机械抛光技术.合肥工业大学学报(自然科学版).2009,第32卷(第09期),第1378-1381页. * |
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