JP2011049598A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a dummy pattern for keeping flatness of a wiring layer, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device has a functional pattern required for achieving a function of a semiconductor device, and a plurality of dummy patterns in a prescribed layer of the semiconductor device together with the functional pattern. A plurality of dummy patterns of a first size are disposed and a plurality of dummy patterns of a second size are disposed in a region where a plurality of dummy patterns of the first size are not disposed. A plurality of dummy patterns of the second size are disposed between a plurality of dummy patterns of the first size and the functional pattern. A plurality of dummy patterns of the first size disposed in a first prescribed direction and a plurality of dummy patterns of the second size disposed in a second prescribed direction lie next to each other. The width between the dummy patterns of the first size is larger than the width between the dummy pattern of the second size. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a structure suitable for suppressing a step of a wiring layer and a manufacturing method thereof.

  FIG. 8 shows a cross-sectional view of a conventional semiconductor device 10. The semiconductor device 10 is a mixed device including a logic circuit and a DRAM (Dynamic Random Access Memory) on the same substrate. The semiconductor device 10 includes a silicon substrate 12. An isolation oxide film 14 formed by a shallow trench process is embedded in the silicon substrate 12.

  Formed on the silicon substrate 12 are a gate electrode 16 and sidewalls 18 that are components of a logic circuit, and a transfer gate (TG) 20 and sidewalls 22 that are components of a DRAM. A first interlayer film 24 made of BPSG is formed on the gate electrode 16 and the TG 20. The first interlayer film 24 is provided with a plurality of contact plugs 26 that are electrically connected to the active region of the DRAM.

  The contact plug 26 is formed by the following procedure. That is, in the step of forming the contact plug 26, first, a contact hole 28 opening in the active region of the DRAM is formed in the first interlayer film 24. Next, doped polysilicon is deposited so that the inside of the contact hole 28 is filled. Finally, CMP (Chemical Mechanical Polishing) is performed so that the upper surface of the first interlayer film 24 and the end surface of the contact plug 26 are flat.

  On the upper layer of the first interlayer film 24, a second interlayer film 30 made of TEOS is formed. The semiconductor device 10 includes a bit line 32 that passes through the second interlayer film 30 and is electrically connected to a part of the contact plug 26, and an active region of the logic circuit that passes through the first and second interlayer films 24 and 30. And a conductive metal wiring 34. The bit line 32 and the metal wiring 34 are formed by the following procedure. That is, in those forming steps, first, a contact hole 36 that penetrates the second interlayer film 24 and a contact hole 38 that penetrates the first and second interlayer films 24 and 30 are formed. Next, tungsten silicide (WSi) is deposited on the entire surface of the second interlayer film 30 so that the insides of the contact holes 36 and 38 are filled. Finally, the WSi is patterned into a desired shape by photolithography and etching.

  A third interlayer film 40 made of TEOS is formed on the second interlayer film 30. The semiconductor device 10 includes a storage node contact plug (SC plug) 42 that penetrates the second and third interlayer films 30 and 40 and is electrically connected to a part of the contact plug 26. The SC plug 42 is formed by the following procedure. That is, in the SC plug forming process, first, a contact hole 44 penetrating the second and third interlayer films 30 and 40 is formed. Next, doped polysilicon is deposited so that the inside of the contact hole 44 is filled. Finally, CMP is performed so that the upper surface of the third interlayer film 40 and the end surface of the SC plug 42 are flat.

  A fourth interlayer film 46 made of BPSG is formed on the third interlayer film 40. The fourth interlayer film 46 is provided with an opening 48 that communicates with the SC plug 42. The inner wall of the opening 48 and the surface of the SC plug 42 are covered with an insulating film 50. A cell plate 52 made of doped polysilicon is formed inside the space surrounded by the insulating film 50 and above the fourth interlayer film 46. The cell plate 52 is formed by the following procedure. That is, in the step of forming the cell plate 52, first, an opening 48 that penetrates the fourth interlayer film 46 is formed. Next, doped polysilicon is deposited on the entire surface of the fourth interlayer film 46 so that the inside of the opening 48 is filled. Finally, the doped polysilicon is patterned into a desired shape by photolithography and etching.

  In a hybrid device such as the semiconductor device 10, the cell plate 52 is formed only in the DRAM region. Therefore, when the cell plate 52 is formed, a step due to the film thickness of the cell plate 52 is generated between the DRAM region and the logic circuit region.

  A fifth interlayer film 54 is formed on the fourth interlayer film 46 so as to cover the cell plate 52. The semiconductor device 10 includes a plurality of metal wires 56 that are electrically connected to the cell plate 52 and the metal wires 34. In the step of forming the metal wiring 56, first, openings are provided in the fifth interlayer film 54 and the fourth interlayer film 46. Next, a barrier metal (TiN: 15 nm, etc.) and a wiring member (AlCu: 150 nm, etc.) are formed on the entire surface of the fifth interlayer film 54 so as to fill those openings. Finally, the laminated film is patterned into a desired shape by photolithography and etching. Thereafter, the above processing is repeated as necessary to form a multilayer wiring structure.

JP 05-152296 A

  A mixed device such as the semiconductor device 10 has a pattern formed only in one of the DRAM and the logic circuit, like the cell plate 52 described above. Therefore, in the upper layer of such a pattern, a step is generated between the DRAM region and the logic circuit region. When such a level difference occurs, the margin in photoengraving becomes small, and contact hole opening defects and wiring pattern accuracy deterioration tend to occur. In addition, when CMP is performed to reduce the level difference, there is a disadvantage that polishing is not uniform due to the unevenness of the surface to be polished.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor device having a dummy pattern for maintaining the flatness of a wiring layer and a method for manufacturing the same.

  The semiconductor device according to the invention of the present application is a semiconductor device having a multilayer wiring structure, and is formed with a functional pattern necessary for realizing the function of the semiconductor device and a predetermined layer of the semiconductor device together with the functional pattern. A plurality of dummy patterns, the plurality of dummy patterns is composed of a plurality of dummy patterns of a first size and a plurality of dummy patterns of a second size smaller than the first size, The plurality of dummy patterns of the first size are regularly arranged, and the plurality of dummy patterns of the second size are in areas where the plurality of dummy patterns of the first size are not regularly arranged. The plurality of dummy patterns arranged in a regular manner, the plurality of dummy patterns of the second size arranged between the plurality of dummy patterns of the first size and the functional pattern, and arranged in a first predetermined direction. One big Each of the plurality of dummy patterns arranged adjacent to each of the plurality of dummy patterns of the second size arranged in the second predetermined direction, and the width between the dummy patterns of the first size. Is larger than the width between the dummy patterns of the second size.

  According to the present invention, each layer included in the multilayer wiring structure is occupied with a high filling rate by the functional pattern and the plurality of types of dummy patterns. Therefore, according to the present invention, a semiconductor device in which each layer has excellent flatness can be realized.

It is sectional drawing of the semiconductor device of Embodiment 1 of this invention. It is a block diagram of the pattern design apparatus used in Embodiment 1 of this invention. FIG. 3 is a flowchart of a routine executed for designing a dummy pattern in the pattern design apparatus shown in FIG. 2. FIG. It is a figure showing the wiring pattern in the state by which one type of dummy pattern was produced | generated according to the routine shown in FIG. It is a figure showing the wiring pattern in the state by which two types of dummy patterns were produced | generated according to the routine shown in FIG. 3 is a flowchart of a routine that is executed in order to delete unnecessary portions of a dummy pattern in the pattern design apparatus shown in FIG. 2. It is a flowchart of the routine performed in order to design a dummy pattern in the pattern design apparatus used in Embodiment 2 of this invention. It is sectional drawing of the conventional semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element which is common in each figure, and the overlapping description is abbreviate | omitted.

Embodiment 1 FIG.
FIG. 1 is a sectional view of a semiconductor device 60 according to the first embodiment of the present invention. The semiconductor device 60 is a mixed device including a logic circuit and a DRAM (Dynamic Random Access Memory) on the same substrate. The semiconductor device 60 includes a silicon substrate 12. An isolation oxide film 14 formed by a shallow trench process is embedded in the silicon substrate 12.

  On the upper part of the silicon substrate 12, a gate electrode 16 and a side wall 18 which are components of a logic circuit, and a TG 20 and a side wall 22 which are components of a DRAM are formed. A first interlayer film 24 made of BPSG is formed on the gate electrode 16 and the TG 20. The first interlayer film 24 is provided with a plurality of contact plugs 26 that are electrically connected to the active region of the DRAM.

  The contact plug 26 is formed by the following procedure. That is, in the step of forming the contact plug 26, first, a contact hole 28 opening in the active region of the DRAM is formed in the first interlayer film 24. Next, doped polysilicon is deposited so that the inside of the contact hole 28 is filled. Finally, CMP is performed so that the upper surface of the first interlayer film 24 and the end surface of the contact plug 26 become flat.

  On the upper layer of the first interlayer film 24, a second interlayer film 30 made of TEOS is formed. The semiconductor device 60 includes a bit line 32 that passes through the second interlayer film 30 and is electrically connected to a part of the contact plug 26, and an active region of the logic circuit that passes through the first and second interlayer films 24 and 30. And a conductive metal wiring 34. The bit line 32 and the metal wiring 34 are formed by the following procedure. That is, in those forming steps, first, a contact hole 36 that penetrates the second interlayer film 24 and a contact hole 38 that penetrates the first and second interlayer films 24 and 30 are formed. Next, tungsten silicide (WSi) is deposited on the entire surface of the second interlayer film 30 so that the insides of the contact holes 36 and 38 are filled. Finally, the WSi is patterned into a desired shape by photolithography and etching.

  A third interlayer film 40 made of TEOS is formed on the second interlayer film 30. The semiconductor device 60 includes SC plugs 42 that penetrate through the second and third interlayer films 30 and are electrically connected to some of the contact plugs 26. The SC plug 42 is formed by the following procedure. That is, in the SC plug forming process, first, a contact hole 44 penetrating the second and third interlayer films 30 and 40 is formed. Next, doped polysilicon is deposited so that the inside of the contact hole 44 is filled. Finally, CMP is performed so that the upper surface of the third interlayer film 40 and the end surface of the SC plug 42 are flat.

  A fourth interlayer film 46 made of BPSG is formed on the third interlayer film 40. The fourth interlayer film 46 is provided with an opening 48 that communicates with the SC plug 42. The inner wall of the opening 48 and the surface of the SC plug 42 are covered with an insulating film 50. A cell plate 52 made of doped polysilicon is formed inside the space surrounded by the insulating film 50 and above the fourth interlayer film 46.

  In the present embodiment, a dummy pattern 62 made of the same material as the cell plate 52 (ie, doped polysilicon) is formed on the fourth interlayer film 46. The dummy pattern 62 is provided in the area of the logic circuit so as not to interfere with any of the other wiring members provided in the semiconductor device 10. In the present specification, the “dummy pattern” refers to a pattern that is unnecessary for securing the essential function of the semiconductor device 60. On the other hand, all the patterns necessary for the function of the semiconductor device 60 (including the bit line 32, the metal wiring 34, and the sidewalls 18 and 22) are hereinafter referred to as “functional patterns”.

  The cell plate 52 and the dummy pattern 62 are formed by the following procedure. That is, in those forming steps, first, an opening 48 penetrating the fourth interlayer film 46 is formed. Next, doped polysilicon is deposited on the entire surface of the fourth interlayer film 46 so that the inside of the opening 48 is filled. Finally, the doped polysilicon is patterned into a predesigned shape, that is, the shape of the cell plate 52 and the shape of the dummy pattern by photolithography and etching.

  In a hybrid device such as the semiconductor device 60, the cell plate 52 is formed only in the DRAM region. For this reason, when the dummy pattern 62 does not exist, a step is generated between the DRAM region and the logic circuit region by forming the cell plate 52. On the other hand, when the dummy pattern 64 is provided in the logic circuit area as in the present embodiment, it is possible to effectively prevent the above-described step from being generated in the DRAM area and the logic circuit area.

  A fifth interlayer film 54 is formed on the fourth interlayer film 46 so as to cover the cell plate 52 and the dummy pattern 62. The surface of the fifth interlayer film 54 is planarized by CMP. In the present embodiment, the lower layer of the fifth interlayer film 54 is flattened as described above. For this reason, the polishing characteristics of CMP for planarizing the fifth interlayer film 54 are substantially uniform over the entire surface. As a result, remarkably good flatness is ensured on the surface of the fifth interlayer film 54 as compared with the case where the dummy pattern 62 is not formed.

  The semiconductor device 60 includes a plurality of metal wires 56 that are electrically connected to the cell plate 52 and the metal wires 34. In the step of forming the metal wiring 56, first, openings are provided in the fifth interlayer film 54 and the fourth interlayer film 46. Next, a barrier metal (TiN: 15 nm, etc.) and a wiring member (AlCu: 150 nm, etc.) are formed on the entire surface of the fifth interlayer film 54 so as to fill those openings. Finally, the laminated film is patterned into a desired shape by photolithography and etching.

  Thereafter, the above processing is repeated as necessary to form a multilayer wiring structure. In FIG. 1, the dummy pattern 62 is generated only in the wiring layer including the cell plate 52, but the dummy pattern is not included only in this wiring layer. That is, the semiconductor device 60 has dummy patterns for improving the flatness in all wiring layers whose flatness deteriorates due to the influence of the functional pattern.

  Next, referring to FIG. 2 to FIG. 6, the features of dummy patterns (including dummy patterns 62) included in the semiconductor device 60 of this embodiment, the design method thereof, and the dummy patterns are automatically designed. A pattern design apparatus will be described.

  FIG. 2 is a block diagram of the pattern design apparatus 70 of the present embodiment. The pattern design apparatus 70 can be realized using a hardware configuration of a general computer system. That is, the pattern design device 70 includes a CPU 72, a ROM 74, and a RAM 76. Those components are connected to each other via a bus line 78. The bus line 78 is further connected to a recording control unit 80, an input control unit 82, a display interface (display I / F) 84, and the like.

  The recording control unit 80 is a device that reads data from a recording medium 86 such as a hard disk or a CD-ROM, or writes data to the recording medium 86. The input control unit 82 is a device that outputs an input signal from an input device 88 such as a keyboard or a mouse to the bus line 78. The display I / F 84 is an interface that generates an image to be displayed on the display 90.

  In the pattern design device 70, the CPU 72 designs a dummy pattern or the like by executing processing to be described later using a program or data loaded from the recording medium 86 to the RAM 76. Hereinafter, a procedure in which the pattern design apparatus 70 designs a pattern including a dummy pattern will be described.

  FIG. 3 shows a flowchart of a first routine executed for generating a dummy pattern in the pattern design apparatus 70. The routine shown in FIG. 3 is executed after the design of the function pattern included in each wiring layer is completed. In the design process of the semiconductor device 60 shown in FIG. 1, for example, after the design of the cell plate 52 to be formed on the fourth interlayer film 46 is completed, the routine shown in FIG. 3 is executed.

  In step 100, the size of the space to be extracted as an area for placing a dummy pattern is set from among the empty areas (areas not occupied by the functional pattern) included in the layer to be processed. Hereinafter, such a space is referred to as a “search space”. In this step, for example, the size of the search space is set such as “a square region having a side of 10 μm”.

  In step 102, the size of the dummy pattern corresponding to the size of the search space set as described above is set. In this step, for example, “a square area having a side of 7 μm” is set as the size of the dummy pattern for a search space having a side of 10 μm.

  In step 104, processing for extracting the search space set in step 100 is executed from the free areas included in the wiring layer to be processed. In step 106, processing for generating the dummy pattern set in step 102 is performed in the extracted search space.

  FIG. 4 shows an example of a wiring pattern designed by the series of processes described above. In FIG. 4, a pattern denoted by reference numeral 92 is a functional pattern of the semiconductor device 60. An area denoted by reference numeral 94 is an empty area with a side of 10 μm. Further, a pattern denoted by reference numeral 96 is a dummy pattern set by the processing of step 106 described above. As shown in FIG. 4, according to the pattern design method of the present embodiment, a plurality of dummy patterns 96 having the same size and shape can be regularly arranged in the vacant area of the wiring layer.

  In step 108, it is determined whether or not a dummy pattern generation end condition is satisfied. In the present embodiment, for example, when the size of the dummy pattern generated in step 106 is equal to or smaller than a predetermined size, or the pattern filling rate in the wiring layer to be processed (the function pattern and the dummy pattern are , The proportion in the wiring layer) is equal to or greater than a predetermined value, it is determined that the dummy pattern generation end condition is satisfied. As a result of the above determination, if it is determined that the end condition has not yet been established, the processing after step 100 is executed again. On the other hand, if it is determined that the end condition has already been satisfied, the current processing cycle is ended.

  When the process in step 100 is executed again, the size of the search space is changed to a size smaller than the size set during the previous processing cycle. For example, the search space set as “a square area with a side of 10 μm” during the first processing cycle is changed to a “square area with a side of 4 μm” during the second processing cycle.

  When the process of step 102 is executed again, the size of the dummy pattern is also changed. For example, a dummy pattern that is set as “a square area with a side of 7 μm” during the first processing cycle is changed to a “square area with a side of 3 μm” in accordance with the search space with a side of 4 μm during the second processing cycle. Is done.

  FIG. 5 shows an example of a wiring pattern designed by executing steps 104 and 106 after the search space and the dummy pattern are set as described above. In FIG. 5, an area denoted by reference numeral 97 is an empty area having a side of 4 μm. A pattern denoted by reference numeral 98 is a dummy pattern having a side of 3 μm. As shown in FIG. 5, according to the method described above, a plurality of dummy patterns 98 having the same size and shape can be regularly arranged in the empty area where the dummy patterns 96 could not be arranged.

  By disposing the small dummy pattern 98 in the empty area where the large dummy pattern 96 cannot be disposed, the pattern filling rate in the wiring layer can be further increased. When the pattern filling rate is increased, the pattern density on the entire surface of the wiring layer can be made uniform regardless of the distribution of the functional pattern. Furthermore, in the method of this embodiment, the pattern filling rate is improved by regularly arranging a plurality of dummy patterns having the same size and shape.

  When polishing the interlayer film formed on the wiring layer by CMP, the pattern filling rate of the wiring layer is high in order to prevent the CMP pattern dependence from appearing, and the pattern distribution is It is desirable to be uniform over the entire surface. According to the method of the present embodiment, by arranging a plurality of types of dummy patterns regularly, those requirements can be satisfied effectively. Therefore, according to the method of the present embodiment, each layer included in the multilayer wiring structure is superior to the case where the dummy pattern is not formed or the case where the dummy pattern is only designed according to a single rule. Flatness can be given.

  FIG. 6 shows a flowchart of a routine executed in the pattern design apparatus 70 to delete a part of the dummy pattern. The routine shown in FIG. 6 is executed after the design of the dummy pattern included in each wiring layer is completed. More specifically, it is executed after the routine shown in FIG. 3 is completed for the wiring layer to be processed.

  In step 110, a pattern penetrating the wiring layer to be processed is read. In this step, for example, a pattern such as the metal wiring 56 shown in FIG. 1 is read. Hereinafter, the pattern read by the above processing is referred to as a “penetration pattern”.

  In step 112, an area that may interfere with the penetrating pattern (hereinafter referred to as “interference area”) is searched among the designed dummy patterns. In the present embodiment, an area obtained by adding a process margin in consideration of photolithography deviation to the size of the penetrating pattern is set as an interference area.

  In step 114, a process of deleting the interference area from the designed dummy pattern is performed. By executing the above processing, a dummy pattern that does not interfere with a wiring member such as the metal wiring 56 is designed like the dummy pattern 62 shown in FIG. When the above-described series of processing ends, the current processing cycle ends.

  As described above, according to the pattern design apparatus 70 of the present embodiment, a dummy pattern that does not interfere with other wiring members and that is effective in preventing CMP pattern dependency is designed in each wiring layer. be able to. By using such a dummy pattern, it is possible to accurately form each wiring layer without affecting the function of the semiconductor device 60. For this reason, according to the present embodiment, it is possible to realize the semiconductor device 60 having stable quality and capable of being manufactured with a high yield.

Embodiment 2. FIG.
Next, a pattern design apparatus according to the second embodiment of the present invention will be described with reference to FIG. The pattern design apparatus of the present embodiment can be realized by causing the apparatus having the configuration shown in FIG. 2 to execute the routine shown in FIG.

  When the semiconductor device is sufficiently miniaturized, the etching process window, that is, the range of etching conditions that can obtain appropriate processing accuracy, changes according to the aperture ratio of the mask used during photolithography. To do. Table 1 shows a process window for etching to open the contact hole 28 shown in FIG. In Table 1, “OK” indicates that the contact hole can be properly opened without causing an etching residue. The results shown in Table 1 indicate that contact hole opening defects are more likely to occur as the mask opening ratio decreases, and that contact hole opening defects are more likely to occur as the etching chamber is used longer. .

  For mixed devices such as the semiconductor device 60, it is rare that a dedicated production line is laid for each product. In other words, an embedded device such as the semiconductor device 60 is generally produced on a general-purpose production line, that is, a line for producing a plurality of products, from the viewpoint of production efficiency.

  The ratio of the logic circuit and DRAM in the embedded device varies greatly depending on the product specifications and the like. Furthermore, the ratio of the functional pattern included in the logic circuit or DRAM to the individual wiring layers also varies greatly depending on the product specifications and the like. For this reason, the aperture ratio of the mask for transferring the functional pattern of the embedded device varies greatly depending on the product specifications.

  In a general-purpose production line, a plurality of wiring layers having process windows that do not overlap may be subject to etching. In this case, if the etching conditions are always constant, the etching conditions for some of the wiring layers are outside the process window, and the functional pattern of the wiring layers is likely to be defective. Such a defective functional pattern can be prevented, for example, by changing the etching conditions in accordance with the aperture ratio of the mask used for each wiring layer. However, according to the above method, it is necessary to check the condition every time a change in the etching condition is required, and the productivity of the embedded device deteriorates.

  The aperture ratio of the mask for transferring the functional pattern of the mixed device can be increased by providing a dummy pattern in addition to the functional pattern. Therefore, by appropriately providing dummy patterns in individual wiring layers, the mask opening ratios for a plurality of wiring layers are matched, and the etching process window for all products to be processed in a general-purpose production line is matched. Can do. When the process windows for all products are matched, it is possible to properly etch the functional patterns of all products while keeping the etching conditions constant. Therefore, according to such a method, it is possible to efficiently produce a plurality of mixed devices on a single general-purpose line.

  FIG. 7 shows a flowchart of a routine executed by the pattern design apparatus of the present embodiment to design a wiring pattern by the above method. The routine shown in FIG. 7 is executed after the functional pattern of the wiring layer is designed for all the wiring layers in which the pattern is formed by etching.

  In step 116, a target mask aperture ratio is set. The target aperture ratio is a value commonly used for all wiring layers processed on the same general-purpose line.

  In step 118, a vacant area where a dummy pattern is to be generated is searched from vacant areas included in the wiring layer to be processed.

  In step 120, the size and arrangement of dummy patterns to be generated in the empty area are set. In this step, the size and arrangement of the functional pattern included in the wiring layer to be processed are set as the size and arrangement of the dummy pattern. More specifically, for example, when an empty area is found in the area of the logic circuit, the size and arrangement of the functional pattern on the DRAM area are set as the size and arrangement of the dummy pattern.

  When the size and arrangement of the dummy patterns are set as described above, the sizes and arrangements of all patterns included in the same wiring layer can be unified. Further, since the reliability and the like of the function pattern is confirmed, if the dummy pattern is designed following the function pattern as described above, it is possible to indirectly guarantee the reliability of the dummy pattern.

  In step 122, processing for generating a dummy pattern set as described above is performed in the searched empty space. When the above processing ends, the current processing cycle ends.

  According to the above processing, a dummy pattern similar to the functional pattern included in the layer can be generated in the empty area of the wiring layer. Even when the functional pattern alone has a low mask aperture ratio (for example, 8% or less in Table 1), if the dummy pattern is generated by the above method, the mask aperture ratio can be set to a sufficiently large value. it can. Therefore, according to the pattern design method of this embodiment, the process windows of all the wiring layers included in a plurality of products can be overlapped to increase the productivity of the mixed device.

  In the second embodiment, only one type of dummy pattern is formed in the empty area. However, the present invention is not limited to this, and a plurality of types of dummy patterns can be obtained using the method of the first embodiment. A pattern may be provided. When a plurality of types of dummy patterns are provided, the filling rate of the wiring pattern can be increased, the mask aperture ratio can be increased, and the flatness of the wiring layer can be improved.

  In the first and second embodiments described above, the DRAM and the logic circuit are mounted on the embedded device. However, the present invention is not limited to this, and the embedded device is replaced with the DRAM. Alternatively, an SRAM may be mounted together with the DRAM.

12 silicon substrate, 16 gate electrode, 18, 22 sidewall, 20 transfer gate, 24 first interlayer film, 26 contact plug, 30 second interlayer film, 32 bit line, 34,56 metal wiring, 40 third Interlayer film, 46 4th interlayer film, 50 insulating film, 52 cell plate, 54 5th interlayer film, 60 semiconductor device, 62, 96, 98 dummy pattern, 70 pattern design device, 92 function pattern, 94, 97 empty region.

Claims (24)

A semiconductor device having a multilayer wiring structure,
Functional patterns necessary for realizing the functions of semiconductor devices,
A plurality of dummy patterns formed together with the functional pattern in a predetermined layer of the semiconductor device,
The plurality of dummy patterns includes a plurality of dummy patterns having a first size and a plurality of dummy patterns having a second size smaller than the first size,
The plurality of dummy patterns of the first size are regularly arranged,
In the region where the plurality of dummy patterns of the first size are not regularly arranged, the plurality of dummy patterns of the second size are regularly arranged,
A plurality of dummy patterns of the second size are arranged between the plurality of dummy patterns of the first size and the functional pattern;
Each of the plurality of dummy patterns of the first size arranged in the first predetermined direction and each of the plurality of dummy patterns of the second size arranged in the second predetermined direction are arranged adjacent to each other. ,
2. A semiconductor device according to claim 1, wherein a width between the first-size dummy patterns is larger than a width between the second-size dummy patterns. The functional pattern includes a wiring member penetrating at least one wiring layer,
2. The semiconductor device according to claim 1, wherein the dummy pattern is formed so as not to interfere with the wiring member. A memory area in which a functional pattern as a component of the memory device is formed;
A logic circuit area in which a functional pattern as a component of the logic circuit is formed,
3. The semiconductor device according to claim 2, wherein the dummy pattern formed in the logic circuit region includes the same pattern as a functional pattern for a memory circuit formed in the same layer as the dummy pattern. The dummy pattern of the first size is a quadrangle whose one side in the first direction has a first length and whose one side in the second direction different from the first direction has a second length,
The dummy pattern of the second size is a quadrangle whose one side in the third direction is a third length and whose one side in the fourth direction different from the third direction is a fourth length,
The semiconductor device according to claim 1, wherein the first length is longer than the third length, and the second length is longer than the fourth length.   The first predetermined direction is the second predetermined direction, the first direction is the same as the third direction, the second direction is the same as the fourth direction, and the first length The semiconductor device according to claim 4, wherein the length is the same as the second length, and the third length is the same as the fourth length. The predetermined layer is a layer formed on an interlayer insulating film covering the gate electrode,
2. The semiconductor device according to claim 1, wherein each of the plurality of dummy patterns having the first size has the same shape, and each of the plurality of dummy patterns having the second size has the same shape. There are a plurality of the functional patterns,
Each of the plurality of dummy patterns of the first size arranged in the first predetermined direction is arranged adjacent to a part of the plurality of functional patterns,
The plurality of dummy patterns of the second size arranged in the second predetermined direction are arranged so as to be adjacent to other parts of the plurality of functional patterns. Semiconductor device. A semiconductor device having a multilayer wiring structure,
Functional patterns necessary for realizing the functions of semiconductor devices,
A plurality of dummy patterns formed together with the functional pattern in a predetermined layer of the semiconductor device,
The plurality of dummy patterns includes a plurality of dummy patterns having a first area and a plurality of dummy patterns having a second area smaller than the first area.
The plurality of dummy patterns of the first area are regularly arranged in the first region,
The plurality of dummy patterns of the second area are regularly arranged in the second region,
The second region is provided between the functional pattern and the first region;
Each of the plurality of dummy patterns of the first area in the first region and each of the plurality of dummy patterns of the second area in the second region are arranged adjacent to each other,
The distance between the dummy patterns of the first area is larger than the distance between the dummy patterns of the second area. The dummy pattern of the first area is a quadrangle whose one side in the first direction is the first length and whose one side in the second direction different from the first direction is the second length,
The dummy pattern of the second area is a quadrangle whose one side in the third direction is a third length, and whose one side in the fourth direction different from the third direction is a fourth length,
9. The semiconductor device according to claim 8, wherein the first length is longer than the third length, and the second length is longer than the fourth length.   The first direction is the same as the third direction, the second direction is the same as the fourth direction, the first length is the same as the second length, The semiconductor device according to claim 9, wherein the third length is the same as the fourth length. The predetermined layer is a layer formed on an interlayer insulating film covering the gate electrode,
9. The semiconductor device according to claim 8, wherein each of the plurality of dummy patterns having the first area has the same shape, and each of the plurality of dummy patterns having the second area has the same shape. There are a plurality of the functional patterns,
Each of the plurality of dummy patterns of the first area in the first region is disposed adjacent to a part of the plurality of functional patterns,
9. The semiconductor device according to claim 8, wherein each of the plurality of dummy patterns of the second area in the second region is disposed adjacent to another part of the plurality of functional patterns. . A semiconductor device having a multilayer wiring structure,
Functional patterns necessary for realizing the functions of semiconductor devices,
A plurality of dummy patterns formed together with the functional pattern in a predetermined layer of the semiconductor device,
When viewed in plan, the plurality of dummy patterns include a plurality of first dummy patterns each having a first size region, and a second size region that is smaller than the first size. A plurality of second dummy patterns having
The plurality of first dummy patterns are regularly arranged,
In a region where the plurality of first dummy patterns are not regularly arranged, the plurality of second dummy patterns are regularly arranged,
The plurality of second dummy patterns are disposed between the plurality of first dummy patterns and the functional pattern,
Each of the plurality of first dummy patterns arranged in the first predetermined direction and each of the plurality of second dummy patterns arranged in the second predetermined direction are arranged adjacent to each other,
The distance between said 1st dummy patterns is larger than the distance between said 2nd dummy patterns, The semiconductor device characterized by the above-mentioned. In the first dummy pattern, one side in a first direction is a first length, and one side in a second direction different from the first direction is a quadrangle having a second length,
The second dummy pattern is a quadrangle whose one side in the third direction is a third length and whose one side in the fourth direction different from the third direction is a fourth length;
14. The semiconductor device according to claim 13, wherein the first length is longer than the third length, and the second length is longer than the fourth length.   The first predetermined direction is the second predetermined direction, the first direction is the same as the third direction, the second direction is the same as the fourth direction, and the first direction 15. The semiconductor device according to claim 14, wherein a length is the same as the second length, and the third length is the same as the fourth length. The predetermined layer is a layer formed on an interlayer insulating film covering the gate electrode,
14. The semiconductor device according to claim 13, wherein the first dummy patterns have the same shape, and the second dummy patterns have the same shape. There are a plurality of the functional patterns,
Each of the plurality of first dummy patterns arranged in the first predetermined direction is arranged to be adjacent to a part of the plurality of functional patterns,
The semiconductor device according to claim 13, wherein each of the plurality of second dummy patterns arranged in the second predetermined direction is arranged adjacent to another part of the plurality of functional patterns. Forming a plurality of transistors;
A method of manufacturing a semiconductor device, comprising: forming a functional pattern necessary for realizing a function of the semiconductor device on the layer where the plurality of transistors are formed; and a plurality of dummy patterns.
The plurality of dummy patterns includes a plurality of dummy patterns having a first area and a plurality of dummy patterns having a second area smaller than the first area.
A plurality of dummy patterns of the first area are regularly arranged,
In the region where the plurality of dummy patterns of the first area are not regularly arranged, the plurality of dummy patterns of the second area are regularly arranged,
The distance between the plurality of dummy patterns of the first area is greater than the distance between the plurality of dummy patterns of the second area,
A plurality of dummy patterns of the second area are arranged between the plurality of dummy patterns of the first area and the functional pattern;
Each of the plurality of dummy patterns having the first area arranged in the first predetermined direction and each of the plurality of dummy patterns having the second area arranged in the second predetermined direction are arranged adjacent to each other. A method for manufacturing a semiconductor device. The functional pattern includes a wiring member penetrating at least one wiring layer,
19. The method of manufacturing a semiconductor device according to claim 18, wherein the dummy pattern is formed so as not to interfere with the wiring member. A memory region in which a functional pattern serving as a component of the memory device is formed; and a logic circuit region in which a functional pattern serving as a component of the logic circuit is formed,
19. The method of manufacturing a semiconductor device according to claim 18, wherein the dummy pattern formed in the logic circuit region includes the same pattern as a functional pattern for a memory circuit formed in the same layer as the dummy pattern. The dummy pattern of the first area is a quadrangle whose one side in the first direction is the first length and whose one side in the second direction different from the first direction is the second length,
The dummy pattern of the second area is a quadrangle whose one side in the third direction is a third length, and whose one side in the fourth direction different from the third direction is a fourth length,
19. The method of manufacturing a semiconductor device according to claim 18, wherein the first length is longer than the third length, and the second length is longer than the fourth length.   The first predetermined direction is the second predetermined direction, the first direction is the same as the third direction, the second direction is the same as the fourth direction, and the first length 22. The method of manufacturing a semiconductor device according to claim 21, wherein the length is the same as the second length, and the third length is the same as the fourth length.   19. The method of manufacturing a semiconductor device according to claim 18, wherein each of the plurality of dummy patterns having the first area has the same shape, and each of the plurality of dummy patterns having the second area has the same shape. A plurality of the functional patterns exist,
Each of the plurality of dummy patterns of the first area arranged in the first predetermined direction is arranged adjacent to a part of the plurality of functional patterns,
24. Each of the plurality of dummy patterns having the second area arranged in the second predetermined direction is arranged adjacent to another part of the plurality of functional patterns. Semiconductor device.

Images