JP4996972B2 - Mask data generation method and mask data generation system - Google Patents

Description

  The present invention relates to a mask data generation method and mask data generation system used in lithography.

  Conventionally, when patterning a semiconductor device using mask data, there is a problem that optical characteristics deteriorate due to an adjacent effect or the like, resulting in poor resolution. This may cause defects such as an increase in constriction, deterioration in dimensional variation, and shape abnormality such as wiring short-circuit. Therefore, an OPC correction technique (optical proximity correction (OPC)) that corrects mask data in consideration of such a proximity effect of light is known.

  Japanese Patent Laid-Open No. 2002-328457 discloses a step of receiving design layout data of a pattern designed by an automatic layout apparatus, and each of correction target cells included in the received design layout data. A step of determining an environment profile to be expressed in a specific format based on whether or not another figure exists, and referring to the cell replacement table, the name of the correction pattern to be replaced corresponding to the determined environment profile A pattern correction method including reading a replacement cell name and generating corrected layout data and fetching a correction pattern corresponding to the read replacement cell name from a cell library is described. In this document, an optimum sub-cell pattern after OPC correction corresponding to each environmental profile is created in advance using a lithography simulator or the like, and registered in advance in a via cell library for OPC correction. Then, by determining the environmental profile of the target via in the design layout data and substituting the name of the subcell according to the environmental profile, the data for masking is developed into the corresponding graphic data stored in the via cell library. It is to be created.

Patent Document 2 (Japanese Patent Application Laid-Open No. 2001-13669) extracts a pattern layout of a part of input data having a design grid (G0) in a mask drawing data creation method used in lithography. A mask drawing data generation method is described which includes a step of converting the pattern layout of the region to G1 larger than G0 and a step of pattern matching the pattern layout defined by G1. Thus, it is said that pattern matching efficiency can be improved by performing pattern matching after converting the grid of input data into a large grid.
JP 2002-328457 A Japanese Patent Laid-Open No. 2001-13669

  However, in the technique described in Patent Document 1, since the sub-cell pattern after OPC correction corresponding to each environment profile is created in advance, even if the same pattern is used, if the surrounding environment is different, the environment is different for each environment. Different subcell patterns need to be prepared, and a huge number of patterns need to be prepared.

  By the way, in a device in which a memory unit and a logic unit such as SRAM are mixedly mounted, the design rule of the SRAM is smaller than that of the logic unit. As described above, devices having layouts with different design rules require different OPC corrections. On the other hand, in order to perform OPC correction efficiently, it is preferable to perform OPC correction processing on the entire device at once. However, if OPC correction is performed collectively on devices having layouts with different design rules, there is a problem that the rules become complicated and the processing time increases.

According to the present invention,
A method for generating mask data used in lithography,
Obtaining design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule;
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout has a desired shape. Obtaining pre-OPC correction data corresponding to the second layout prepared in advance;
Generating intermediate data by replacing the second layout of the design layout data with the pre-OPC correction data;
Performing OPC correction of the intermediate data according to the first OPC correction rule;
Only including,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
The intermediate data prior to the step of generating a step further including mask data generation method for converting a grid size of the design layout data to the second grid size is provided.

According to the present invention,
A system for generating mask data used in lithography,
A layout data acquisition unit that acquires design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule. When,
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout becomes a desired shape. A pre-OPC correction data storage unit for storing pre-OPC correction data prepared in advance,
An intermediate data generation unit that generates intermediate data for the second layout of the design layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit;
An OPC correction processing unit that performs OPC correction of the intermediate data according to the first OPC correction rule;
Only including,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
The mask data generation system further includes a grid conversion processing unit that converts the grid size of the design layout data acquired by the layout data acquisition unit into the second grid size,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. A mask data generation system for generating is provided.
Moreover, according to the present invention,
A system for generating mask data used in lithography,
A layout data acquisition unit that acquires design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule. When,
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout becomes a desired shape. A pre-OPC correction data storage unit for storing pre-OPC correction data prepared in advance,
An intermediate data generation unit that generates intermediate data for the second layout of the design layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit;
An OPC correction processing unit that performs OPC correction of the intermediate data according to the first OPC correction rule;
Including
A storage unit for storing a grid size in which the pre-OPC correction data corresponding to the second layout is drawn;
It is determined whether or not the grid size of the design layout data is different from the grid size stored in the storage unit. If the grid size is different, the grid size of the design layout data is converted to the grid size stored in the storage unit. A grid conversion processing unit,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. A mask data generation system for generating is provided.

  According to such a configuration, even when the first layout and the second layout having different design rules are included, the OPC correction set corresponding to the first layout after the second layout is corrected in advance. Therefore, the second layout can also have a desired shape, and OPC correction can be performed collectively to generate mask data efficiently and accurately. Here, the second layout can be designed with a small design rule and include a large number of repeated patterns. The second layout can be a memory unit such as SRAM or DRAM.

  According to the present invention, even when layouts having different design rules are included, OPC correction can be performed collectively and mask data can be generated efficiently and accurately.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  In the present embodiment, an example of generating mask data used in lithography when manufacturing a device in which a logic unit (first layout) and an SRAM unit (second layout) having different design rules are mounted together. explain. Here, the design rule of the SRAM part is smaller than the design rule of the logic part. The OPC correction is performed collectively for the entire device using the OPC correction rule corresponding to the logic part having a large design rule. In this case, since the design rule of the SRAM unit is different from that of the logic unit, the layout of the SRAM unit does not have a desired shape if it is left as it is. In this embodiment, pre-OPC correction data for the SRAM unit is prepared in advance so that the SRAM unit has a desired shape when the same OPC correction rule as that for the logic unit is applied to the SRAM unit. Before the OPC correction, only the SRAM portion layout is replaced with the pre-OPC correction data to generate intermediate data. As a result, the layout of the SRAM portion can also be set to a desired shape, and OPC correction can be performed collectively to generate mask data efficiently and accurately.

FIG. 1 is a flowchart showing a procedure of a mask data generation method according to the present embodiment.
First, pre-OPC correction data corresponding to the SRAM unit layout is prepared in advance (S100). The pre-OPC correction data can be created on a one-to-one basis for a specific component cell such as an SRAM bit cell in the layout data. A specific example of the pre-OPC correction data will be described later. The pre-OPC correction data corresponding to each specific part cell is stored in association with the cell name of each specific part cell.

  In the present embodiment, the pre-OPC correction data is based on the shape in the case where the OPC correction rule corresponding to the logic portion is actually applied to the layout of the SRAM portion, and the OPC correction rule corresponding to the logic portion. When the OPC correction is performed, the SRAM portion is generated by correcting in a direction in which the layout of the SRAM portion becomes a desired shape. Further, the pre-OPC correction data can be prepared for each apparatus that performs lithography, for each apparatus installation location, for example. In this way, correction can be performed in accordance with the characteristics peculiar to the device and the place, and the layout can be made into a desired shape.

  In the present embodiment, the grid size of the pre-OPC correction data can be made smaller than the grid size of the design layout data. As a result, the shape of the pre-OPC correction data can be designed more finely, so that the layout of the SRAM portion can be made to have a desired shape with higher accuracy. In this case, before the design layout data is replaced with the pre-OPC correction data, the grid size of the design layout data needs to be reduced in the same manner as the grid size of the pre-OPC correction data. For example, if the grid size of the design layout data is 1 nm and the grid size of the pre-OPC correction data is 0.25 nm, before replacing the layout of the SRAM portion of the design layout data with the pre-OPC correction data, It is necessary to convert the grid size from 1 nm to 0.25 nm. Thereafter, the layout of the SRAM portion is replaced with the corresponding pre-OPC correction data.

  FIG. 2A is a schematic diagram illustrating an example of design layout data. The design layout data 200a includes an SRAM unit design layout 202a and a logic unit design layout 204a. Here, the SRAM unit design layout 202a and the logic unit design layout 204a have different design rules. For example, the SRAM part design layout 202a may have a minimum wiring width / interval design rule of 90 nm / 90 nm, and the logic part design layout 204a may have a minimum wiring width / interval design rule of 100 nm / 100 nm. . Thus, the design rule of the SRAM part is smaller than the design rule of the logic part. Here, the SRAM unit design layout 202a and the logic unit design layout 204a can each have a grid size of 1 nm.

  Returning to FIG. 1, when the design layout data is acquired (YES in S102), it is determined whether or not the grid size needs to be converted (S104). If the grid size needs to be converted (YES in S104), the grid size is changed. Conversion is performed (S106). Whether or not the grid size needs to be converted is determined by whether or not the grid size of the pre-OPC correction data is different from the grid size of the design layout data. That is, when the grid size of the pre-OPC correction data is different from the grid size of the design layout data, the grid size of the design layout data is converted so that the grid size of the design layout data matches the grid size of the pre-OPC correction data. However, if the grid size of the pre-OPC correction data is originally the same as the grid size of the design layout data, conversion of the grid size is not necessary. The grid size of pre-OPC correction data may be smaller than the grid size of design layout data as a standard, and the grid size may always be converted. The grid size of pre-OPC correction data may be set to the grid of design layout data. It is possible to set the same size as the standard so that grid size conversion is not always required. In this case, the determination step of step S104 can be omitted.

  2B shows a grid replacement layout including an SRAM part grid replacement layout 202b and a logic part grid replacement layout 204b in which the respective grid sizes of the SRAM part design layout 202a and the logic part design layout 204a of FIG. 2A are reduced. It is a schematic diagram which shows an example of the data 200b.

  FIG. 3A shows an example of the SRAM unit design layout 202a, and FIG. 3B shows an example of the SRAM unit grid replacement layout 202b in which the grid size of the SRAM unit design layout 202a is reduced. Here, as an example, it is assumed that the SRAM unit design layout 202a has a grid size of 1 nm and the SRAM unit grid replacement layout 202b has a grid size of 0.25 nm. In the figure, the dashed lines indicate grid lines. In this case, the data of one pixel in the SRAM unit design layout 202a shown in FIG. 3A becomes data of 16 pixels in the SRAM unit grid replacement layout 202b shown in FIG. That is, the SRAM part grid replacement layout 202b is obtained by increasing the resolution of the SRAM part design layout 202a.

  Returning to FIG. 1, intermediate data is generated by replacing the layout of the SRAM portion with the corresponding pre-OPC correction data (S108). Each specific part cell included in the layout of the SRAM portion is replaced with the corresponding pre-OPC correction data based on the cell name.

  FIG. 2C is a schematic diagram showing an example of intermediate data 200c obtained by replacing the SRAM section grid replacement layout 202b of FIG. 2B with the corresponding SRAM section pre-OPC correction data 202c. Here, the logic part grid replacement layout 204b remains as it is.

  FIG. 4 is a diagram illustrating an example of the SRAM part grid replacement layout 202b. Here, the SRAM portion grid replacement layout 202b includes a bit cell 208b and a bit cell 210b, and an array termination cell 206b provided around them. Here, the bit cell 208b is provided adjacent to the array termination cell 206b, and the bit cell 210b is surrounded by other bit cells.

  FIG. 5A is a pattern schematic diagram showing an example of the bit cell 208b. FIG. 5B is a schematic pattern diagram illustrating an example of pre-OPC correction data 208c corresponding to the bit cell 208b illustrated in FIG. FIG. 6A is a schematic pattern diagram showing an example of the array termination cell 206b. FIG. 6B is a schematic pattern diagram showing an example of pre-OPC correction data 206c corresponding to the array termination cell 206b shown in FIG.

  Returning to FIG. 1, thereafter, OPC correction processing is performed according to the OPC correction rule corresponding to the logic unit (S110). In this embodiment, since OPC correction is performed collectively after generating intermediate data, even if the environment around the target cell is different, a slight difference can be adjusted by the OPC correction program. Therefore, it is possible to save the trouble of preparing a plurality of pre-OPC correction data even when the environment around the target cell is different. That is, for example, when the bit cell 208b and the bit cell 210b have different surrounding environments but have the same layout specified by the same cell name, the bit cell 208b and the bit cell 210b are replaced with the same pre-OPC correction data (for example, pre-OPC correction data 208c). can do. Even in this case, the difference in the environment around the pre-OPC correction data 208c can be adjusted by the subsequent OPC correction program, and the layout can have a desired shape.

FIG. 7 is a block diagram showing a configuration of a mask data generation system 100 that executes the procedure described with reference to FIG.
The mask data generation system 100 includes a layout data acquisition unit 102, a grid conversion processing unit 104, an intermediate data generation processing unit 106, an OPC correction processing unit 108, a cell replacement table 110, and a pre-OPC correction data storage unit 112.

  Each component of the mask data generation system 100 shown in FIG. 7 is not a hardware unit configuration but a functional unit block. Each component of the mask data generation system 100 includes an arbitrary computer CPU, memory, a program for realizing the components shown in the figure loaded in the memory, a storage unit such as a hard disk for storing the program, and a network connection interface. It is realized by any combination of hardware and software. It will be understood by those skilled in the art that there are various modifications to the implementation method and apparatus.

  The layout data acquisition unit 102 includes a logic unit (first layout) designed with the first design rule and an SRAM unit (second layout) designed with a second design rule smaller than the first design rule. ) Including design layout data. In the present embodiment, the design layout data is designed by, for example, a manufacturer's design department. The mask data generation system 100 is installed, for example, in a department that undertakes mask data generation, for example, which actually performs lithography. Here, the design layout data is assigned a cell name for each specific part cell, and the layout data acquisition unit 102 also acquires these cell names in association with each other. The layout data acquisition unit 102 also acquires information indicating the grid size on which the design layout data is drawn.

  The grid conversion processing unit 104 converts the grid size of the design layout data acquired by the layout data acquisition unit 102. For example, when the design layout data is drawn with the first grid size and the pre-OPC correction data is drawn with the second grid size, the grid conversion processing unit 104 sets the grid size of the design layout data to the first grid size. Convert from size to second grid size.

  The pre-OPC correction data storage unit 112 displays the second layout when the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule. Pre-OPC correction data prepared in advance so as to have a desired shape is stored. The cell replacement table 110 stores the cell name of each specific part cell and the cell name of the data before OPC correction in association with each other. FIG. 8 shows the internal configuration of the cell replacement table 110. Here, the cell name “Data1” of the data before OPC correction is associated with the cell name “A001”.

  The intermediate data generation processing unit 106 generates intermediate data for the second layout of the layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit 112 based on the cell name of the specific component cell. To do. The OPC correction processing unit 108 performs OPC correction of intermediate data according to the first OPC correction rule.

  It should be noted that the pre-OPC correction data has no particular design rule and is appropriately designed to have a desired shape. The degree of fine design is determined by the grid size when drawing the pre-OPC correction data. Therefore, the grid size of the pre-OPC correction data may be set as appropriate depending on the degree of correction required. The cell replacement table 110 can also store the grid size in which the pre-OPC correction data is drawn in association with the cell name of each specific component cell and the cell name of the pre-OPC data. In this case, the grid conversion processing unit 104 refers to the cell replacement table 110 and determines whether the grid size of the design layout data acquired by the layout data acquisition unit 102 is different from the grid size of the pre-OPC correction data. Determine whether grid size conversion is required.

By doing so, the following effects can be obtained.
Conventionally, when it is desired to change the OPC correction rule during mass production, the layout has to be changed back to the design layout data. However, in this embodiment, when the OPC correction rule is changed, the part cell used in the design is not changed (the design layout data is not changed), and the OPC correction rule (program) is significantly corrected. Therefore, the layout after OPC correction can be optimized. In the present invention, the pre-OPC correction data is generated separately from the design layout data. Therefore, when the OPC correction rule is changed, only the pre-OPC correction data needs to be changed so as to conform to it. Thus, it is not necessary to correct the data retroactively to the design layout data of the SRAM section. Further, it is not necessary to significantly modify the OPC correction rule in consideration of both the logic part and the SRAM part. In addition, by performing such correction before OPC correction and performing OPC correction collectively for the entire device, even if the surrounding environment such as a cell adjacent to the target cell is different, there is a slight difference in the OPC correction program. Can be adjusted. Therefore, it is not necessary to prepare a plurality of pre-OPC correction data according to the environment around the target cell, and the preparation becomes simple.

  In order to perform OPC correction with high accuracy, the grid size of layout data must be reduced. However, creating design layout data with a small grid size from the beginning is not desirable because the amount of data becomes enormous. In the present embodiment, layout is performed with a large grid size at the design stage and converted to a small grid size immediately before the OPC correction. Therefore, highly accurate OPC correction can be performed while keeping the design layout data amount small.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

In the above embodiment, the case where the second layout is the SRAM section has been described as an example. However, the second layout is not limited to this, and the structure is designed with a small design rule and includes many repetitive patterns. It can be. The second layout may be a memory unit such as DRAM other than SRAM.
The present invention includes the following aspects.
(Appendix 1)
A method for generating mask data used in lithography,
Obtaining design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule;
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout has a desired shape. Obtaining pre-OPC correction data corresponding to the second layout prepared in advance;
Generating intermediate data by replacing the second layout of the design layout data with the pre-OPC correction data;
Performing OPC correction of the intermediate data according to the first OPC correction rule;
A mask data generation method including:
(Appendix 2)
In the mask data generation method according to attachment 1,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
A mask data generation method further comprising a step of converting a grid size of the design layout data into the second grid size before the step of generating the intermediate data.
(Appendix 3)
In the mask data generation method according to appendix 1 or 2,
The first layout is a logic part,
The mask data generation method, wherein the second layout is a memory unit.
(Appendix 4)
In the mask data generation method according to any one of appendices 1 to 3,
The mask data generation method, wherein the pre-OPC correction data is provided corresponding to each bit cell unit of the second layout.
(Appendix 5)
A system for generating mask data used in lithography,
A layout data acquisition unit that acquires design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule. When,
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout becomes a desired shape. A pre-OPC correction data storage unit for storing pre-OPC correction data prepared in advance,
An intermediate data generation unit that generates intermediate data for the second layout of the design layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit;
An OPC correction processing unit that performs OPC correction of the intermediate data according to the first OPC correction rule;
Mask data generation system including
(Appendix 6)
In the mask data generation system according to attachment 5,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
The mask data generation system further includes a grid conversion processing unit that converts the grid size of the design layout data acquired by the layout data acquisition unit into the second grid size,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. Mask data generation system to generate.
(Appendix 7)
In the mask data generation system according to attachment 6,
A storage unit for storing a grid size in which the pre-OPC correction data corresponding to the second layout is drawn;
It is determined whether or not the grid size of the design layout data is different from the grid size stored in the storage unit. If the grid size is different, the grid size of the design layout data is converted to the grid size stored in the storage unit. A grid conversion processing unit,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. Mask data generation system to generate.

It is a flowchart which shows the procedure of the mask data generation method in embodiment of this invention. It is a schematic diagram which shows an example of mask data. It is a schematic diagram which shows an example of the mask data of a SRAM part. It is a schematic diagram which shows an example of the mask data of a SRAM part. It is a schematic diagram which shows an example of the mask data of a SRAM part. It is a schematic diagram which shows an example of the mask data of a SRAM part. It is a block diagram which shows the structure of the mask data generation system which performs the procedure demonstrated with reference to FIG. It is a figure which shows an example of an internal structure of a cell replacement table.

Explanation of symbols

100 mask data generation system 102 layout data acquisition unit 104 grid conversion processing unit 106 intermediate data generation processing unit 108 OPC correction processing unit 110 cell replacement table 112 pre-OPC correction data storage unit 200a design layout data 200b grid replacement layout data 200c intermediate data 202a SRAM section design layout 202b SRAM section grid replacement layout 202c SRAM section pre-OPC correction data 204a Logic section design layout 204b logic section grid replacement layout 206b Array termination cell 206c Pre-OPC correction data 208b Bit cell 208c Pre-OPC correction data 210b Bit cell

Claims (5)

A method for generating mask data used in lithography,
Obtaining design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule;
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout has a desired shape. Obtaining pre-OPC correction data corresponding to the second layout prepared in advance;
Generating intermediate data by replacing the second layout of the design layout data with the pre-OPC correction data;
Performing OPC correction of the intermediate data according to the first OPC correction rule;
Only including,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
The intermediate data prior to the step of generating a further including a mask data generation method the step of converting the grid size of the design layout data to the second grid size. The mask data generation method according to claim 1 ,
The first layout is a logic part,
The mask data generation method, wherein the second layout is a memory unit. In the mask data generation method according to claim 1 or 2 ,
The mask data generation method, wherein the pre-OPC correction data is provided corresponding to each bit cell unit of the second layout. A system for generating mask data used in lithography,
A layout data acquisition unit that acquires design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule. When,
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout becomes a desired shape. A pre-OPC correction data storage unit for storing pre-OPC correction data prepared in advance,
An intermediate data generation unit that generates intermediate data for the second layout of the design layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit;
An OPC correction processing unit that performs OPC correction of the intermediate data according to the first OPC correction rule;
Only including,
The design layout data is drawn with a first grid size;
The pre-OPC correction data is drawn with a second grid size smaller than the first grid size,
The mask data generation system further includes a grid conversion processing unit that converts the grid size of the design layout data acquired by the layout data acquisition unit into the second grid size,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. mask data generation system which generates. A system for generating mask data used in lithography,
A layout data acquisition unit that acquires design layout data including a first layout designed with a first design rule and a second layout designed with a second design rule smaller than the first design rule. When,
When the OPC correction is performed on the second layout according to the first OPC correction rule set corresponding to the first design rule, the second layout becomes a desired shape. A pre-OPC correction data storage unit for storing pre-OPC correction data prepared in advance,
An intermediate data generation unit that generates intermediate data for the second layout of the design layout data by replacing the pre-OPC correction data stored in the pre-OPC correction data storage unit;
An OPC correction processing unit that performs OPC correction of the intermediate data according to the first OPC correction rule;
Including
A storage unit for storing a grid size in which the pre-OPC correction data corresponding to the second layout is drawn;
It is determined whether or not the grid size of the design layout data is different from the grid size stored in the storage unit. If the grid size is different, the grid size of the design layout data is converted to the grid size stored in the storage unit. A grid conversion processing unit,
The intermediate data generation unit replaces the second layout of the layout data converted by the grid conversion processing unit with the pre-OPC correction data stored in the pre-OPC correction data storage unit, and replaces the intermediate data. Mask data generation system to generate.

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