CN105611113A - Digital video signal synchronization head polarity adaptive method based on FPGA - Google Patents
Digital video signal synchronization head polarity adaptive method based on FPGA Download PDFInfo
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- CN105611113A CN105611113A CN201510959813.8A CN201510959813A CN105611113A CN 105611113 A CN105611113 A CN 105611113A CN 201510959813 A CN201510959813 A CN 201510959813A CN 105611113 A CN105611113 A CN 105611113A
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- signal
- polarity
- video signal
- digital video
- synchronous head
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
Abstract
The invention reveals a digital video signal synchronization head polarity adaptive method based on an FPGA, and relates to a digital video signal decoding circuit and a synchronization head polarity adaptive function module. The method comprises the steps: decoding an inputted DVI standard video signal, an enabling signal (DE) and line synchronization (Hsync) and field synchronization (Vsync) signals meeting a VESA time sequence standard; converting the polarity of a synchronization head signal with any polarity (positive or negative) into a determined polarity through the synchronization head polarity adaptive function module, and carrying out the self-adaption of a random-resolution video signal synchronization head signal meeting the VESA time sequence standard. The method guarantees the normal operation of a subsequent function module no matter whether the synchronization head polarity of the inputted video signal is at a high level or low level, and is universal.
Description
Technical field
The present invention relates to a kind of digital video signal synchronous head polarity adaptive approach. Especially be applicable to realize in airborne intelligent display the adaptive method of digital video signal synchronous head polarity.
Background technology
DVI is digital visual interface, is a kind of technology of high-speed transfer data signal. DVI transmission of video has been avoided the digital-to-analogue conversion of transmitting terminal and the analog-digital conversion process of receiving terminal in analog video signal transmitting procedure, has also avoided the noise jamming problem in analog signal transmission process simultaneously, and therefore image impairment is little.
The existing airborne giant-screen multifunction display overwhelming majority adopts the pattern of the input of DVI as display video signal. The DVI serial digital video signal of input is by the decoding chip processing of decoding, FPGA is by decoded parallel rgb signal, and enable signal (DE), row synchronous (Hsync) and field synchronization (Vsync) signal, export after treatment the vision signal that meets VESA sequential standard for subsequent conditioning circuit.
According to VESA standard, row synchronous head polarity synchronous and field sync signal can be both positive polarity, can be also negative polarity. For display, fpga logic can only meet a kind of signal of synchronous head polarity, if give tacit consent to synchronous head polarity in fpga logic and be negative polarity, the input signal synchronous head polarity obtaining of decoding is positive polarity, there will be decision error, causes the judgement of subsequent logic function to make mistakes. Therefore, must carry out self adaptation to the synchronizing signal of opposed polarity of input, what no matter input signal parsed is the synchronous head signal of what polarity, and the synchronous head signal polarity after adaptation module is all negative polarity, to meet design needs.
Summary of the invention
In view of the defect that above-mentioned prior art exists, the object of the invention is to propose a kind of digital video signal synchronous head polarity adaptive approach based on FPGA.
Above-mentioned purpose of the present invention, to be achieved by the following technical programs: realize based on decoded digital video signal circuit and synchronous head polarity adaptation function module, wherein said decoded digital video signal circuit is decoded into rgb signal by the DVI video standard signal of input and meets the enable signal (DE) of VESA sequential standard, row synchronous (Hsync) and field synchronization (Vsync) signal; Described synchronous head polarity adaptation function module comprises signal level edge arbitration functions module, counter module and upset assignment module, the polarity of the synchronous head signal of any polarity (positive polarity or negative polarity) is changed into definite polarity, and to meeting the arbitrary resolution vision signal synchronous head signal self adaptation of VESA sequential standard.
Remarkable result after technical solution of the present invention application implementation is: the adaptive method of digital video signal synchronous head polarity of the present invention is taking FPGA as basis, the corresponding video decode circuit of arbitrary resolution vision signal utilization for input is decoded, by synchronous head polarity adaptation function module, the line synchronising signal that decoding is obtained and the synchronous head polarity of field sync signal judge. As required synchronous head signal polarity is converted to the polarity needing. Guarantee no matter incoming video signal synchronous head polarity is high level or low level, can meet the normal work of follow-up function module, has versatility.
Brief description of the drawings
Fig. 1 is digital video signal synchronous head polarity adaptive approach theory diagram of the present invention.
Fig. 2 is signal level of the present invention edge arbitration functions module principle block diagram.
Fig. 3 is counter function module principle block diagram of the present invention.
Fig. 4 is the present invention's assignment functional module theory diagram that overturns.
Detailed description of the invention
Below just accompanying drawing in conjunction with the embodiments, is described in further detail the specific embodiment of the present invention, so that technical solution of the present invention is easier to understand, grasp.
Below by specific embodiment, the present invention is described in detail:
Refer to Fig. 1, it is a kind of theory diagram of realizing the adaptive method of digital video signal synchronous head polarity of the present invention. The present invention can realize the adaptive method of digital video signal synchronous head polarity and comprise decoded digital video signal circuit and synchronous head polarity adaptation function module. Decoded digital video signal circuit can be decoded into the DVI serial digital video signal of input parallel RGB data signal and meet the enable signal (DE) of VESA sequential standard, row synchronous (Hsync) and field synchronization (Vsync) signal. Synchronous head polarity adaptation function module is carried out the judgement of synchronous head polarity to the row that obtains of decoding is synchronous with field sync signal, and as required the synchronizing signal of any polarity (positive polarity or negative polarity) is changed into the synchronizing signal of definite polarity.
Synchronous head polarity adaptation function module in the present invention comprises signal level edge arbitration functions module, counter module and upset assignment module. Refer to Fig. 2 to Fig. 4, described signal level edge arbitration functions module is the trigger condition of rolling counters forward and assignment, often carry out clock signal one time, do once judgement, in the time that synchronizing signal is low level, counter is from adding ' 1 ', in the time of synchronizing signal rising edge, stop counting, by the value assignment of counter to register.
Described counter module is under the driving of clock, whenever the hour counter that satisfies condition is from adding ' 1 '.
Described upset assignment module judges the row field signal synchronous head level of input, when synchronous head level is that in the value VESA standard in low hour counter, synchronous head is that low signal sequence coincide, think that the synchronous head signal polarity of input is low, otherwise synchronous head signal polarity is high. By whole sync direction upset.
In sum, visible to the present invention is based on the detailed introduction of FPGA digital video signal synchronous head polarity adaptive approach, its advantage is: compatible strong, there is adaptivity for the input signal of any synchronous head polarity; Flexibility is strong, and the video input signals of arbitrary resolution is had to versatility.
In addition to the implementation, the present invention can also have other embodiment. All employings are equal to the technical scheme of replacement or equivalent transformation formation, within all dropping on the present invention's scope required for protection.
Claims (1)
1. the digital video signal synchronous head polarity adaptive approach based on FPGA, it is characterized in that, realize based on decoded digital video signal circuit and synchronous head polarity adaptation function module, wherein said decoded digital video signal circuit is decoded into rgb signal by the DVI video standard signal of input and meets the enable signal DE of VESA sequential standard, the synchronous Hsync of row and field synchronization Vsync signal; Described synchronous head polarity adaptation function module comprises signal level edge arbitration functions module, counter module and upset assignment module, the polarity of the synchronous head signal of any polarity is changed into definite polarity, and to meeting the arbitrary resolution vision signal synchronous head signal self adaptation of VESA sequential standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510959813.8A CN105611113B (en) | 2015-12-21 | 2015-12-21 | A kind of digital video signal synchronous head polarity adaptive approach based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510959813.8A CN105611113B (en) | 2015-12-21 | 2015-12-21 | A kind of digital video signal synchronous head polarity adaptive approach based on FPGA |
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| CN105611113A true CN105611113A (en) | 2016-05-25 |
| CN105611113B CN105611113B (en) | 2019-03-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831666A (en) * | 2019-02-25 | 2019-05-31 | 苏州长风航空电子有限公司 | A kind of detection method of digital signal transmission quality |
| CN111147107A (en) * | 2019-12-25 | 2020-05-12 | 天地融科技股份有限公司 | Data receiving method and device |
| CN116778857A (en) * | 2023-08-22 | 2023-09-19 | 联士光电（深圳）有限公司 | Input signal polarity self-adapting circuit in micro display panel |
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| JPH04129192U (en) * | 1991-05-13 | 1992-11-25 | 株式会社富士通ゼネラル | Synchronous signal polarity identification circuit |
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2015
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| JPH04129192U (en) * | 1991-05-13 | 1992-11-25 | 株式会社富士通ゼネラル | Synchronous signal polarity identification circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831666A (en) * | 2019-02-25 | 2019-05-31 | 苏州长风航空电子有限公司 | A kind of detection method of digital signal transmission quality |
| CN111147107A (en) * | 2019-12-25 | 2020-05-12 | 天地融科技股份有限公司 | Data receiving method and device |
| CN111147107B (en) * | 2019-12-25 | 2021-12-24 | 天地融科技股份有限公司 | Data receiving method and device |
| CN116778857A (en) * | 2023-08-22 | 2023-09-19 | 联士光电（深圳）有限公司 | Input signal polarity self-adapting circuit in micro display panel |
| CN116778857B (en) * | 2023-08-22 | 2023-11-07 | 联士光电（深圳）有限公司 | Input signal polarity self-adapting circuit in micro display panel |
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| CN105611113B (en) | 2019-03-19 |
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