CN105577363B - For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms - Google Patents
For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms Download PDFInfo
- Publication number
- CN105577363B CN105577363B CN201610062576.XA CN201610062576A CN105577363B CN 105577363 B CN105577363 B CN 105577363B CN 201610062576 A CN201610062576 A CN 201610062576A CN 105577363 B CN105577363 B CN 105577363B
- Authority
- CN
- China
- Prior art keywords
- data
- algorithm
- core
- bit
- algorithms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Storage Device Security (AREA)
Abstract
The invention discloses a kind of Extensible pipeline circuits and its implementation for SM4 cryptographic algorithms, the present invention realizes encryption and decryption interative computation and key schedule using SM4 algorithm cores array, the SM4 algorithm cores array includes N/4 SM4 algorithm cores, the enciphering/deciphering of each 32 128 bit datas of completion of SM4 algorithm cores loop iteration, N/4 SM4 algorithm cores perform parallel, the number of the SM4 algorithms core is adjusted according to I/O bit wides, if I/O bit wides are N, then the algorithm check figure included in structure is N/4.The present invention can perform SM4 algorithm enciphering/decipherings in the form of assembly line, and the adjustment of circuit structure can be carried out according to the I/O interfaces of different bit wides.
Description
Technical field：
The present invention relates to information security technology and IC design fields more particularly to one kind to be directed to SM4 cryptographic algorithms
Extensible pipeline circuit and its implementation.
Background technology：
SM4 algorithms are original SMS4 algorithms, are to be used for nothing by what national commercial cipher management office was announced in January, 2006
The grouping symmetric cryptographic algorithm of line Local Area Network products is approved as professional standard in March, 2012 by national Password Management office.
SM4 algorithms are a kind of block ciphers, and block length and key length are 128 bits.SM4 algorithm standard rules
It is middle by the algorithm partition be three parts：Encryption Algorithm, decipherment algorithm and key schedule.Encryption Algorithm is by 32 interative computations
It is formed with 1 antitone mapping, each interative computation needs to be loaded into one group of round key into round function.Decipherment algorithm and Encryption Algorithm
Structure is identical, and differ only in round key uses order.Algorithms for encryption and decryption round key needed for interative computation by
Key schedule provides.
The realization of SM4 algorithms can be summarized as two classes：Software is realized and hardware realization.The software realization mode speed of service is slow,
And security is poor.The hardware implementation mode speed of service is fast, safe.Existing hardware circuit is mostly using the side of Xun Huan
Formula realizes 32 iteration, i.e., the data of one group 128 bit do not allow to be loaded into new data, this is just before 32 iteration are not completed
Cause throughput relatively low.If however, 32 iteration are fully deployed, although very high throughput can be obtained, again can
Bring larger area overhead.
The content of the invention：
The purpose of the present invention is provide a kind of Extensible pipeline for SM4 cryptographic algorithms in view of the above problems
Circuit and its implementation can not only provide higher throughput, but also will not bring larger area expense.
Above-mentioned purpose is realized by following technical scheme：
A kind of Extensible pipeline circuit for SM4 cryptographic algorithms includes at least：Data are distributed gives birth to enable signal
Into module（S102）, SM4 algorithm core arrays（S104）And data output buffer module（S105）；
The data distribution and enable signal generation module（S102）128 bit datas are assigned to each SM4 in turn to calculate
Among method core array (S104)；
The SM4 algorithm core arrays（S104）Encryption and decryption interative computation and key schedule are used to implement, it is described
SM4 algorithm core arrays (S104) include N/4 SM4 algorithm cores, wherein the 1st core (S106) is the hard of cipher key spreading and encryption and decryption
Multiplexing on part circuit structure is used to implement cipher key spreading or realizes encryption and decryption；The 2 ~ N/4 SM4 algorithms core (S107) is only
It is used to implement encryption and decryption；
The data output buffer module（S105）For the encryption and decryption result of 128 bits to be exported.
The Extensible pipeline circuit for SM4 cryptographic algorithms, further includes input data buffer module（S101）,
The input data buffer module（S101）N-bit data for will continuously input are spliced after 128/N cycle
For the data of 128 bits, wherein N is equal to 8 either 16 or 32 or 64.
The Extensible pipeline circuit for SM4 cryptographic algorithms, further includes state of a control machine（S103）, it is described
State of a control machine（S103）For the working condition that controls entire circuit and to circuit external output status signal.
The Extensible pipeline circuit for SM4 cryptographic algorithms, data distribution is generated with enable signal
Module (S102) is made of a shift register and two counter A and counter B：The shift register is used to generate
The enable signal of SM4 algorithm cores has N/4 output, each corresponding SM4 algorithm cores of output；
The counter A bit wides are log2 (128/N)Bit, count value is from 0 to 128/N -1, for controlling N-bit number
According to being spliced into the required clock periodicity of 128 bits；The counter B bit wides are log2 (N/4)Bit, count value from 0 to
N/4-1。
The implementation method of the above-mentioned Extensible pipeline circuit for SM4 cryptographic algorithms：This method is：It is calculated using SM4
Method core array（S104）Realize encryption and decryption interative computation and key schedule, the SM4 algorithm core arrays（S104）Comprising
N/4 SM4 algorithm cores, the enciphering/deciphering of each 32 128 bit datas of completion of SM4 algorithms core loop iteration, N/4 SM4 algorithm
Core performs parallel, and the number of the SM4 algorithms core is adjusted according to I/O bit wides, if I/O bit wides are N, then included in structure
Algorithm check figure for N/4, be specifically：After the input data that bit wide is N is passed through 128/N cycle, splicing becomes 128 bits
Data, be then sequentially allocated in turn in N/4 SM4 algorithm cores so that being assigned to the data of each algorithm core can keep
32 cycles, and 128 bit datas for being assigned to two neighboring algorithm core stagger 128/N cycle between each other so that it is defeated
Enter data and may not need continuously transmitting for wait, similarly, the result of calculation of two neighboring algorithm core staggers 128/N cycle,
Each result of calculation just needs 128/N cycle to complete output so that and what output data can also be without waiting continuously transmits,
It is exactly that SM4 algorithms core passes through 32 iteration and completes 128 bits to be assigned to 32 cycles that the data of each algorithm core are kept
Time needed for data enciphering/deciphering, data transmission and enciphering/deciphering form overlapping in time so that flowing water without waiting
Line executive mode is achieved.
Description of the drawings：
Fig. 1 SM4 algorithms pipeline organization schematic diagrames provided by the invention；
The state of a control transition diagram of Fig. 2 SM4 algorithms pipeline organization designs provided by the invention；
Specific embodiment：
To make the purpose of the present invention, technical solution and being more clearly understood a little, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
The present invention provides a kind of Extensible pipeline circuit for SM4 cryptographic algorithms, as shown in Figure 1, specifically including：It is defeated
Enter data buffering module S101, data distribution and enable signal generation module S102, state of a control machine S103, SM4 algorithm core battle array
Arrange S104 and data output buffer S105.Wherein, the N that input data buffer module S101 will be inputted continuously（N is equal to 8,16,
32,64）Bit data is spliced into the data of 128 bits after 128/N cycle；Data are distributed generates mould with enable signal
128 bit datas that block S102 exports input buffer are assigned in turn among each SM4 algorithms core, and are calculated for each SM4
Method core provides enable signal；State of a control machine S103 is used to control the working condition of entire circuit and to circuit external output state
Signal；SM4 algorithm core arrays S104 is used to implement encryption and decryption interative computation and key schedule；Data output buffer S105 will
The encryption and decryption result of 128 bits is continuously exported by the data of 128/N period divisions into 128/N N-bit.
As shown in Fig. 2, state of a control machine S103 includes 4 states, specifically include：Idle S201, cipher key spreading S202,
Enciphering/deciphering S203 and ending S204.Each state is described as follows：
Idle phase S201：After circuit " enabled " signal puts height, into idle phase, " start-up operation " letter is then waited
Number put height.
Cipher key spreading stage S202：After " start-up operation " signal puts height, into the cipher key spreading stage, " data will be loaded into
Request " signal puts height, and " starting to be loaded into data " signal is waited to put height, starts to be loaded into data, close after 128/N cycle
Key loading finishes, and should be dragged down at this point, external signal " starts to be loaded into data " signal.External signal " starts to be loaded into data " signal
While dragging down, cipher key spreading is carried out, after 32 cycles, cipher key spreading finishes, and draws high " cipher key spreading finishes " signal.
Encryption/decryption phase S203：After drawing high " cipher key spreading finishes " signal, into the encryption and decryption stage, wait and " starting
It is loaded into data " the continuous loading data of beginning after height are put, by starting encryption and decryption after 128/N cycle.All data are loaded into
After finishing, external signal " starting to be loaded into data " should drag down." loading request of data " " starts to be loaded into number in external signal
According to " be lower drags down afterwards.In+32 cycles of 128/N after " starting to be loaded into data " puts height, encryption and decryption result starts defeated
Go out, each cycle exports N-bit, and output result is with putting high " output data is effective " signal.
Finishing phase S204：" starting to be loaded into data " signal drags down, and shows that all data loadings finish, at this time state machine
Into finishing phase.After treating that all data encrypting and decipherings are completed, draw high signal " work finishes ", state machine receive this signal it
Afterwards, idle state is returned.At this point, user can drag down " start-up operation " signal and circuit " enabled " signal.
Data distribution is made of with enable signal generation module S102 a shift register and two counters A and B.It moves
Bit register is used to generate the enable signal of SM4 algorithm cores, there is N/4 output, each corresponding SM4 algorithm cores of output.It moves
The output after 128/N cycle is deposited in 1st output of bit register for " starting to be loaded into data " signal；2nd output is
" starting to be loaded into data " signal deposits the output after 2 × 128/N cycle；3rd output is " starting to be loaded into data " signal
Deposit the output after 3 × 128/N cycle；And so on.The 1 ~ N/4 of shift register output pass through or computing it
Afterwards, the enable signal as the 1st SM4 algorithm cores；After the 2 ~ N/4 output process of shift register or computing, as
The enable signal of 2nd SM4 algorithm cores；After the 3 ~ N/4 output process of shift register or computing, as the 3rd SM4
The enable signal of algorithm core；And so on.
Counter A bit wides are log2 (128/N)Bit, count value is from 0 to 128/N -1, for N-bit data to be controlled to splice
For the required clock periodicity of 128 bits.Counter B bit wides are log2 (N/4)Bit, count value is from 0 to N/4-1.Data point
The concrete mode matched somebody with somebody is：When the count value of counter A reaches count maximum, show that the data of 128 bits are already prepared to,
The count value current according to counter B, the data of this 128 bit are assigned among the SM4 algorithm cores of reference numeral.With 32 ratios
Exemplified by special I/O interfaces, counter A bit wides are 2 bits, and counter B bit wides are 3 bits, if the count value of counter A is 3, meter
Number device B count values are 5, then the data of 128 bits just are distributed to the SM4 algorithm cores that number is 5.
The circuit of the present invention is the combination of loop iteration structure and parallel organization.SM4 algorithms core uses the side of loop iteration
Formula realizes enciphering/deciphering, and multiple cores are included in SM4 algorithm core arrays, there is no connection relation between core and core, therefore can be parallel
It performs.The data of each SM4 algorithms core processing are distributed by data distributes in turn with enabling generation module, the input of each algorithm core
Data can keep 32 cycles so that each SM4 algorithms have time enough to complete 32 iteration.Due to SM4 algorithm cores
Iteration time it is equal with the input data retention time, therefore mask the retention time of input data.Although each SM4 algorithms
Core is all the structure of loop iteration, but multiple cores can perform parallel and input data staggers in time, therefore
The continuity of achievable data processing in time.The continuity of continuity and output data in conjunction with input data, with regard to structure
Work into whole system can be carried out in the form of assembly line.Specifically：SM4 algorithm core arrays S104 includes N/4 SM4 and calculates
Connection relation is not present between these cores for method core.1st core S106 is on the hardware circuit of cipher key spreading and encryption and decryption
Multiplexing, can not only realize cipher key spreading, but also can realize encryption and decryption.Key expansion function only can just make in cipher key spreading state
With, under other states be encryption and decryption functions.The 2 ~ N/4 SM4 algorithm core S107 function is completely the same.Each SM4 algorithm cores are equal
There are one enable signals, only can just work when the core is enabled.In addition, in cipher key spreading state, only the 1st SM4
Algorithm core works, other do not work.
As shown in Figure 1, the 2 ~ N/4 SM4 algorithm core S107 is by a data selector, round function and antitone mapping mould
Block forms, and round key needed for round function is provided by the 1st SM4 algorithm cores S106.The round function of 1st SM4 algorithm cores S106
It can be multiplexed and do cipher key spreading, under cipher key spreading state, generate 32 round key and be stored among internal register, and
It is always maintained in calculating afterwards constant.
The implementation method of the Extensible pipeline circuit for SM4 cryptographic algorithms of the present invention：This method is：Using SM4
Algorithm core array（S104）Realize encryption and decryption interative computation and key schedule, the SM4 algorithm core arrays（S104）Bag
Containing comprising N/4 SM4 algorithm cores, the enciphering/decipherings of each 32 128 bit datas of completion of SM4 algorithms core loop iteration, N/4
SM4 algorithm cores perform parallel, and the number of the SM4 algorithms core is adjusted according to I/O bit wides, if I/O bit wides are N, then knot
The algorithm check figure included in structure is N/4, is specifically：After the input data that bit wide is N is passed through 128/N cycle, it is spliced into
For the data of 128 bits, then it is sequentially allocated in turn in N/4 SM4 algorithm cores so that be assigned to the data of each algorithm core
32 cycles can be kept, and 128 bit datas for being assigned to two neighboring algorithm core stagger 128/N week between each other
Phase so that input data may not need continuously transmitting for wait, and similarly, the result of calculation of two neighboring algorithm core staggers 128/
N number of cycle, each result of calculation just need 128/N cycle to complete output so that output data can also be without waiting
It continuously transmits, it is exactly that SM4 algorithms core is complete by 32 iteration to be assigned to 32 cycles that the data of each algorithm core are kept
Into the time needed for 128 bit data enciphering/decipherings, data transmission and enciphering/deciphering form overlapping in time so that without etc.
The assembly line executive mode treated is achieved.
The workflow of entire circuit is described as follows：State of a control machine enters after cipher key spreading state, by the 1st SM4
Algorithm core S106 carries out cipher key spreading, after completing key and being loaded into, completes cipher key spreading by 32 cycles, and sends " close
Key extension finishes " signal.After state machine receives this signal, into enciphering/deciphering state, it is carried out at the same time data and is loaded into and adds/solution
It is close.After the loading of all data finishes, into finishing phase, after all data enciphering/decipherings is waited to complete and exports and finishes,
End operation simultaneously returns to idle state.
The expansible characteristic of circuit structure provided by the invention is described as follows：Circuit structure provided by the invention is using parametrization
Design, circuit structure can be adjusted according to the bit wide of I/O interfaces, specific as shown in table 1.Using 8 bit bit wide I/O interfaces as
Example, input data buffering need 16 cycles that 8 bit datas continuously inputted are spliced into 128 bits；In SM4 algorithm core arrays
Comprising number of cores for 2, wherein the 1st kernel reusable does cipher key spreading；Data output buffer was needed by 16 cycles
The data that the data of 128 bits are divided into 8 bits are sequentially output.Other I/O bit wides are similar therewith.
The design parameter of 1 circuit structure of table
The assembly line of circuit structure provided by the invention performs characteristic and is described as follows：
Under encryption and decryption state, data are loaded into, data output and enciphering/deciphering overlap in time, so as to mask data
It is loaded into and data exports the required time so that be achieved from flowing water execution.By taking 32 bit interfaces as an example, using the present invention
The structure of offer can realize each 1 32 bit data of clock cycle parallel processing.
Claims (6)
1. a kind of Extensible pipeline circuit for SM4 cryptographic algorithms, which is characterized in that it is included at least：Data distribute with
Enable signal generation module（S102）, SM4 algorithm core arrays（S104）And data output buffer module（S105）；
The data distribution and enable signal generation module（S102）128 bit datas are assigned to each SM4 algorithms core in turn
Among array (S104)；
The SM4 algorithm core arrays（S104）It is used to implement encryption and decryption interative computation and key schedule, the SM4 algorithms
The number of core is adjusted according to I/O bit wides, if I/O bit wides are N, then the number of algorithm core is N/4 in structure, described
SM4 algorithm core arrays (S104) include N/4 SM4 algorithm cores, wherein the 1st core (S106) is the hard of cipher key spreading and encryption and decryption
Multiplexing on part circuit structure is used to implement cipher key spreading or realizes encryption and decryption；The 2 ~ N/4 SM4 algorithms core (S107) is only
It is used to implement encryption and decryption；
The data output buffer module（S105）For the encryption and decryption result of 128 bits to be exported.
2. the Extensible pipeline circuit according to claim 1 for SM4 cryptographic algorithms, which is characterized in that described
Circuit further includes input data buffer module（S101）, the input data buffer module（S101）For will continuously input
N-bit data are by being spliced into the data of 128 bits after 128/N cycle, wherein N is either 16 or 32 or 64 equal to 8.
3. the Extensible pipeline circuit according to claim 1 or 2 for SM4 cryptographic algorithms, which is characterized in that described
Circuit further include state of a control machine（S103）, the state of a control machine（S103）For controlling the working condition of entire circuit
And to circuit external output status signal.
4. the Extensible pipeline circuit according to claim 1 or 2 for SM4 cryptographic algorithms, which is characterized in that described
Data distribution be made of with enable signal generation module (S102) a shift register and two counter A and counter B：
The shift register is used to generate the enable signal of SM4 algorithm cores, there is N/4 output, and each corresponding SM4 of output is calculated
Method core；
The counter A bit wides are log2 (128/N)Bit, count value is from 0 to 128/N -1, for N-bit data to be controlled to spell
It is connected in the required clock periodicity of 128 bits；The counter B bit wides are log2 (N/4)Bit, count value is from 0 to N/4-
1。
5. the Extensible pipeline circuit according to claim 3 for SM4 cryptographic algorithms, which is characterized in that described
Data distribution is made of with enable signal generation module (S102) a shift register and two counter A and counter B：Institute
The shift register stated is used to generate the enable signal of SM4 algorithm cores, there is N/4 output, each corresponding SM4 algorithm of output
Core；
The counter A bit wides are log2 (128/N)Bit, count value is from 0 to 128/N -1, for N-bit data to be controlled to spell
It is connected in the required clock periodicity of 128 bits；The counter B bit wides are log2 (N/4)Bit, count value is from 0 to N/4-
1。
6. the implementation method of the Extensible pipeline circuit for SM4 cryptographic algorithms described in a kind of one of claim 1-5：Its
It is characterized in that：This method is：Using SM4 algorithm core arrays（S104）Realize encryption and decryption interative computation and key schedule, institute
The SM4 algorithm core arrays stated（S104）Comprising N/4 SM4 algorithm cores, each 32 completions of SM4 algorithms core loop iteration, 128 ratio
The enciphering/deciphering of special data, N/4 SM4 algorithm cores perform parallel, and the number of the SM4 algorithms core is adjusted according to I/O bit wides
It is whole, if I/O bit wides are N, then the algorithm check figure included in structure is N/4, is specifically：The input data that bit wide is N is passed through
After 128/N cycle, then splicing is sequentially allocated as the data of 128 bits in N/4 SM4 algorithm cores in turn so that
32 cycles can be kept by being assigned to the data of each algorithm core, and be assigned to 128 bit datas of two neighboring algorithm core
Staggering 128/N cycle between each other so that input data may not need continuously transmitting for wait, similarly, two neighboring calculation
The result of calculation of method core staggers 128/N cycle, and each result of calculation just needs 128/N cycle to complete output so that defeated
Go out that data can also be without waiting continuously transmits, and is assigned to 32 cycles that the data of each algorithm core are kept and is exactly
SM4 algorithms core completes the time needed for 128 bit data enciphering/decipherings by 32 iteration, and data transmission and enciphering/deciphering are in the time
On form it is overlapping so that assembly line executive mode without waiting is achieved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610062576.XA CN105577363B (en) | 2016-01-29 | 2016-01-29 | For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610062576.XA CN105577363B (en) | 2016-01-29 | 2016-01-29 | For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105577363A CN105577363A (en) | 2016-05-11 |
| CN105577363B true CN105577363B (en) | 2018-06-01 |
Family
ID=55887082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610062576.XA Active CN105577363B (en) | 2016-01-29 | 2016-01-29 | For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105577363B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612683B (en) * | 2017-09-30 | 2020-10-27 | 上海众人网络安全技术有限公司 | Encryption and decryption method, device, system, equipment and storage medium |
| CN109617671B (en) * | 2018-12-21 | 2023-06-09 | 成都海光集成电路设计有限公司 | Encryption and decryption methods, encryption and decryption devices, expansion methods, encryption and decryption systems and terminal |
| CN109981250B (en) * | 2019-03-01 | 2020-04-07 | 北京海泰方圆科技股份有限公司 | SM4 encryption and key expansion method, device, equipment and medium |
| CN111612622B (en) | 2020-05-20 | 2021-03-23 | 深圳比特微电子科技有限公司 | Circuit and method for performing a hashing algorithm |
| CN111625202B (en) * | 2020-07-28 | 2021-03-09 | 上海聪链信息科技有限公司 | Algorithm extension customizing method and system of block chain chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780608A (en) * | 2014-01-14 | 2014-05-07 | 浪潮电子信息产业股份有限公司 | SM4-algorithm control method based on programmable gate array chip |
| CN104333447A (en) * | 2014-11-26 | 2015-02-04 | 上海爱信诺航芯电子科技有限公司 | SM4 method capable of resisting energy analysis attack |
-
2016
- 2016-01-29 CN CN201610062576.XA patent/CN105577363B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780608A (en) * | 2014-01-14 | 2014-05-07 | 浪潮电子信息产业股份有限公司 | SM4-algorithm control method based on programmable gate array chip |
| CN104333447A (en) * | 2014-11-26 | 2015-02-04 | 上海爱信诺航芯电子科技有限公司 | SM4 method capable of resisting energy analysis attack |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105577363A (en) | 2016-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105577363B (en) | For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms | |
| EP1282025B1 (en) | An interface for a security coprocessor | |
| CN110380844A (en) | A kind of quantum key delivering method, equipment and storage medium | |
| CN1321506C (en) | Apparatus and method for performing KASUMI ciphering | |
| US7240203B2 (en) | Method and apparatus for establishing secure sessions | |
| CA1127258A (en) | Method and apparatus for enciphering blocks which succeed short blocks in a key-controlled block-cipher cryptographic system | |
| CN101588233B (en) | Module multiplexing method for AES coprocessor in wireless sensor network node application | |
| CN101083525A (en) | Cryptography processing units and multiplier | |
| US8023644B2 (en) | Multimode block cipher architectures | |
| CN112865954A (en) | Accelerator, chip and system for Paillier decryption | |
| US20200145187A1 (en) | Bit-length parameterizable cipher | |
| CN105007154B (en) | A kind of encrypting and decrypting device based on aes algorithm | |
| CN104933008A (en) | Reconfigurable system and reconfigurable array structure and application of reconfigurable array structure | |
| CN101599828A (en) | A kind of encipher-decipher method of RSA efficiently and coprocessor thereof | |
| CN109617671A (en) | Encryption and decryption, extended method and device, encrypting and deciphering system, terminal | |
| US9992053B1 (en) | Multi-channel, multi-lane encryption circuitry and methods | |
| Ma et al. | Implementation and evaluation of different parallel designs of AES using CUDA | |
| CN101567781A (en) | Sequence number encrypting method and cipher machine generated by sequencing | |
| CN105224286B (en) | Buffer storage for restructural cipher processor | |
| CN110213050A (en) | Key generation method, device and storage medium | |
| CN101630244A (en) | System and method of double-scalar multiplication of streamlined elliptic curve | |
| CN104219045A (en) | RC4 (Rivest cipher 4) stream cipher generator | |
| CN105141558B (en) | Scrambling apparatus and scrambling configuration method | |
| Chen et al. | Implementation and optimization of AES algorithm on the sunway taihulight | |
| CN104158652A (en) | Circulating-unfolded-structured AES encryption/decryption circuit based on data redundancy real-time error detection mechanism |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210330 Address after: No.18, ningshuang Road, Nanjing, Jiangsu, 210000 Patentee after: Nanjing qinheng Microelectronics Co.,Ltd. Address before: No. 18 Ningshuang Road, Yuhuatai District, Nanjing City, Jiangsu Province, 210012 Patentee before: JIANGSU QINHENG Co.,Ltd. |