CN105007154B - A kind of encrypting and decrypting device based on aes algorithm - Google Patents
A kind of encrypting and decrypting device based on aes algorithm Download PDFInfo
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Abstract
The invention discloses a kind of encrypting and decrypting device based on aes algorithm, is related to field of information security technology, solves the problems, such as that AES encryption decryption mode is single in the prior art.The encrypting and decrypting device of the present invention includes the cryptographic handling module for handling data.The cryptographic handling module includes input logic access, the first multi-path choice unit, cipher function arithmetic element, the first demultiplex unit, output logical path and the second multi-path choice unit.AES mode control signal control selections input logic accesses input grouped data, and choose cipher function arithmetic element and handled forward or backwards grouped data, then control selections export logical path output grouping data.Present invention is mainly used for data are encrypted and decrypted by aes algorithm.
Description
Technical field
The present invention relates to field of information security technology more particularly to a kind of encrypting and decrypting devices based on aes algorithm.
Background technology
AES (Advanced Encryption Standard, Advanced Encryption Standard) is U.S. NIST (National
Institute of Standards and Technology, national standard and Institute for Research and Technology) used in establishment in 2002
A kind of new Information Encryption Algorithm.With being constantly progressive for modern password analysis level, chip processing capabilities and computing technique,
Aes algorithm is widely applied in every profession and trade each department, and gradually replaces encryption work(of the DES in IPSec, SSL and ATM
Energy.
The country is normally based on software realization in the research in terms of algorithm realization at present.Relative to software encryption system,
Hardware encryption system processing speed is fast and more safe and reliable.And the high-speed hardware of AES realizes negligible amounts at present.Therefore with
The hardware development of the popularization and application of aes algorithm, algorithm is increasingly becoming an important project.
In the implementation of the present invention, inventor has found at least to have the following technical problems in the prior art：
Aes algorithm includes five kinds of encryption and decryption patterns of ECB, CTR, OFB, CFB and CBC.And in currently available technology, it supports
The AES encryption device of syntype or few, mostly just two or three kind of support.Encryption mode is more single, safety and guarantor
Close property is poor.
Invention content
The present invention provides a kind of encrypting and decrypting device based on aes algorithm, can support the full mould of AES encryption decipherment algorithm
Formula improves the safety and reliability of encrypting and decrypting.
The present invention provides a kind of encrypting and decrypting device based on aes algorithm, includes the Cipher Processing mould for handling data
Block；The cryptographic handling module includes：
At least one input logic access carries out logical operation for the grouped data to input；
First multi-path choice unit, for input logic access to export logic all the way according to the selection of AES mode control signals
Grouped data after operation；
Cipher function arithmetic element, for selecting positive or reversed cipher function according to the AES mode control signals
Decryption processing is encrypted to the grouped data；
Second demultiplex unit, for the grouped data after encrypting and decrypting to be resolved at least grouped data all the way；
At least one output logical path, for carrying out logical operation respectively to decomposing the roads Hou Mei grouped data；
Second multi-path choice unit, for according to AES mode control signals selection output logical path output all the way
Grouped data after logical operation.
The core algorithm part of encrypting and decrypting device provided by the invention based on aes algorithm is realized using devices at full hardware, is propped up
All 5 kinds of AES encryption decryption modes, 3 kinds of key bit wides are held, disclosure satisfy that whole demands to aes algorithm encrypting and decrypting, are improved
The safety of data ciphering and deciphering and confidentiality so that the present invention has the stronger ability for resisting outside world.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram of cryptographic handling module in one embodiment of the invention；
Fig. 2 is the structural schematic diagram of positive cryptographic handling module in one embodiment of the invention；
Fig. 3 is the structural schematic diagram of reversed cryptographic handling module in one embodiment of the invention；
Fig. 4 is the structural schematic diagram of positive crypto-operation unit in one embodiment of the invention；
Fig. 5 is the structural schematic diagram of reversed crypto-operation unit in one embodiment of the invention；
Fig. 6 is the process chart of positive crypto-operation unit in Fig. 4；
Fig. 7 is the process chart of reversed crypto-operation unit in Fig. 5；
Fig. 8 is the structural schematic diagram of the encrypting and decrypting device provided by the present invention based on aes algorithm.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
The characteristics of encrypting and decrypting device provided by the present invention is according to aes algorithm encryption decryption scheme, to logical resource reality
Now it is multiplexed.From the flow chart of data processing of aes algorithm encrypting and decrypting it is found that the difference of several encryption modes is at 2 points：When
The constituted mode of input grouped data and output grouping data after processing before cipher function processing；Second is that selected cipher function.
According to above-mentioned two feature, a plurality of logical channel is transferred to handle data before and after treatment in the present invention.For
Data constituted mode is identical before and after the processing, and multiplexing is merged by logical channel.In this way, when encrypting and decrypting is handled, only
Relevant logical channel need to be selected, forwards/reverse cipher function is recalled and a variety of AES encryption decryption modes can be realized.Below
It is described in detail in conjunction with the embodiments.
In one embodiment provided by the present invention, the encrypting and decrypting device based on aes algorithm is mainly to Cipher Processing mould
Block is improved.Specifically, as shown in Figure 1, cryptographic handling module includes：
At least one input logic access carries out logical operation for the grouped data to input；
First multi-path choice unit, for input logic access to export logic all the way according to the selection of AES mode control signals
Grouped data after operation；
Cipher function arithmetic element, for selecting positive or reversed cipher function according to the AES mode control signals
Decryption processing is encrypted to the grouped data；
First demultiplex unit, for the grouped data after encrypting and decrypting to be resolved at least grouped data all the way；
At least one output logical path, for carrying out logical operation respectively to decomposing the roads Hou Mei grouped data；
Second multi-path choice unit, for according to AES mode control signals selection output logical path output all the way
Grouped data after logical operation.
Specifically, the cryptographic handling module further includes the second demultiplex unit being connected with input logic access,
For the grouped data of input to be resolved into multichannel.When input grouped data handled by the input logic access is identical, need
It is sent in each input logic access after being decomposed to the grouped data of input by the second road resolving cell.When input logic is logical
When the input grouped data difference of road processing, then input logic access is directly transferred to handle input grouped data.
Specifically, the output logical path is any one in following output logical path：First input logic is logical
Road, for directly inputting grouped data；Second input logic access, it is different for inputting grouped data and the progress of password initial vector
Or the data after logical operation；Third input logic access, 128 data of output point for inputting grouped data and previous stage
Group carries out the data after XOR logic operation；4th input logic access, for directly inputting key initial vector；5th input
Logical path, for inputting, previous stage inputs low b-s of grouping and the positions s of previous stage ciphertext carry out the number after splicing operation
According to；6th input logic access, 128 packets of output for inputting previous stage；7th input logic access, for defeated
Enter the value of counter.
Specifically, the output logical path is any one in following output logical path：First output logic is logical
Road is used for direct output grouping data；Second output logical path, the s for high s of output grouping data and working as prime plaintext
Data after the XOR operation of position；Third exports logical path, and XOR operation is carried out in plain text with prime is worked as output grouping data
Data afterwards；4th output logical path carries out XOR operation for high s for output grouping data with the positions s for working as prime ciphertext
Data afterwards；5th output logical path, for output grouping data and data after prime ciphertext XOR operation；6th is defeated
Go out logical path, for output grouping data and the data after key initial vector XOR operation；7th output logical path, is used
Data after the input ciphertext of output grouping data and previous stage carries out XOR operation.
Compared with prior art, positive encryption and the input logic channel reversely decrypted and output logic are led in the present invention
Road is multiplexed, and effectively saves the hardware realization area of device.By configuring input logic channel and output logical channel, realize
The various modes of aes algorithm.The specific implementation of the various modes of aes algorithm is carried out specifically in the following embodiments
It is bright.
In one embodiment provided by the present invention, cryptographic handling module is divided into positive cipher function processing and reversed close
Code function processing is divided into two independent modules.Specifically, input logic access, multi-path choice list are separately included in two modules
Member, demultiplex unit and output logical path.It describes in detail below to the specific implementation process of two modules.
Referring to Fig. 2, positive cipher function processing module includes seven input logic accesses, two demultiplexers, two
Multiple selector, positive cipher function arithmetic element and five tunnels export logical path.Wherein, clear packets data are through multichannel point
It is three input logic accesses to solve device output.Other four input logic access input grouped datas are different, it is not necessary that multichannel is arranged
Decomposer.The input terminal of seven input logic access output the first multiple selector of connection.The output end of first multiple selector
The positive cipher function arithmetic element of connection；Positive cipher function arithmetic element output end connects the second demultiplexer.More than second
Road destroyer breaks down is five output logical paths.Five output logical paths select to export by the second multiple selector.
Wherein, seven input logic accesses include：Access (1), for directly inputting clear packets data；Access (2) is used
Data after input clear packets data carry out XOR logic operation with password initial vector；Access (3), for inputting in plain text
128 packets of output of grouped data and previous stage carry out the data after XOR logic operation.Access (4), for direct
Input key initial vector IV；Access (5), for inputting low b-s of previous stage clear packets data and the s of previous stage ciphertext
Position carries out the data after splicing operation；Access (6), 128 packets for inputting previous stage output；Access (7), is used for
Input the value of counter.Wherein, five output logical paths include：Access (8), for directly exporting ciphertext block data；It is logical
Road (9), for exporting high s of ciphertext block data and the data after positions the s XOR operation of prime plaintext；Access (10) is used
Data after exporting ciphertext block data and when prime progress XOR operation in plain text；Access (11), for exporting ciphertext block
High s of data and the data after positions s of prime ciphertext carry out XOR operation；Access (12), for exporting ciphertext block data
With data after prime ciphertext XOR operation.
Referring to Fig. 3, reversed cipher function processing module includes an input logic access, reversed cipher function operation list
Member, demultiplexer, three output logical paths and a multiple selector.It is patrolled since reverse process pertains only to an input
Channel is collected, therefore the demultiplexer of input terminal and multiple selector can be omitted.Input logic channel connects reversed password letter
Number arithmetic element；The reversed demultiplexed device of cipher function arithmetic element is divided into three output logical paths；Export logical path
It selects to export by multiple selector.
Wherein, input logic access includes access (0), for directly exporting ciphertext block data.Three output logics are logical
Road includes：Access (1), for directly exporting ciphertext block data；Access (2), at the beginning of exporting clear packets data and key
Data after the vector IV XOR operation that begins；Access (3), the input ciphertext for exporting clear packets data and previous stage carry out different
Or the data after operation.
Based on above-mentioned it is found that the present invention uses logical resource multiplexing technology, for carrying out 5 kinds of pattern identity logic channels
Merge, while the positive cipher function CIPHk being involved in and reversed cipher function CIPH-1K carries out individually designed.Pass through AES
Mode control signal selects input logic access and output logical path, and is called cipher function as public module,
Realize 5 kinds of encryption and decryption patterns of aes algorithm.The specific implementation for realizing 5 kinds of patterns is described below.
ECB encryption：Using the access (1) (8) of Fig. 2；ECB is decrypted：Using the access (0) (1) of Fig. 3.
CBC is encrypted：First input, 128 packets use the access (2) (8) of Fig. 2, other 128 data of input
Grouping uses the access (3) (8) of Fig. 2.CBC is decrypted：First output, 128 packets use the access (0) (2) of Fig. 3,
He exports the access (0) (3) that 128 packets use Fig. 3.
CFB is encrypted：First input, 128 packets use the access (4) (9) of Fig. 2, other 128 data of input
Grouping uses the access (5) (10) of Fig. 2.CFB is decrypted：First input, 128 packets use the access (4) (11) of Fig. 2,
Other input the access (5) (11) that 128 packets use Fig. 2.
OFB is encrypted：First input, 128 packets use the access (4) (10) of Fig. 2, other 128 data of input
Grouping uses the access (6) (10) of Fig. 2.OFB is decrypted：First input, 128 packets use the access (4) (12) of Fig. 2,
Other input the access (6) (12) that 128 packets use Fig. 2.
CTR is encrypted：Using the access (7) (10) of Fig. 2.CTR is decrypted：Using the access (7) (12) of Fig. 2.
It should be noted that the invention is not limited in above-described embodiments.It is patrolled for choosing input logic channel and output
Arbitrary realized any one or more encryption decryption scheme of ECB, CTR, OFB, CFB, CBC of combination for collecting channel, all in this hair
Within bright protection domain.Compared with prior art, a variety of encryption and decryption may be implemented in encrypting and decrypting device provided by the present invention
Pattern effectively improves safety and the confidentiality of data, while by being multiplexed to logical resource, effectively saves the hard of device
Part realizes area.
In one embodiment provided by the present invention, for positive cipher function arithmetic element and reversed cipher function operation
Unit is improved.Since 3 kinds of bit wide aes algorithms have corresponded to the key K of 128/192/256bit respectively, but their data
The least unit of processing is all 128bit, for no other reason than that the different corresponding encrypting and decrypting data processing wheel numbers of key bit wide are different,
Respectively 10/12/14 wheel.And the mode for often taking turns processing is just as, therefore will often to take turns processing mode individually designed by the present invention, makees
It is called for public resource, to reach saving resource, reduces the effect of area.For different wheel numbers, matched using register
The mode set controls the number that single-wheel processing public module calls.
Specifically, referring to Fig. 4, positive cipher function arithmetic element includes two modules：First operation sequentially to data into
The transformation of row S boxes, row transformation, rank transformation and expanded keys exclusive or are handled, for realizing the wheel of other wheels in addition to last wheel
Operation.Second computing module sequentially carries out the transformation of S boxes, row transformation and 3 step of expanded keys exclusive or to data, for realizing last
The wheel operation of one wheel.
Referring to Fig. 5, reversed cipher function arithmetic element includes two modules：Third computing module sequentially carries out data anti-
Row transformation, the transformation of anti-S boxes are handled with expanded keys exclusive or, anti-rank transformation, realize the wheel fortune of other wheels in addition to last wheel
It calculates；4th computing module sequentially carries out anti-row transformation, the transformation of anti-S boxes to data, is handled with expanded keys exclusive or, realizes last
Wheel wheel operation.
In the prior art, the process of operation is taken turns as contrary in positive function arithmetic unit and reversed function arithmetic unit.
From the foregoing, the reversed function arithmetic unit of the present invention with the wheel calculating process in positive function arithmetic unit and non-fully phase
It is inverse.Therefore, compared with prior art, the present invention having higher safety.
Referring to Fig. 6 and Fig. 7, the present invention is preferably designed using multistage flowing water for taking turns the processing of operation.Such as 1 institute of table
Show, wheel operation is preferably divided into Nr1, Nr2, Nr3, Nr4 in the present invention, 5 wheel of final wheel, the sum that 5 wheels are added is Nr.Certainly
It is segmented into more stages or is suitably adjusted every grade of wheel operation times.
Table 1
Wherein, the digital representation in table will do the number of wheel operation, the wheel operation for indicating not doing this grade if it is 0.
First step cone operation times Nr1 unified distributions are 3, and fourth stage wheel operation times Nr4+ finally takes turns distribution can be due to always taking turns number difference
It is different.Second step cone operation times Nr2 and third step cone operation times Nr3, does the step cone operation and is then assigned as 4, no if necessary
It is 0 to do the step cone operation then.Often wheel operation needs 1 clock cycle, and Nr1 is assigned as 3.Nr1 wheels are different with expanded keys before executing
Or need to consume 1 clock cycle, it needs 4 clock cycle together with Nr1, in this way when 128 packets of input fill up 4
After level production line, so that it may with every 4 clock cycle, export 128 packets, substantially reduce original positive cipher function,
Reversed cipher function is required for 10/12/14 clock cycle just to generate the time for exporting 128 grouped datas.
In one embodiment provided by the present invention, the cryptographic handling module further includes bit width conversion unit, for pair
The grouped data of the input and bit width conversion is carried out to the grouped data of output.Specifically, as in Fig. 2, bit width conversion list
The output end of the input terminal and multiple selector of member connection demultiplexer.Bit width conversion unit connecting path (0) is defeated in Fig. 3
Enter the output end of end and multiple selector.
In one embodiment provided by the present invention, referring to Fig. 8, AES encryption decryption device further includes and Cipher Processing mould
The connected interaction registration module of block, for generating the AES scheme controls needed for cryptographic handling module according to register configuration information
Signal C.The configuration information of register can be obtained from input traffic in the present invention, can also be obtained from processor corresponding
Configuration information.Interaction registration module generates AES mode control signal C according to register configuration information, controls Cipher Processing mould
Block treats encryption and decryption grouped data D0 and decryption processing is encrypted in key initial vector IV.It should be noted that AES pattern controls
Signal C processed is applied not only to control encryption and decryption pattern, is additionally operable to control work bit wide etc..
In one embodiment provided by the present invention, the encrypting and decrypting device further includes and interacts what registration module was connected
Processor module, for register configuration information to be arranged.Above-mentioned to refer to, the register configuration information of input traffic load is actually
Hardware configuration mode, its advantage is that the speed of service is fast, but configuration mode is relatively single and fixed.And processor module is software
Configuration mode, i.e. user can be by loading corresponding configurator in processor module, you can complete register configuration.Cause
This, configuration mode of the processor configuration mode relative to input traffic has higher flexibility.And the present invention is using the two
In conjunction with mode, can configure various working methods, improve the speed of service of the present apparatus, while also enhancing the flexible of configuration
Property.
In one embodiment provided by the present invention, the encrypting and decrypting device further includes input data selecting module.Institute
Input data selecting module is stated for selecting the input traffic D of different-format to enter interactive registration module.In input traffic D
Contain the data D0 of register configuration information and decryption to be encrypted.
In one embodiment provided by the present invention, the encrypting and decrypting device further includes interface module, and being used for will be different
The input traffic of format carries out format conversion, transformed data flow through the input data selecting module select it is defeated
Go out.Wherein, the interface module includes that serial ports converting unit, parallel port converting unit, SPI converting units and JTAG conversions are single
Member.Wherein, serial ports converting unit is used to converting serial data streams being converted into 32 at parallel data stream, such as by 1 bit data stream
Bit data stream, Parallel transformation unit are used to a kind of parallel data stream being converted into another parallel data stream, such as by 8 or 16
Or 32 bit data stream be converted into 32 bit data streams.SPI converting units are used to change the stream compression for meeting SPI protocol into parallel number
It is converted into 32 data flows according to stream, such as by 1 or 2 or 4 bit data streams.JTAG converting units will meet the data of JTAG protocol
Circulation changes parallel data stream into, such as 1 bit data stream is converted into 32 bit data streams.Wherein, JTAG converting units can also be used
In configuring cipher key K.Interface module in the present invention uses traffic transmission rate matching technique, by the interface of a variety of different rates
It is unified into the interface of fixed rate, follow-up data is facilitated to handle.
In one embodiment provided by the present invention, the encrypting and decrypting device further includes output data selecting module, is used
According to the positive processing data D1 of the AES mode control signals C controls cryptographic handling module selection output or reversely
Handle data D2.The output data selecting module will be at forwards/reverse according to the AES mode control signals C of interaction register
Data after reason carry out selection output, and are stored, and the loading procedure of entire data flow is completed.
In one embodiment provided by the present invention, the encrypting and decrypting device further includes and output data selecting module phase
Memory module even, data that treated for storing forwards/reverse.
In conclusion encrypting and decrypting device provided by the present invention realizes the core of aes algorithm using devices at full hardware,
All 5 kinds of encryption and decryption patterns are supported simultaneously, be disclosure satisfy that whole demands of encrypting and decrypting, are improved safety and the secrecy of data
Property.Therefore compared with the existing technology, the present invention has the stronger ability for resisting outside world.In addition, the present apparatus is with a variety of
Configuration mode, effectively increases the flexibility of device configuration, while supporting a variety of data-interfaces, meets a variety of data flow applications
Demand.
It is that can pass through one of ordinary skill in the art will appreciate that realizing all or part of flow in above-described embodiment
Computer program is completed to instruct relevant hardware, and the program can be stored in a computer read/write memory medium,
The program is when being executed, it may include such as the flow of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic disc,
CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, all answer by the change or replacement that can be readily occurred in
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (12)
1. a kind of encrypting and decrypting device based on aes algorithm, which is characterized in that include the Cipher Processing mould for handling data
Block；The cryptographic handling module includes：
At least one input logic access carries out logical operation for the grouped data to input；
First multi-path choice unit, for input logic access to export logical operation all the way according to the selection of AES mode control signals
Grouped data afterwards, the AES mode control signals are generated according to user configuration information, and the user configuration information includes user
The AES operating modes of selection；
Cipher function arithmetic element, for selecting positive or reversed cipher function to institute according to the AES mode control signals
It states grouped data and decryption processing is encrypted；
First demultiplex unit, for the grouped data after encrypting and decrypting to be resolved at least grouped data all the way；
At least one output logical path, for carrying out logical operation respectively to decomposing the roads Hou Mei grouped data；
Second multi-path choice unit, for output logical path to export logic all the way according to AES mode control signals selection
Grouped data after operation.
2. encrypting and decrypting device according to claim 1, which is characterized in that the cryptographic handling module further includes more than second
Road resolving cell for the grouped data of input to be decomposed into multichannel, and is sent in the input logic access.
3. encrypting and decrypting device according to claim 1, which is characterized in that the input logic access is that following input is patrolled
Collect any one in access：
First input logic access, for directly inputting grouped data；
Second input logic access carries out the data after XOR logic operation for inputting grouped data and password initial vector；
Third input logic access, 128 packets of output for inputting grouped data and previous stage carry out XOR logic
Data after operation；
4th input logic access, for directly inputting key initial vector；
5th input logic access, for inputting, previous stage inputs low b-s of grouping and the positions s of previous stage ciphertext are spliced
Data after operation；
6th input logic access, 128 packets of output for inputting previous stage；
7th input logic access, the value for inputting counter.
4. encrypting and decrypting device according to claim 1, which is characterized in that the output logical path is that following output is patrolled
Collect any one in access：
First output logical path, is used for direct output grouping data；
Second output logical path, for high s of output grouping data and the data after positions the s XOR operation of prime plaintext；
Third exports logical path, for output grouping data and data after prime carries out XOR operation in plain text；
4th output logical path, for high s of output grouping data and the number after progress XOR operation of the positions s of prime ciphertext
According to；
5th output logical path, for output grouping data and data after prime ciphertext XOR operation；
6th output logical path, for output grouping data and the data after key initial vector XOR operation；
7th output logical path carries out the data after XOR operation for the input ciphertext of output grouping data and previous stage.
5. encrypting and decrypting device according to claim 1, which is characterized in that the cipher function arithmetic element includes forward direction
Cipher function arithmetic element and reversed cipher function arithmetic element；Wherein,
The forward direction cipher function arithmetic element includes two modules：First computing module sequentially carries out the transformation of S boxes, row to data
Transformation, rank transformation are handled with expanded keys exclusive or, for realizing the wheel operation that other are taken turns in addition to last rounds of operations；The
Two computing modules sequentially carry out the transformation of S boxes, row transformation to data, are handled with expanded keys exclusive or, for realizing last rounds of
Operation；
The reversed cipher function arithmetic element includes two modules：Third computing module sequentially to data carry out anti-row transformation,
Anti- S boxes transformation is handled with expanded keys exclusive or and anti-rank transformation, for realizing the wheel fortune that other are taken turns in addition to last wheel
It calculates；4th computing module sequentially carries out anti-row transformation, the transformation of anti-S boxes to data, is handled with expanded keys exclusive or, for realizing most
Rounds of operations afterwards.
6. encrypting and decrypting device according to claim 1, which is characterized in that the cryptographic handling module further includes that bit wide turns
Unit is changed, the grouped data for grouped data and output to input carries out bit width conversion.
7. encrypting and decrypting device according to claim 1, which is characterized in that the encrypting and decrypting device further includes that interaction is posted
Storing module, for generating the AES mode control signals according to register configuration information.
8. encrypting and decrypting device according to claim 7, which is characterized in that the encrypting and decrypting device further includes processor
Module, for configuring the register configuration information needed for the interactive registration module.
9. encrypting and decrypting device according to claim 7, which is characterized in that the encrypting and decrypting device further includes input number
According to selecting module, for selecting the input traffic of different-format to enter interactive registration module.
10. encrypting and decrypting device according to claim 9, which is characterized in that the encrypting and decrypting device further includes interface
Module, for being sent to the input data selecting module after the input traffic of different-format is carried out format conversion.
11. encrypting and decrypting device according to claim 1, which is characterized in that the encrypting and decrypting device further includes output
Data selecting module, for controlling the cryptographic handling module selection output forwards/reverse according to the AES mode control signals
Data that treated.
12. encrypting and decrypting device according to claim 11, which is characterized in that the encrypting and decrypting device further includes storage
Module, the data for storing the output data selecting module output.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105512573B (en) * | 2015-11-24 | 2019-02-05 | 深圳国微技术有限公司 | A kind of moderator of attack resistance |
| CN105610585A (en) * | 2016-03-14 | 2016-05-25 | 北京三未信安科技发展有限公司 | Crypto-operation supporting microprocessor, method and system |
| CN109670320B (en) * | 2017-10-13 | 2023-04-25 | 三星电子株式会社 | Encryption device and decryption device, and operation method thereof |
| CN109714162A (en) * | 2019-01-29 | 2019-05-03 | 南京南瑞国盾量子技术有限公司 | A kind of quantum key expansion method and system |
| CN111488628B (en) * | 2020-06-02 | 2022-08-05 | 南京大学 | Address encryption circuit, address encryption method and setting network |
| CN115022000B (en) * | 2022-05-27 | 2023-12-01 | 北京交大微联科技有限公司 | Communication method and device of railway signal system and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101782956A (en) * | 2010-02-09 | 2010-07-21 | 杭州晟元芯片技术有限公司 | Method and device for protecting data on basis of AES real-time encryption |
| CN102185692A (en) * | 2011-04-25 | 2011-09-14 | 北京航空航天大学 | Multimode reconfigurable encryption method based on advanced encryption standard (AES) encryption algorithm |
| CN102799800A (en) * | 2011-05-23 | 2012-11-28 | 中国科学院计算技术研究所 | Security encryption coprocessor and wireless sensor network node chip |
-
2015
- 2015-07-23 CN CN201510437634.8A patent/CN105007154B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101782956A (en) * | 2010-02-09 | 2010-07-21 | 杭州晟元芯片技术有限公司 | Method and device for protecting data on basis of AES real-time encryption |
| CN102185692A (en) * | 2011-04-25 | 2011-09-14 | 北京航空航天大学 | Multimode reconfigurable encryption method based on advanced encryption standard (AES) encryption algorithm |
| CN102799800A (en) * | 2011-05-23 | 2012-11-28 | 中国科学院计算技术研究所 | Security encryption coprocessor and wireless sensor network node chip |
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