CN206585573U - reconfigurable S-box circuit structure - Google Patents
reconfigurable S-box circuit structure Download PDFInfo
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- CN206585573U CN206585573U CN201720193909.2U CN201720193909U CN206585573U CN 206585573 U CN206585573 U CN 206585573U CN 201720193909 U CN201720193909 U CN 201720193909U CN 206585573 U CN206585573 U CN 206585573U
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Abstract
The Reconfigurable S-box circuit structure that the utility model is provided, including：Composite matrix multiplication unit 1, composite matrix multiplication unit 2, constant add unit 1, constant plus unit 2, constant plus unit 3, constant plus unit 4, compositum multiplication against unit, selector 1, selector 2, byte data input port, byte data output port and control signal input mouthful, and the selector 1 and the selector 2 are one-out-three selector.The Reconfigurable S-box circuit structure that the utility model is provided, by being multiplexed compositum multiplication against unit mode, realizes the reconfigurable function of the computing of AES encryption S boxes, AES decryption S boxes computings and SM4 S box computings.The inverse multiplexing of compositum multiplication can greatly reduce circuit area, while the composite matrix structure in Reconfigurable S-box is conducive to the raising of circuit optimization efficiency, so as to further reduce circuit area.
Description
Technical field
The utility model is related to cryptochannel field, more particularly to a kind of Reconfigurable S-box circuit structure.
Background technology
1.AES cryptographic algorithms and SM4 cryptographic algorithms
AES (Advanced Encryption Standard, Advanced Encryption Standard) is by American National Standard and technology
A new generation's packet symmetric cryptographic algorithm that research institute formulates for 2001, original DES (the Data Encryption for replacing
Standard, data encryption standards).The data packet length of AES cryptographic algorithms is 128 bits, and key length has 128,192 Hes
256 three kinds of bits.AES is provided, according to these three different key lengths, and ciphering process is respectively necessary for the wheel of carry out 10,12 and 14
Round transformation computing, each round transformation computing includes byte and replaced again, and row displacement, row mixing and key add four sub- computings, remove
Last wheel, in order to eliminate symmetry, last wheel round transformation does not include row hybrid operations.AES decrypting processes are encrypted
The inverse process of journey, therefore the wheel round transformation computing of carry out 10,12 and 14 is also respectively necessary for, and each round round transformation is replaced including inverse byte
Change, Retrograde transposition, inverse row mixing and inverse key add four sub- computings, except the first round, first round round transformation, which does not include inverse row, to be mixed
Close computing.
SM4 AESs are first commercializations announced by the national commercial cipher management office of China in January, 2006
Block cipher, its block length and key length are 128 bits.AES and key schedule are all taken turns using 32
Nonlinear iteration structure.AES is identical with the structure of decipherment algorithm, is only that the use order of round key is opposite.Each round
SM4 round transformations include byte replacement operation, cycle shift operation and XOR.
Cryptographic algorithm can be realized by hardware, can also be realized by software.Software encryption technique have flexibility it is high,
The advantages of scalability is strong and portable good, but enciphering rate is relatively low, and due to the opening of software runtime environment, it is close
Code algorithm and encryption information are easily tampered and stolen.Compared with software encryption technique, hardware-based cryptographic has higher thing
Security and enciphering rate are managed, with broader practice prospect.In order to improve the flexibility of hardware-based cryptographic, generally require
By different algorithm integrations into a hardware platform.It is not only integrated at home in the Related product of safety chip manufacturer
SM4 cryptographic algorithms are also integrated with AES cryptographic algorithms, to meet the encryption requirements of different application occasion.
2.AES S boxes computings and SM4S box computings
In AES cryptographic algorithms and SM4 cryptographic algorithms, byte replacement operation (commonly referred to as S boxes computing) is unique non-
Linear operation, computational complexity highest.Therefore in AES cipher circuits and SM4 cipher circuits, S box computing circuits are
Topmost arithmetic unit, occupies most of logical resource respectively in the two cipher circuits.
2.1AES S box computings
The S boxes of AES cryptographic algorithms and the S boxes of SM4 cryptographic algorithms are all byte operation units, that is, it is all one to input and export
Individual byte.In AES cryptographic algorithms, ciphering process and decrypting process use different S box computings, defeated in encryption S box computings
Enter byte and carry out a finite field gf (2 first8) domain comultiplication inverse operation, an Affine arithmetic is then carried out, its expression formula is：
Wherein x is input byte, (x)A -1The GF (2 specified for AES cryptographic algorithms8) inverse of multiplication on domain, MAFor 8 ×
8bit constant matrices, cAFor 8bit constant vectors, MAAnd cAFor completing the Affine arithmetic in encryption S boxes.
Specified GF (2 in AES cryptographic algorithms8) irreducible function in domain is
F (x)=x8+x4+x3+x+1
Constant matrices MAWith constant vector cARespectively：
Decryption S box computings are the inverse operations for encrypting S box computings, and its expression formula is：
Wherein M'AFor MAInverse of a matrix matrix, M'AAnd cAFor complete decryption S boxes in Affine arithmetic, other computings with
Formula (1) computing is identical.
2.2SM4S box computings
In SM4 cryptographic algorithms, ciphering process and decrypting process use same S boxes computing.In SM4S box computings, input
Byte carries out an Affine arithmetic first, and a GF (2 is then carried out again8) domain inverse of multiplication, affine fortune is finally carried out again
Calculate, its expression is
Wherein (Ms×x+cs)S -1The GF (2 specified for SM4 cryptographic algorithms8) inverse of multiplication on domain, MSFor 8 × 8bit
Constant matrices, cSFor 8bit constant vectors, MSAnd cSFor completing Affine arithmetic.
Specified GF (2 in SM4 cryptographic algorithms8) irreducible function in domain is
F (x)=x8+x7+x6+x5+x4+x2+1
Constant matrices MSWith constant vector cSRespectively：
3. AES S boxes computings and SM4S box computings based on compositum
From formula (1)~(3), AES S boxes computings and the computing of SM4S boxes are all by GF (28) domain inverse of multiplication and
Affine arithmetic is constituted, wherein GF (28) domain inverse of multiplication is computing most complicated in two S boxes.As AES cryptographic algorithms and SM4
Cryptographic algorithm, can be by arithmetic element multiplex mode to GF (2 when same hardware platform is realized8) domain multiplication is inverse is answered
With, it can so substantially reduce circuit area, but it is not same GF that AES cryptographic algorithms and SM4 cryptographic algorithms, which use,
(28) domain, therefore can not be directly to GF (28) domain multiplication is inverse is multiplexed.The utility model is further by the GF in AES S boxes
(28) GF (2 in inverse of multiplication and SM4S boxes8) inverse of multiplication is mapped to same compositum (i.e. GF ((24)2) or GF
(((22)2)2) domain) middle realization, so as to realize GF (28) the inverse multiplexing of domain multiplication, reduce the circuit face of cryptographic algorithms' implementation
Product.
The 3.1 AES encryption S boxes based on compositum
AES encryption S box operation expressions based on compositum are：
Wherein ()C -1For the inverse of multiplication on compositum, compositum for arbitrarily with GF (28) domain isomorphism compositum, DA
For 8 × 8bit mapping matrixes, it is that will input byte x from GF (2 that it, which is acted on,8) domain mapping is to target compositum, D'AFor DAInverse matrix,
Its effect is that compositum inverse of multiplication result is mapped back to the GF (2 specified by AES cryptographic algorithms from target compositum8)
Domain.In formula (4), MAAnd D'AAll it is 8 × 8bit matrixes, therefore 8 × 8bit matrix can be merged into, after merging
AES encryption S box operation expressions are：
Wherein constant matrices QAFor MAAnd D'AMerge matrix, i.e. QA=MA×D'A, constant matrices QAAlso it is 8 × 8bit constants
Matrix.
The 3.2 AES decryption S boxes based on compositum
AES based on compositum decrypts S box operation expressions：
Related operation in above formula is identical with formula (4).Equally, mapping matrix DAWith constant matrices M'AOne can be merged into
Individual matrix, the AES after merging decrypts S box operation expressions and is：
Wherein constant matrices Q'A=DA×M'A, constant vector dA=Q'A×cA。
The 3.3 SM4S boxes based on compositum
SM4S box operation expressions based on compositum are：
Wherein ()C –1For the inverse of multiplication on target compositum, DSFor mapping matrix, D'SFor inverse mapping matrix.
The compositum in compositum and formula (5~7) in formula (8) is same compositum, so can be real in hardware
Compositum multiplication is multiplexed in existing circuit against unit.Equally, the correlation matrix in formula (8) is merged, after merging
SM4S box operation expressions are：
Wherein constant matrices QS=MS×D'S, constant matrices RS=DS×MS, constant vector dS=DS×cS。
Because in the prior art, the S boxes computing in AES cryptographic algorithms and the S boxes computing in SM4 cryptographic algorithms are logical respectively
Two different circuit realirations are crossed, cause the circuit area of overall cryptographic algorithm larger, so that using the encryption method
Device volume it is larger.
The content of the invention
The utility model provides a kind of Reconfigurable S-box circuit structure, the circuit area to reduce cryptographic algorithms' implementation.
In order to solve the above problems, the utility model provides a kind of Reconfigurable S-box circuit structure, including：Composite matrix
Multiplication unit 1, composite matrix multiplication unit 2, constant add unit 1, constant plus unit 2, constant plus unit 3, constant plus unit 4,
Compositum multiplication is against unit, selector 1, selector 2, byte data input port, byte data output port and control signal
Input port, the selector 1 and the selector 2 are one-out-three selector；
The input port of the composite matrix multiplication unit 1 is connected with byte data input port；Composite matrix multiplication
The output end P of unit 1A, output end PV, output end PSInput, constant respectively with selector 1 add unit 1 input, often
The input of number plus unit 2 connects one to one；The constant add unit 1 output end and constant plus unit 2 output end it is equal
It is connected with the input of selector 1；The output end of the selector 1 is connected with the input of compositum multiplication against unit；Institute
The output end for stating compositum multiplication against unit is connected with the input of composite matrix multiplication unit 2；The composite matrix multiplication
The output end P of unit 2A, output end PV, output end PSAdd the input of unit 3, the input of selector 2, often with constant respectively
The input of number plus unit 4 connects one to one；The constant adds the output end and constant of unit 3 plus the output end point of unit 4
It is not connected with the input of selector；The output end of the selector 2 is connected with byte number exit port；The selector 1
It is connected with the selection end of selector 2 with control signal input mouthful；
The Reconfigurable S-box circuit structure has three mode of operations：AES encryption S boxes mode of operation, AES decryption S box works
Operation mode and SM4S box mode of operations；Under the control of selection signal, selector 1 and selector 2 select different signals respectively
Passage, so as to realize the different mode of operation of Reconfigurable S-box；Under AES encryption S box mode of operations, the output synthesis square of selector 1
The output end P of battle array multiplication unit 1AOn operation result, the output constant of selector 2 adds the operation result of unit 3；S is decrypted in AES
Under box mode of operation, the output constant of selector 1 adds the operation result of unit 1, the output composite matrix of selector 2 multiplication unit 2
Output end PVOn operation result；Under SM4S box mode of operations, the output constant of selector 1 adds the operation result of unit 2, selection
The output constant of device 2 adds the operation result of unit 4；The control signal is inputted by control signal input mouthful.
It is preferred that, described composite matrix multiplication unit 1 realize composite matrix multiplying Φ ×；Described composite matrix
Φ is by the constant matrices D in AES encryption S boxesA, AES decryption S boxes in constant matrices Q'A, constant matrices R in SM4S boxesSGroup
Conjunction is formed；The output end P of composite matrix multiplication unit 1A, output end PVWith output end PSDifference output constant matrix multiplication DA×
Operation result, constant matrices multiplication Q'A× operation result and constant matrices multiplication RS× operation result；
Described composite matrix multiplication unit 2 realize composite matrix multiplying Ψ ×；Described composite matrix Ψ is by AES
Encrypt the constant matrices Q in S boxesA, AES decryption S boxes in constant matrices D'A, constant matrices Q in SM4S boxesSCombine；
The output end P of composite matrix multiplication unit 2A, output end PVWith output end PSDifference output constant matrix multiplication QA× computing knot
Really, constant matrices multiplication D'A× operation result and constant matrices multiplication QS× operation result；
Described constant adds unit 1 to realize the additive constant d in AES decryption S boxesAComputing；
Described constant adds unit 2 to realize the additive constant d in SM4S boxesSComputing；
Described constant adds unit 3 to realize the additive constant c in AES encryption S boxesAComputing；
Described constant adds unit 4 to realize the additive constant c in SM4S boxesSComputing；
Described compositum multiplication realizes input byte in compositum comultiplication inverse operation against unit.
It is preferred that, described constant dAThe constant c in S boxes is decrypted for AESAWith constant matrices Q'AProduct；
Described constant dSFor the constant c in SM4S boxesSWith constant matrices DSProduct；
Described constant cAFor the constant vector in the Affine arithmetic specified in AES cryptographic algorithms；
Described constant cSFor the constant vector in the Affine arithmetic specified in SM4 cryptographic algorithms；
Described constant matrices Q'AFor constant matrices DAWith constant matrices M'AProduct；
Described constant matrices RSFor constant matrices DSWith constant matrices MSProduct；
Described constant matrices QAFor constant matrices MAWith constant matrices D'AProduct；
Described constant matrices QSFor constant matrices MSWith constant matrices D'SProduct；
Described constant matrices DAFor mapping matrix, it is the GF (2 that will be specified in AES cryptographic algorithms that it, which is acted on,8) member on domain
Element is mapped on target compositum；
Described constant matrices D'AFor mapping matrix, it is that the element on target compositum is mapped into AES is close that it, which is acted on,
The GF (2 specified in code algorithm8) on domain；
Described constant matrices DSFor mapping matrix, it is the GF (2 that will be specified in SM4 cryptographic algorithms that it, which is acted on,8) member on domain
Element is mapped on target compositum；
Described constant matrices D'SFor mapping matrix, its effect is that the element on target compositum is mapped into SM4 passwords
The GF (2 specified in algorithm8) on domain；
Described constant matrices MAFor the constant matrices in the encryption flow Affine arithmetic specified in AES cryptographic algorithms；
Described constant matrices M'AFor the constant matrices in the decryption flow Affine arithmetic specified in AES cryptographic algorithms；
Described constant matrices MSFor the constant matrices in the Affine arithmetic specified in SM4 cryptographic algorithms；
Described compositum for arbitrarily with GF (28) domain isomorphism compositum.
The Reconfigurable S-box circuit structure that the utility model is provided, by being multiplexed compositum multiplication against unit mode, is realized
The reconfigurable function of the computing of AES encryption S boxes, AES decryption S boxes computings and SM4S box computings.The inverse multiplexing of compositum multiplication can be with
Circuit area is greatly reduced, while the composite matrix structure in Reconfigurable S-box is conducive to the raising of circuit optimization efficiency, so that
Further reduce circuit area.
Brief description of the drawings
Fig. 1 is the Reconfigurable S-box electrical block diagram of the utility model embodiment；
Fig. 2 is the Reconfigurable S-box circuit structure of the utility model embodiment under AES encryption S box mode of operations
Schematic diagram；
Fig. 3 is decrypted under S box mode of operations for the Reconfigurable S-box circuit structure of the utility model embodiment in AES
Schematic diagram；
Fig. 4 is Reconfigurable S-box circuit structure the showing under SM4S box mode of operations of the utility model embodiment
It is intended to.
Embodiment
The embodiment of the Reconfigurable S-box circuit structure provided below in conjunction with the accompanying drawings the utility model is done specifically
It is bright.
Present embodiment provides a kind of Reconfigurable S-box circuit structure, and Fig. 1 is the utility model embodiment
Reconfigurable S-box electrical block diagram.Reconfigurable S-box circuit structure described in present embodiment, it is possible to achieve be based on
AES encryption S boxes, the AES of compositum decrypt the reconfigurable function of the computing such as S boxes and SM4S boxes.Fig. 2 is that the utility model is specifically real
Apply schematic diagram of the Reconfigurable S-box circuit structure of mode under AES encryption S box mode of operations；Fig. 3 is that the utility model is specifically real
The Reconfigurable S-box circuit structure for applying mode decrypts the schematic diagram under S box mode of operations in AES；Fig. 4 is that the utility model is specifically real
Apply schematic diagram of the Reconfigurable S-box circuit structure of mode under SM4S box mode of operations.
As shown in figure 1, the Reconfigurable S-box circuit structure that present embodiment is proposed includes：Composite matrix multiplication unit
1st, constant adds unit 1, constant plus unit 2, selector 1, compositum multiplication to add list against unit, composite matrix multiplication unit 2, constant
Member 3, constant add unit 4, selector 2, wherein, the selector 1 and the selector 2 are one-out-three selector.
Circuit structure also includes：One byte data input port, a byte data output port and a control letter
Number input port.
The input port of the composite matrix multiplication unit 1 is connected with byte data input port；Composite matrix multiplication
The output end P of unit 1A, output end PV, output end PSAn input, the constant with selector 1 add the input of unit 1 respectively
End, constant add the input of unit 2 to connect one to one；Constant adds the output end and constant of unit 1 plus the output end point of unit 2
It is not connected with an input of selector 1；The output end of selector 1 is connected with the input of compositum multiplication against unit
Connect；The output end of compositum multiplication against unit is connected with the input of composite matrix multiplication unit 2；Composite matrix multiplication unit
2 output end PA, output end PV, output end PSAdd the input of unit 3, an input of selector 2, often with constant respectively
The input of number plus unit 4 connects one to one；Constant add unit 3 output end and constant plus unit 4 output end respectively with
One input of selector is connected；The output end of selector 2 is connected with byte number exit port；Selector 1 and selector 2
Selection end and control signal input mouthful be connected.
Composite matrix multiplication unit 1 realize composite matrix multiplying Φ ×, composite matrix Φ is in AES encryption S boxes
Constant matrices DA, AES decryption S boxes in constant matrices Q'A, constant matrices R in SM4S boxesSCombine, i.e.,
The output end P of composite matrix multiplication unit 1A, output end PVWith output end PSDifference output constant matrix multiplication DA
× operation result, constant matrices multiplication Q'A× operation result and constant matrices multiplication RS× operation result.
Composite matrix multiplication unit 2 realize composite matrix multiplying Ψ ×, composite matrix Ψ is in AES encryption S boxes
Constant matrices QA, AES decryption S boxes in constant matrices D'A, constant matrices Q in SM4S boxesSCombine, i.e.,
The output end P of the composite matrix multiplication unit 2A, output end PVWith output end PSDifference output constant matrix multiplication
QA× operation result, constant matrices multiplication D'A× operation result and constant matrices multiplication QS× operation result.
The constant adds unit 1 to realize the additive constant d in AES decryption S boxesAComputing, constant adds unit 2 to realize in SM4S boxes
Additive constant dSComputing, constant adds unit 3 to realize the additive constant c in AES encryption S boxesAComputing, constant adds unit 4 to realize SM4S boxes
In additive constant cSComputing.Compositum multiplication realizes input byte in compositum comultiplication inverse operation against unit.
Reconfigurable S-box circuit shown in Fig. 1 has three kinds of mode of operations：AES encryption S boxes mode of operation, AES decryption S box works
Operation mode and SM4S box mode of operations.
AES encryption S box mode of operations are as shown in Figure 2.Under AES encryption S box mode of operations, Reconfigurable S-box inputs one
Byte vector x, the byte vector x of input initially enters composite matrix multiplication unit 1 and carries out composite matrix multiplying, i.e.,
Operation result DAThe output port Ps of × x from composite matrix multiplication unit 1AOutput, operation result Q'A× x is from synthesis
The output port P of matrix multiplication unit 1VOutput, operation result RSThe output port Ps of × x from composite matrix multiplication unit 1SIt is defeated
Go out.Selector 1 selects P under selection signal controlAOperation result D on portA× x is output to compositum multiplication against unit, warp
Cross compositum multiplication and further input into composite matrix multiplication unit 2 and carry out against operation result, operation result is exported after unit
Composite matrix multiplying, i.e.,
Operation resultFrom the output port P of composite matrix multiplication unit 2AOutput, operation resultFrom the output port P of composite matrix multiplication unit 2VOutput, operation resultFrom conjunction
Into the output port P of matrix multiplication unit 2SOutput.Wherein PAOperation result on portFurther enter
Enter and additive constant c is carried out in constant plus unit 3AComputing, operation result is, selector 2 is in selection letter
By operation result under number controlFrom the output of byte data output port.Knowable to contrast equation (5),
The operation result is AES encryption S box operation results SA(x).The selection signal of selector 1 and selector 2 is defeated from control signal
Inbound port is inputted.
AES decryption S box mode of operations are as shown in Figure 3.Under AES decryption S box mode of operations, Reconfigurable S-box inputs one
Byte vector x, the byte vector x of input initially enters composite matrix multiplication unit 1 and carries out composite matrix multiplying, i.e.,
Operation result DAThe output port Ps of × x from composite matrix multiplication unit 1AOutput, operation result Q'A× x is from synthesis
The output port P of matrix multiplication unit 1VOutput, operation result RSThe output port Ps of × x from composite matrix multiplication unit 1SIt is defeated
Go out.Wherein PVOperation result Q' on portA× x, which is further input into, carries out additive constant d in constant plus unit 1AComputing, computing
As a result it is Q'A×x+dA.The selectivity constant under selection signal control of selector 1 adds the operation result Q' of unit 1A×x+dAOutput
To compositum multiplication against unit, by compositum multiplication against exporting operation result after unitOperation result
Progress composite matrix multiplying in composite matrix multiplication unit 2 is further input into, i.e.,
Operation resultFrom the output port P of composite matrix multiplication unit 2AOutput, computing knot
ReallyFrom the output port P of composite matrix multiplication unit 2VOutput, operation resultFrom the output port P of composite matrix multiplication unit 2SOutput.Selector 2 is under selection signal control
By PVOperation result on portFrom the output of byte data output port.Contrast equation (7) can
Know, the operation result is AES decryption S box operation results S'A(x).The selection signal of selector 1 and selector 2 is believed from control
The input of number input port.
SM4S box mode of operations are as shown in Figure 4.Under SM4S box mode of operations, Reconfigurable S-box inputs a byte vector
X, the byte vector x of input initially enters composite matrix multiplication unit 1 and carries out composite matrix multiplying, i.e.,
Operation result DAThe output port Ps of × x from composite matrix multiplication unit 1AOutput, operation result Q'A× x is from synthesis
The output port P of matrix multiplication unit 1VOutput, operation result RSThe output port Ps of × x from composite matrix multiplication unit 1SIt is defeated
Go out.Wherein PSOperation result R on portS× x, which is further input into, carries out additive constant d in constant plus unit 2SComputing, computing knot
Fruit is RS×x+dS.The selectivity constant under selection signal control of selector 1 adds the operation result R of unit 2S×x+dSIt is output to multiple
Domain multiplication is closed against unit, by compositum multiplication against exporting operation result after unitOperation result enters one
Step is input to progress composite matrix multiplying in composite matrix multiplication unit 2, i.e.,
Operation resultFrom the output port P of composite matrix multiplication unit 2AOutput, computing knot
ReallyFrom the output port P of composite matrix multiplication unit 2VOutput, operation resultFrom the output port P of composite matrix multiplication unit 2SOutput.Wherein PSOperation result on portFurther input into and additive constant c is carried out in constant plus unit 4SComputing, operation result isSelector 2 adds constant under selection signal control the operation result of unit 4From the output of byte data output port.Contrast equation (9) understands that the operation result is
AES decryption S box operation results SS(x).The selection signal of selector 1 and selector 2 is inputted from control signal input mouthful.
The Reconfigurable S-box circuit structure that the utility model is provided, by being multiplexed compositum multiplication against unit mode, is realized
The reconfigurable function of the computing of AES encryption S boxes, AES decryption S boxes computings and SM4S box computings.The inverse multiplexing of compositum multiplication can be with
Circuit area is greatly reduced, while the composite matrix structure in Reconfigurable S-box is conducive to the raising of circuit optimization efficiency, so that
Further reduce circuit area.
Described above is only preferred embodiment of the present utility model, it is noted that for the common skill of the art
Art personnel, on the premise of the utility model principle is not departed from, can also make some improvements and modifications, these improvements and modifications
Also it should be regarded as protection domain of the present utility model.
Claims (3)
1. a kind of Reconfigurable S-box circuit structure, it is characterised in that including：Composite matrix multiplication unit 1, composite matrix multiplication list
Member 2, constant add unit 1, constant plus unit 2, constant plus unit 3, constant plus unit 4, compositum multiplication against unit, selector 1,
Selector 2, byte data input port, byte data output port and control signal input mouthful, the selector 1 and described
Selector 2 is one-out-three selector；
The input port of the composite matrix multiplication unit 1 is connected with byte data input port；Composite matrix multiplication unit 1
Output end PA, output end PV, output end PSInput, constant respectively with selector 1 adds the input of unit 1, constant to add list
The input of member 2 connects one to one；The constant add unit 1 output end and constant plus unit 2 output end with selection
The input connection of device 1；The output end of the selector 1 is connected with the input of compositum multiplication against unit；It is described compound
The output end of domain multiplication against unit is connected with the input of composite matrix multiplication unit 2；The composite matrix multiplication unit 2
Output end PA, output end PV, output end PSAdd input, the input of selector 2, constant plus the unit of unit 3 with constant respectively
4 input connects one to one；The constant add unit 3 output end and constant plus unit 4 output end respectively with selection
The input of device is connected；The output end of the selector 2 is connected with byte number exit port；The selector 1 and selector 2
Selection end and control signal input mouthful be connected；
The Reconfigurable S-box circuit structure has three mode of operations：AES encryption S boxes mode of operation, AES decryption S box Working moulds
Formula and SM4S box mode of operations；Under the control of selection signal, selector 1 and selector 2 select different signalling channels respectively,
So as to realize the different mode of operation of Reconfigurable S-box；Under AES encryption S box mode of operations, the output composite matrix of selector 1 multiplies
The output end P of method unit 1AOn operation result, the output constant of selector 2 adds the operation result of unit 3；S box works are decrypted in AES
Under operation mode, the output constant of selector 1 adds the operation result of unit 1, the output of the output composite matrix of selector 2 multiplication unit 2
Hold PVOn operation result；Under SM4S box mode of operations, the output constant of selector 1 adds the operation result of unit 2, selector 2
Output constant adds the operation result of unit 4；The control signal is inputted by control signal input mouthful.
2. Reconfigurable S-box circuit structure according to claim 1, it is characterised in that described composite matrix multiplication unit 1 is real
Existing composite matrix multiplying Φ ×；Described composite matrix Φ is by the constant matrices D in AES encryption S boxesA, AES decryption S boxes
In constant matrices Q'A, constant matrices R in SM4S boxesSCombine；The output end P of composite matrix multiplication unit 1A, output
Hold PVWith output end PSDifference output constant matrix multiplication DA× operation result, constant matrices multiplication Q'A× operation result and
Constant matrices multiplication RS× operation result；
Described composite matrix multiplication unit 2 realize composite matrix multiplying Ψ ×；Described composite matrix Ψ is by AES encryption
Constant matrices Q in S boxesA, AES decryption S boxes in constant matrices D'A, constant matrices Q in SM4S boxesSCombine；Synthesis
The output end P of matrix multiplication unit 2A, output end PVWith output end PSDifference output constant matrix multiplication QA× operation result,
Constant matrices multiplication D'A× operation result and constant matrices multiplication QS× operation result；
Described constant adds unit 1 to realize the additive constant d in AES decryption S boxesAComputing；
Described constant adds unit 2 to realize the additive constant d in SM4S boxesSComputing；
Described constant adds unit 3 to realize the additive constant c in AES encryption S boxesAComputing；
Described constant adds unit 4 to realize the additive constant c in SM4S boxesSComputing；
Described compositum multiplication realizes input byte in compositum comultiplication inverse operation against unit.
3. Reconfigurable S-box circuit structure according to claim 2, it is characterised in that described constant dAFor in AES decryption S boxes
Constant cAWith constant matrices Q'AProduct；
Described constant dSFor the constant c in SM4S boxesSWith constant matrices DSProduct；
Described constant cAFor the constant vector in the Affine arithmetic specified in AES cryptographic algorithms；
Described constant cSFor the constant vector in the Affine arithmetic specified in SM4 cryptographic algorithms；
Described constant matrices Q'AFor constant matrices DAWith constant matrices M'AProduct；
Described constant matrices RSFor constant matrices DSWith constant matrices MSProduct；
Described constant matrices QAFor constant matrices MAWith constant matrices D'AProduct；
Described constant matrices QSFor constant matrices MSWith constant matrices D'SProduct；
Described constant matrices DAFor mapping matrix, it is the GF (2 that will be specified in AES cryptographic algorithms that it, which is acted on,8) element on domain reflects
It is mapped on target compositum；
Described constant matrices D'AFor mapping matrix, its effect is that the element on target compositum is mapped into AES cryptographic algorithms
In the GF (2 that specifies8) on domain；
Described constant matrices DSFor mapping matrix, it is the GF (2 that will be specified in SM4 cryptographic algorithms that it, which is acted on,8) element on domain reflects
It is mapped on target compositum；
Described constant matrices D'SFor mapping matrix, its effect is that the element on target compositum is mapped into SM4 cryptographic algorithms
In the GF (2 that specifies8) on domain；
Described constant matrices MAFor the constant matrices in the encryption flow Affine arithmetic specified in AES cryptographic algorithms；
Described constant matrices M'AFor the constant matrices in the decryption flow Affine arithmetic specified in AES cryptographic algorithms；
Described constant matrices MSFor the constant matrices in the Affine arithmetic specified in SM4 cryptographic algorithms；
Described compositum for arbitrarily with GF (28) domain isomorphism compositum.
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| CN201720193909.2U CN206585573U (en) | 2017-03-01 | 2017-03-01 | reconfigurable S-box circuit structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921487A (en) * | 2017-03-01 | 2017-07-04 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure |
| CN108809627A (en) * | 2018-06-11 | 2018-11-13 | 安徽工程大学 | Round transformation multiplex circuit and AES decrypt circuit |
| CN109033023A (en) * | 2018-06-11 | 2018-12-18 | 安徽工程大学 | A kind of ordinary wheel transform operation unit, ordinary wheel translation circuit and AES encryption circuit |
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2017
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921487A (en) * | 2017-03-01 | 2017-07-04 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure |
| CN106921487B (en) * | 2017-03-01 | 2023-09-15 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure |
| CN108809627A (en) * | 2018-06-11 | 2018-11-13 | 安徽工程大学 | Round transformation multiplex circuit and AES decrypt circuit |
| CN109033023A (en) * | 2018-06-11 | 2018-12-18 | 安徽工程大学 | A kind of ordinary wheel transform operation unit, ordinary wheel translation circuit and AES encryption circuit |
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