CN105577363A - Extensible pipelined circuit aiming at SM4 cryptographic algorithm and implementation method thereof - Google Patents
Extensible pipelined circuit aiming at SM4 cryptographic algorithm and implementation method thereof Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
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Abstract
The invention discloses an extensible pipelined circuit aiming at an SM4 cryptographic algorithm and an implementation method thereof. According to the invention, an encryption and decryption iterative operation and a key extending algorithm are implemented through an SM4 algorithm core array, the SM4 algorithm core array comprises N/4 SM4 algorithm cores, each SM4 algorithm core performs loop iteration 32 times to finish encryption/decryption of 128 bits of data, the N/4 SM4 algorithm cores perform parallel execution, the number of the SM4 algorithm cores is regulated according to I/O bit width, and given that the I/O bit width is N, so the number of the algorithm cores in the structure is N/4. According to the invention, encryption/decryption of the SM4 algorithm can be executed in a pipelined form, and a circuit structure can be regulated according to I/O interfaces with different bit widths.
Description
Technical field:
The present invention relates to information security technology and integrated circuit (IC) design field, particularly relate to a kind of Extensible pipeline circuit for SM4 cryptographic algorithm and its implementation.
Background technology:
SM4 algorithm and former SMS4 algorithm, be the grouping symmetric cryptographic algorithm for Wireless LAN Equipments announced in January, 2006 by national commercial cipher management office, be approved as industry standard in March, 2012 by national Password Management office.
SM4 algorithm is a kind of block cipher, and its block length and key length are 128 bits.Be three parts by this algorithm partition in SM4 algorithm standard rules: cryptographic algorithm, decipherment algorithm and key schedule.Cryptographic algorithm is made up of 32 interative computations and 1 antitone mapping, and each interative computation needs loading one group of round key in round function.Decipherment algorithm is identical with cryptographic algorithm structure, and difference is only the use order of round key.The round key of algorithms for encryption and decryption needed in interative computation is provided by key schedule.
The realization of SM4 algorithm can be summarized as two classes: software simulating and hardware implementing.The software realization mode speed of service is slow, and fail safe is poor.The hardware implementation mode speed of service is fast, and fail safe is high.The existing hardware circuit mode of circulation that adopts realizes 32 iteration more, and namely the data of one group of 128 bit are not before completing 32 iteration, do not allow to be loaded into new data, and this just causes throughput lower.But, if 32 iteration launched completely, although very high throughput can be obtained, larger area overhead can be brought again.
Summary of the invention:
The object of the invention is to provide a kind of Extensible pipeline circuit for SM4 cryptographic algorithm and its implementation for above-mentioned Problems existing, both can provide higher throughput, and larger area expense can not be brought again.
Above-mentioned object is realized by following technical scheme:
For an Extensible pipeline circuit for SM4 cryptographic algorithm, it at least comprises: data allocations and enable signal generation module (S102), SM4 algorithm core array (S104) and data output buffer module (S105);
128 Bit datas are assigned among each SM4 algorithm core array (S104) by described data allocations and enable signal generation module (S102) in turn;
Described SM4 algorithm core array (S104) is for realizing encryption and decryption interative computation and key schedule, described SM4 algorithm core array (S104) comprises N/4 SM4 algorithm core, wherein the 1st core (S106) be cipher key spreading and encryption and decryption hardware circuit on multiplexing, for realizing cipher key spreading or realizing encryption and decryption; 2nd ~ N/4 SM4 algorithm core (S107) is only for realizing encryption and decryption;
Described data output buffer module (S105) is for exporting the encryption and decryption result of 128 bits.
The described Extensible pipeline circuit for SM4 cryptographic algorithm, also comprise input data buffering module (S101), described input data buffering module (S101) for being spliced into the data of 128 bits after 128/N cycle by the N inputted continuously Bit data, wherein N equals 8 or 16 or 32 or 64.
The described Extensible pipeline circuit for SM4 cryptographic algorithm, also comprises state of a control machine (S103), described state of a control machine (S103) for control whole circuit operating state and to circuit external output status signal.
The described Extensible pipeline circuit for SM4 cryptographic algorithm, described data allocations and enable signal generation module (S102) are made up of a shift register and two counter A sum counter B: described shift register is for generating the enable signal of SM4 algorithm core, there is N/4 output, the corresponding SM4 algorithm core of each output;
Described counter A bit wide is log
2 (128/N)bit, count value, from 0 to 128/N-1, is spliced into the clock periodicity of 128 bits for control N Bit data; Described counter B bit wide is log
2 (N/4)bit, count value is from 0 to N/4-1.
The implementation method of the above-mentioned Extensible pipeline circuit for SM4 cryptographic algorithm: the method is: adopt SM4 algorithm core array (S104) to realize encryption and decryption interative computation and key schedule, described SM4 algorithm core array (S104) comprises N/4 SM4 algorithm core, each SM4 algorithm core loop iteration completes the enciphering/deciphering of 128 Bit datas for 32 times, N/4 SM4 algorithm core executed in parallel, the number of described SM4 algorithm core adjusts according to I/O bit wide, if I/O bit wide is N, the algorithm check figure so comprised in structure is N/4, specifically: be that the input data of N are after 128/N cycle by bit wide, splicing becomes the data of 128 bits, then be assigned in N/4 SM4 algorithm core in turn successively, make the data being assigned to each algorithm core all can keep 32 cycles, and 128 Bit datas being assigned to adjacent two algorithm cores stagger 128/N cycle each other, making to input data can without the need to the continuous transmission waited for, similarly, the result of calculation of adjacent two algorithm cores staggers 128/N cycle, each result of calculation just in time needs 128/N cycle to complete output, making to export data also can without the need to the continuous transmission waited for, 32 cycles that the data being assigned to each algorithm core keep, to be just in time SM4 algorithm core completed time needed for 128 Bit data enciphering/decipherings by 32 iteration, transfer of data and enciphering/deciphering define overlapping in time, streamline executive mode without the need to waiting for is achieved.
Accompanying drawing illustrates:
Fig. 1 SM4 algorithm provided by the invention pipeline organization schematic diagram;
The state of a control transition diagram of Fig. 2 SM4 algorithm provided by the invention pipeline organization design;
Embodiment:
For making object of the present invention, technical scheme and a little clearly understanding, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The invention provides a kind of Extensible pipeline circuit for SM4 cryptographic algorithm, as shown in Figure 1, specifically comprise: input data buffering module S101, data allocations and enable signal generation module S102, state of a control machine S103, SM4 algorithm core array S104 and data output buffer S105.Wherein, inputting data buffering module S101 and the N(N inputted continuously equaled 8,16,32,64) Bit data is spliced into the data of 128 bits after 128/N cycle; 128 Bit datas that input buffer exports by data allocations and enable signal generation module S102 are assigned among each SM4 algorithm core in turn, and provide enable signal for each SM4 algorithm core; State of a control machine S103 for control whole circuit operating state and to circuit external output status signal; SM4 algorithm core array S104 is used for realizing encryption and decryption interative computation and key schedule; The encryption and decryption result of 128 bits becomes the data of 128/N N bit to export continuously through 128/N period divisions by data output buffer S105.
As shown in Figure 2, state of a control machine S103 comprises 4 states, specifically comprises: idle S201, cipher key spreading S202, enciphering/deciphering S203 and ending S204.Being described below of each state:
Idle phase S201: after circuit " enable " signal sets high, enter idle phase, then waits for that " starting working " signal sets high.
Cipher key spreading stage S202: after " starting working " signal sets high, enter the cipher key spreading stage, " loading request of data " signal is set high, wait for that " starting to be loaded into data " signal sets high, start to be loaded into data, after 128/N cycle, key is loaded into complete, now, external signal " starts to be loaded into data " signal and should drag down.External signal " starts to be loaded into data " while signal drags down, and carry out cipher key spreading, after 32 cycles, cipher key spreading is complete, draws high " cipher key spreading is complete " signal.
Encrypt/decrypt stage S203: after drawing high " cipher key spreading is complete " signal, enter the encryption and decryption stage, waits for that " starting to be loaded into data " starts to be loaded into data continuously after setting high, after 128/N cycle, starts encryption and decryption.After all data loadings are complete, external signal " starts to be loaded into data " and should drag down." loading request of data " drags down after external signal " starts to be loaded into data " step-down.In 128/N+32 the cycle after " starting to be loaded into data " sets high, encryption and decryption result starts to export, and each cycle exports N bit, and Output rusults is along with " exporting data effective " signal set high.
Finishing phase S204: " starting to be loaded into data " signal drags down, show that all data are loaded into complete, now state machine enters finishing phase.After treating that all data encrypting and decipherings complete, draw high signal and " work complete ", state machine returns idle condition after receiving this signal.Now, user can drag down " starting working " signal and circuit " enable " signal.
Data allocations and enable signal generation module S102 are made up of a shift register and two counter A and B.Shift register, for generating the enable signal of SM4 algorithm core, has N/4 output, the corresponding SM4 algorithm core of each output.1st output of shift register is the output that " starting to be loaded into data " signal deposits after 128/N cycle; 2nd exports is the output that " starting to be loaded into data " signal deposits after 2 × 128/N cycle; 3rd exports is the output that " starting to be loaded into data " signal deposits after 3 × 128/N cycle; By that analogy.1st ~ N/4 of shift register export through or computing after, as the enable signal of the 1st SM4 algorithm core; 2nd ~ N/4 of shift register export through or computing after, as the enable signal of the 2nd SM4 algorithm core; 3rd ~ N/4 of shift register export through or computing after, as the enable signal of the 3rd SM4 algorithm core; By that analogy.
Counter A bit wide is log
2 (128/N)bit, count value, from 0 to 128/N-1, is spliced into the clock periodicity of 128 bits for control N Bit data.Counter B bit wide is log
2 (N/4)bit, count value is from 0 to N/4-1.The concrete mode of data allocations is: when the count value of counter A reaches count maximum, shows that the data of 128 bits are ready to, according to the count value that counter B is current, among the data allocations of this 128 bit to the SM4 algorithm core of reference numeral.For the I/O interface of 32 bits, counter A bit wide is 2 bits, and counter B bit wide is 3 bits, if the count value of counter A is 3, counter B count value is 5, so just by the data allocations of 128 bits to the SM4 algorithm core being numbered 5.
Circuit of the present invention is the combination of loop iteration structure and parallel organization.SM4 algorithm core adopts the mode of loop iteration to realize enciphering/deciphering, comprises multiple core, there is not annexation between core and core in SM4 algorithm core array, therefore can executed in parallel.The data of each SM4 algorithm core process take turns flow assignment by data allocations and enable generation module, and the input data of each algorithm core all can keep 32 cycles, make each SM4 algorithm all have time enough to complete 32 iteration.Because the iteration time of SM4 algorithm core is equal with input data hold time, therefore mask the retention time of input data.Although each SM4 algorithm core is the structure of loop iteration, multiple endorse with executed in parallel and input data stagger in time, therefore can realize data processing continuity in time.Combine the continuity of input data again and export the continuity of data, all can carry out with the form of streamline with regard to the work forming whole system.Concrete: SM4 algorithm core array S104 comprises N/4 SM4 algorithm core, there is not annexation between these cores.1st core S106 be cipher key spreading and encryption and decryption hardware circuit on multiplexing, both can realize cipher key spreading, can encryption and decryption be realized again.Key expansion function only just can use when cipher key spreading state, is encryption and decryption functions under other state.2nd ~ N/4 SM4 algorithm core S107 function is completely the same.Each SM4 algorithm core all has an enable signal, only this core be enabled Shi Caihui work.In addition, when cipher key spreading state, only have the work of the 1st SM4 algorithm core, other all do not work.
As shown in Figure 1,2nd ~ N/4 SM4 algorithm core S107 is made up of a data selector, round function and antitone mapping module, and round key needed for round function is provided by the 1st SM4 algorithm core S106.The round function of the 1st SM4 algorithm core S106 multiplexingly can do cipher key spreading, under cipher key spreading state, generates 32 round key and leaves among internal register, and remaining unchanged in calculating afterwards always.
The implementation method of the Extensible pipeline circuit for SM4 cryptographic algorithm of the present invention: the method is: adopt SM4 algorithm core array (S104) to realize encryption and decryption interative computation and key schedule, described SM4 algorithm core array (S104) comprises N/4 SM4 algorithm core, each SM4 algorithm core loop iteration completes the enciphering/deciphering of 128 Bit datas for 32 times, N/4 SM4 algorithm core executed in parallel, the number of described SM4 algorithm core adjusts according to I/O bit wide, if I/O bit wide is N, the algorithm check figure so comprised in structure is N/4, specifically: be that the input data of N are after 128/N cycle by bit wide, splicing becomes the data of 128 bits, then be assigned in N/4 SM4 algorithm core in turn successively, make the data being assigned to each algorithm core all can keep 32 cycles, and 128 Bit datas being assigned to adjacent two algorithm cores stagger 128/N cycle each other, making to input data can without the need to the continuous transmission waited for, similarly, the result of calculation of adjacent two algorithm cores staggers 128/N cycle, each result of calculation just in time needs 128/N cycle to complete output, making to export data also can without the need to the continuous transmission waited for, 32 cycles that the data being assigned to each algorithm core keep, to be just in time SM4 algorithm core completed time needed for 128 Bit data enciphering/decipherings by 32 iteration, transfer of data and enciphering/deciphering define overlapping in time, streamline executive mode without the need to waiting for is achieved.
The workflow of whole circuit is described below: after state of a control machine enters cipher key spreading state, cipher key spreading is carried out by the 1st SM4 algorithm core S106, after completing key and being loaded into, complete cipher key spreading through 32 cycles, and send " cipher key spreading is complete " signal.After state machine receives this signal, enter enciphering/deciphering state, carry out data loading and enciphering/deciphering simultaneously.All data be loaded into complete after, enter finishing phase, wait for all data enciphering/decipherings complete and export complete after, end operation also returns idle condition.
Circuit structure easily extensible characteristic description provided by the invention is as follows: circuit structure provided by the invention adopts Parametric designing, and circuit structure can regulate according to the bit wide of I/O interface, specifically as shown in table 1.For 8 bit bit wide I/O interfaces, input data buffering needs 16 cycles that 8 Bit datas inputted continuously are spliced into 128 bits; The number of cores comprised in SM4 algorithm core array is 2, and wherein the 1st kernel reusable does cipher key spreading; The data that it is 8 bits by the Data Segmentation of 128 bits that data output buffer needs through 16 cycles export successively.Other I/O bit wides are similar with it.
The design parameter of table 1 circuit structure
The streamline execution characteristic description of circuit structure provided by the invention is as follows:
Under encryption and decryption state, data are loaded into, data export and enciphering/deciphering is overlapping in time, thus mask data loading and the time required for data output, make to perform from flowing water to be achieved.For 32 bit interface, adopt structure provided by the invention can realize each clock cycle parallel processing 1 32 Bit data.
Claims (6)
1. for an Extensible pipeline circuit for SM4 cryptographic algorithm, it is characterized in that, it at least comprises: data allocations and enable signal generation module (S102), SM4 algorithm core array (S104) and data output buffer module (S105);
128 Bit datas are assigned among each SM4 algorithm core array (S104) by described data allocations and enable signal generation module (S102) in turn;
Described SM4 algorithm core array (S104) is for realizing encryption and decryption interative computation and key schedule, described SM4 algorithm core array (S104) comprises N/4 SM4 algorithm core, wherein the 1st core (S106) be cipher key spreading and encryption and decryption hardware circuit on multiplexing, for realizing cipher key spreading or realizing encryption and decryption; 2nd ~ N/4 SM4 algorithm core (S107) is only for realizing encryption and decryption;
Described data output buffer module (S105) is for exporting the encryption and decryption result of 128 bits.
2. the Extensible pipeline circuit for SM4 cryptographic algorithm according to claim 1, it is characterized in that, described circuit also comprises input data buffering module (S101), described input data buffering module (S101) for being spliced into the data of 128 bits after 128/N cycle by the N inputted continuously Bit data, wherein N equals 8 or 16 or 32 or 64.
3. the Extensible pipeline circuit for SM4 cryptographic algorithm according to claim 1 and 2, it is characterized in that, described circuit also comprises state of a control machine (S103), described state of a control machine (S103) for control whole circuit operating state and to circuit external output status signal.
4. the Extensible pipeline circuit for SM4 cryptographic algorithm according to claim 1 and 2, it is characterized in that, described data allocations and enable signal generation module (S102) are made up of a shift register and two counter A sum counter B: described shift register is for generating the enable signal of SM4 algorithm core, there is N/4 output, the corresponding SM4 algorithm core of each output;
Described counter A bit wide is log
2 (128/N)bit, count value, from 0 to 128/N-1, is spliced into the clock periodicity of 128 bits for control N Bit data; Described counter B bit wide is log
2 (N/4)bit, count value is from 0 to N/4-1.
5. the Extensible pipeline circuit for SM4 cryptographic algorithm according to claim 3, it is characterized in that, described data allocations and enable signal generation module (S102) are made up of a shift register and two counter A sum counter B: described shift register is for generating the enable signal of SM4 algorithm core, there is N/4 output, the corresponding SM4 algorithm core of each output;
Described counter A bit wide is log
2 (128/N)bit, count value, from 0 to 128/N-1, is spliced into the clock periodicity of 128 bits for control N Bit data; Described counter B bit wide is log
2 (N/4)bit, count value is from 0 to N/4-1.
6. the implementation method of the Extensible pipeline circuit for SM4 cryptographic algorithm that one of claim 1-5 is described: it is characterized in that: the method is: adopt SM4 algorithm core array (S104) to realize encryption and decryption interative computation and key schedule, described SM4 algorithm core array (S104) comprises N/4 SM4 algorithm core, each SM4 algorithm core loop iteration completes the enciphering/deciphering of 128 Bit datas for 32 times, N/4 SM4 algorithm core executed in parallel, the number of described SM4 algorithm core adjusts according to I/O bit wide, if I/O bit wide is N, the algorithm check figure so comprised in structure is N/4, specifically: be that the input data of N are after 128/N cycle by bit wide, splicing becomes the data of 128 bits, then be assigned in N/4 SM4 algorithm core in turn successively, make the data being assigned to each algorithm core all can keep 32 cycles, and 128 Bit datas being assigned to adjacent two algorithm cores stagger 128/N cycle each other, making to input data can without the need to the continuous transmission waited for, similarly, the result of calculation of adjacent two algorithm cores staggers 128/N cycle, each result of calculation just in time needs 128/N cycle to complete output, making to export data also can without the need to the continuous transmission waited for, 32 cycles that the data being assigned to each algorithm core keep, to be just in time SM4 algorithm core completed time needed for 128 Bit data enciphering/decipherings by 32 iteration, transfer of data and enciphering/deciphering define overlapping in time, streamline executive mode without the need to waiting for is achieved.
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| CN107612683A (en) * | 2017-09-30 | 2018-01-19 | 上海众人网络安全技术有限公司 | A kind of encipher-decipher method, device, system, equipment and storage medium |
| CN109617671A (en) * | 2018-12-21 | 2019-04-12 | 成都海光集成电路设计有限公司 | Encryption and decryption, extended method and device, encrypting and deciphering system, terminal |
| CN109981250A (en) * | 2019-03-01 | 2019-07-05 | 北京海泰方圆科技股份有限公司 | A kind of SM4 encryption, cipher key spreading method, apparatus, equipment and medium |
| CN111612622A (en) * | 2020-05-20 | 2020-09-01 | 深圳比特微电子科技有限公司 | Circuit and method for implementing a hashing algorithm |
| CN111625202A (en) * | 2020-07-28 | 2020-09-04 | 上海聪链信息科技有限公司 | Algorithm extension customizing method and system of block chain chip |
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| CN107612683A (en) * | 2017-09-30 | 2018-01-19 | 上海众人网络安全技术有限公司 | A kind of encipher-decipher method, device, system, equipment and storage medium |
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| CN109617671A (en) * | 2018-12-21 | 2019-04-12 | 成都海光集成电路设计有限公司 | Encryption and decryption, extended method and device, encrypting and deciphering system, terminal |
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| CN111625202A (en) * | 2020-07-28 | 2020-09-04 | 上海聪链信息科技有限公司 | Algorithm extension customizing method and system of block chain chip |
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