CN111625202B - Algorithm extension customizing method and system of block chain chip - Google Patents
Algorithm extension customizing method and system of block chain chip Download PDFInfo
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- CN111625202B CN111625202B CN202010734485.2A CN202010734485A CN111625202B CN 111625202 B CN111625202 B CN 111625202B CN 202010734485 A CN202010734485 A CN 202010734485A CN 111625202 B CN111625202 B CN 111625202B
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Abstract
An algorithm expansion customization method of a blockchain chip comprises the following steps: reading binary numbers written into the blockchain chip in advance when the blockchain chip executes the algorithm flow; calculating the binary number and an output value of the first sub-algorithm flow to obtain a calculated value; inputting the operation value into a second sub-algorithm process as an input value of the second sub-algorithm process; the first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip. The invention can expand and customize the original algorithm on the block chain chip, reduces the cost, improves the efficiency, increases the value-added benefit for customers with stronger timeliness requirements, and simultaneously, chip development enterprises can avoid secondary development.
Description
Technical Field
The invention relates to the technical field of a block chain, in particular to an algorithm expansion customization method and system for a block chain chip.
Background
In order to improve the operational performance of the blockchain service, enterprises develop various high-performance operational chips which are based on corresponding algorithms and are used for running on a blockchain server, however, the blockchain chips only work based on a certain single algorithm, the expansibility is poor, if the algorithm is required to be expanded into a variant algorithm, the enterprises need to perform secondary development, and customers need to buy chips again, so that the cost is high, the efficiency is low, the time consumption is long, and the value-added benefits of the customers with strong timeliness requirements can be reduced.
Disclosure of Invention
Based on this, in order to solve the above technical problem, a block chain chip algorithm expansion customizing method and system thereof are provided.
In order to solve the technical problems, the invention adopts the following technical scheme:
an algorithm expansion customization method of a blockchain chip comprises the following steps:
reading binary numbers written into the blockchain chip in advance when the blockchain chip executes the algorithm process, wherein the algorithm process comprises a plurality of sub-algorithm processes;
calculating the binary number and an output value of the first sub-algorithm flow to obtain a calculated value;
inputting the calculated value into a second sub-algorithm process as an input value of the second sub-algorithm process for calculation, so that the output value of the second sub-algorithm process is different from the original output value;
the first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
Writing a binary number to the block chain chip in advance includes:
and after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as binary number, wherein the low level is 0, and the high level is 1.
Writing a binary number to the block chain chip in advance includes:
and burning the binary number into a one-time programmable memory of the block chain chip.
The binary number is 12-bit data, and writing the binary number to the block chain chip in advance comprises:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as 4-bit data;
burning 4-bit data into a one-time programmable memory of the block chain chip;
configuring 4-bit data to a register of the block chain chip;
and combining the 3 4-bit data into 12-bit data according to a preset sequence.
The 3 pieces of 4-bit data are combined into 12-bit data in order from left to right.
The invention also relates to an algorithm expansion customization system of the blockchain chip, which comprises a storage module arranged in the blockchain chip, wherein the storage module comprises a plurality of instructions loaded and executed by a processing module of the blockchain chip:
reading binary numbers written into the blockchain chip in advance when the blockchain chip executes the algorithm process, wherein the algorithm process comprises a plurality of sub-algorithm processes;
calculating the binary number and an output value of the first sub-algorithm flow to obtain a calculated value;
inputting the calculated value into a second sub-algorithm process as an input value of the second sub-algorithm process for calculation, so that the output value of the second sub-algorithm process is different from the original output value;
the first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
Writing a binary number to the block chain chip in advance includes:
and after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as binary number, wherein the low level is 0, and the high level is 1.
Writing a binary number to the block chain chip in advance includes:
and burning the binary number into a one-time programmable memory of the block chain chip.
The binary number is 12-bit data, and writing the binary number to the block chain chip in advance comprises:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as 4-bit data;
burning 4-bit data into a one-time programmable memory of the block chain chip;
configuring 4-bit data to a register of the block chain chip;
and combining the 3 4-bit data into 12-bit data according to a preset sequence.
The 3 pieces of 4-bit data are combined into 12-bit data in order from left to right.
The invention can expand and customize the original algorithm on the block chain chip, reduces the cost, improves the efficiency, increases the value-added benefit for customers with stronger timeliness requirements, and simultaneously, chip development enterprises can avoid secondary development.
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The invention is described in detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of the present invention;
fig. 2 is a flowchart of an encryption algorithm according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, an algorithm expansion customizing method of a blockchain chip includes:
s101, when the block chain chip executes the algorithm process, reading binary numbers written into the block chain chip in advance.
The algorithm flow comprises a plurality of sub-algorithm flows.
And S102, operating the binary number and the output value of the first sub-algorithm flow to obtain an operation value.
Different binary numbers are written in and different operation modes are adopted, the original algorithm on the block chain chip can be expanded and customized, and the binary numbers and the operation modes can be determined according to the output requirements of customers on the algorithm. The operation method is, for example, addition, subtraction, or exclusive or.
And S103, inputting the operation value serving as an input value of the second sub-algorithm flow into the second sub-algorithm flow. And after calculation, the output value of the second sub-algorithm flow is different from the original output value of the second sub-algorithm flow.
The first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
The invention changes the output of the original algorithm by operating the intermediate value between the two sub-processes, obtains the variant algorithm, the binary number and the operation mode required by the operation can be determined according to the output requirement of the client on the algorithm, and the chip enterprise can solidify and customize the binary number and the operation mode in the chip according to the requirement of the client in the chip development stage, thereby realizing the expansion and customization of the original algorithm on the block chain chip, reducing the cost, improving the efficiency, increasing the value-added benefit of the client with stronger timeliness requirement, and simultaneously avoiding the secondary development of the chip development enterprise.
The register of the chip can be configured through software carried by the blockchain server, so that the chip is instructed to execute the original algorithm flow or the variant algorithm flow, for example, when an A value is configured in the register, the chip executes the original algorithm flow, and when a B value is configured, the chip executes the variant algorithm flow.
In this embodiment, writing a binary number to the blockchain chip in advance includes:
after the block chain chip is powered on, the level of an input pin and an output pin of the block chain chip is read and stored as binary number, the low level is 0, and the high level is 1. In the chip design stage, after determining binary numbers according to the requirements of customers, a chip development enterprise carries out corresponding design on an input/output pin circuit of the chip development enterprise, so that the corresponding binary numbers can be obtained after the input/output pins are powered on, if 1100 is required to be obtained, the input/output pin circuit is designed to be that pins 0 and 1 are grounded, and pins 2 and 3 are connected with high level.
Of course, it is also possible to burn customer-determined binary numbers into the one-time programmable memory of the blockchain chip during the chip design phase.
Wherein, the one-time programmable memory adopts an EFUSE memory.
Preferably, in this embodiment, the binary number is 12-bit data, and writing the binary number to the block chain chip in advance includes:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as 4-bit data;
burning 4-bit data into a one-time programmable memory of the block chain chip;
configuring 4-bit data to a register of a block chain chip;
and combining the 3 4-bit data into 12-bit data according to a preset sequence.
The 8-bit data is solidified by a chip enterprise in a chip design stage through a pin circuit design and a mode of burning into a one-time programmable memory, and the rest 4-bit data is reserved for a client to configure a register of a block chain chip.
Specifically, the 3 pieces of 4-bit data are combined into 12-bit data in order from left to right.
The scheme also relates to an algorithm expansion customization system of the blockchain chip, which comprises a storage module arranged in the blockchain chip, wherein the storage module comprises a plurality of instructions loaded and executed by a processing module of the blockchain chip, and as shown in fig. 1:
s101, when the block chain chip executes the algorithm process, reading binary numbers written into the block chain chip in advance.
The algorithm flow comprises a plurality of sub-algorithm flows.
And S102, operating the binary number and the output value of the first sub-algorithm flow to obtain an operation value.
Different binary numbers are written in and different operation modes are adopted, the original algorithm on the block chain chip can be expanded and customized, and the binary numbers and the operation modes can be determined according to the output requirements of customers on the algorithm.
And S103, inputting the operation value serving as an input value of the second sub-algorithm flow into the second sub-algorithm flow. And after calculation, the output value of the second sub-algorithm flow is different from the original output value of the second sub-algorithm flow.
The first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
In this embodiment, writing a binary number to the blockchain chip in advance includes:
after the block chain chip is powered on, the level of an input pin and an output pin of the block chain chip is read and stored as binary number, the low level is 0, and the high level is 1. In the chip design stage, after determining binary numbers according to the requirements of customers, a chip development enterprise carries out corresponding design on an input/output pin circuit of the chip development enterprise, so that the corresponding binary numbers can be obtained after the input/output pins are powered on, if 1100 is required to be obtained, the input/output pin circuit is designed to be that pins 0 and 1 are grounded, and pins 2 and 3 are connected with high level.
Of course, it is also possible to burn customer-determined binary numbers into the one-time programmable memory of the blockchain chip during the chip design phase.
Wherein, the one-time programmable memory adopts an EFUSE memory.
Preferably, in this embodiment, the binary number is 12-bit data, and writing the binary number to the block chain chip in advance includes:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as 4-bit data;
burning 4-bit data into a one-time programmable memory of the block chain chip;
configuring 4-bit data to a register of a block chain chip;
and combining the 3 4-bit data into 12-bit data according to a preset sequence.
The 8-bit data is solidified by a chip enterprise in a chip design stage through a pin circuit design and a mode of burning into a one-time programmable memory, and the rest 4-bit data is reserved for a client to configure a register of a block chain chip.
Specifically, the 3 pieces of 4-bit data are combined into 12-bit data in order from left to right.
As shown in fig. 2, taking an encryption algorithm flow as an example, the encryption algorithm flow includes two sub-encryption algorithm flows: the Salsa20 algorithm flow and the SHA256 algorithm flow, the 12-bit binary number is 101010111100.
1011 and 1100 are fixed in the chip by the chip enterprise, and the operation mode is fixed as addition operation, 1010 is configured from the register of the block chain chip by the client.
Then, the output value X of the Salsa20 algorithm flow is added to 101010111100 to obtain an operation value.
And finally, inputting the operation value serving as an input value of the SHA256 algorithm flow into the SHA256 algorithm flow, wherein an output value of the SHA256 algorithm flow is an output value of the encryption algorithm after being subjected to hash.
However, those skilled in the art should realize that the above embodiments are illustrative only and not limiting to the present invention, and that changes and modifications to the above described embodiments are intended to fall within the scope of the appended claims, provided they fall within the true spirit of the present invention.
Claims (10)
1. An algorithm expansion customizing method of a block chain chip is characterized by comprising the following steps:
reading binary numbers written into the blockchain chip in advance when the blockchain chip executes the algorithm process, wherein the algorithm process comprises a plurality of sub-algorithm processes;
calculating the binary number and an output value of the first sub-algorithm flow to obtain a calculated value;
inputting the calculated value into a second sub-algorithm process as an input value of the second sub-algorithm process for calculation, so that the output value of the second sub-algorithm process is different from the original output value;
the first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
2. The algorithm expansion customizing method of the blockchain chip according to claim 1, wherein reading a binary number previously written to the blockchain chip comprises:
and after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as binary number, wherein the low level is 0, and the high level is 1.
3. The algorithm expansion customizing method of the blockchain chip according to claim 1, wherein reading a binary number previously written to the blockchain chip comprises:
and burning the binary number into a one-time programmable memory of the block chain chip.
4. The algorithm expansion customizing method of a blockchain chip according to claim 1, wherein the binary number is 12-bit data, and reading the binary number previously written to the blockchain chip comprises:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as a first group of 4-bit data;
burning a second group of 4-bit data into a one-time programmable memory of the block chain chip;
configuring a third group of 4-bit data to a register of the block chain chip;
and combining the three groups of 4-bit data into 12-bit data according to a preset sequence.
5. The method of claim 4, wherein said three groups of 4-bit data are combined into 12-bit data in a left-to-right order.
6. The algorithm expansion customization system of the blockchain chip is characterized by comprising a storage module arranged in the blockchain chip, wherein the storage module comprises a plurality of instructions loaded and executed by a processing module of the blockchain chip:
reading binary numbers written into the blockchain chip in advance when the blockchain chip executes the algorithm process, wherein the algorithm process comprises a plurality of sub-algorithm processes;
calculating the binary number and an output value of the first sub-algorithm flow to obtain a calculated value;
inputting the calculated value into a second sub-algorithm process as an input value of the second sub-algorithm process for calculation, so that the output value of the second sub-algorithm process is different from the original output value;
the first sub-algorithm process and the second sub-algorithm process are any two sub-algorithm processes before and after the algorithm process executed by the block chain chip.
7. The system of claim 6, wherein reading the binary number previously written to the blockchain chip comprises:
and after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as binary number, wherein the low level is 0, and the high level is 1.
8. The system of claim 6, wherein reading the binary number previously written to the blockchain chip comprises:
and burning the binary number into a one-time programmable memory of the block chain chip.
9. The system of claim 6, wherein the binary number is 12 bits of data, and reading the binary number previously written to the blockchain chip comprises:
after the block chain chip is electrified, reading the level of an input/output pin of the block chain chip and storing the level as a first group of 4-bit data;
burning a second group of 4-bit data into a one-time programmable memory of the block chain chip;
configuring a third group of 4-bit data to a register of the block chain chip;
and combining the three groups of 4-bit data into 12-bit data according to a preset sequence.
10. The system according to claim 9, wherein the three groups of 4-bit data are combined into 12-bit data in a left-to-right order.
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| CN106452776A (en) * | 2015-08-12 | 2017-02-22 | 航天信息股份有限公司 | Data encryption method |
| CN105577363B (en) * | 2016-01-29 | 2018-06-01 | 江苏沁恒股份有限公司 | For the Extensible pipeline circuit and its implementation of SM4 cryptographic algorithms |
| CN108616348B (en) * | 2018-04-19 | 2019-08-23 | 清华大学无锡应用技术研究院 | The method and system of security algorithm, decipherment algorithm are realized using reconfigurable processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN204965422U (en) * | 2015-09-18 | 2016-01-13 | 芯佰微电子（北京）有限公司 | Multi -protocols cryptographic algorithm treater and system on chip/SOC |
| CN108229686A (en) * | 2016-12-14 | 2018-06-29 | 阿里巴巴集团控股有限公司 | Model training, Forecasting Methodology, device, electronic equipment and machine learning platform |
| CN109976723A (en) * | 2019-03-12 | 2019-07-05 | 北京国电智深控制技术有限公司 | A kind of algorithm development platform, algorithm development method and computer readable storage medium |
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