CN105577347A - Time division multiplexing transmission circuit and data transmission device - Google Patents
Time division multiplexing transmission circuit and data transmission device Download PDFInfo
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- CN105577347A CN105577347A CN201510934954.4A CN201510934954A CN105577347A CN 105577347 A CN105577347 A CN 105577347A CN 201510934954 A CN201510934954 A CN 201510934954A CN 105577347 A CN105577347 A CN 105577347A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
Abstract
The invention discloses a time division multiplexing transmission circuit and a data transmission device. The time division multiplexing transmission circuit comprises a NOR gate circuit which comprises an output end, a first control end, multiple data input ends and at least one second control end; a first control circuit which is connected with the first control end and used for prohibiting or allowing transmission of data inputted from multiple data transmission ends to the output end; and a second control circuit which is connected with the second control ends and used for controlling the level of the second control ends and selecting to transmit the data of one data input end of multiple data input ends to the output end when the first control circuit allows transmission of the data inputted from multiple data transmission ends to the output end. According to the time division multiplexing transmission circuit and the data transmission device, time division multiplexing transmission through one path of port can be realized so that single-chip microcomputer resources and data transmission ports are saved and management of the multiplexing transmission data is greatly facilitated.
Description
Technical field
The present invention relates to field of data transmission, particularly relate to a kind of time-sharing multiplex transmission circuit and data transmission device.
Background technology
Along with the development of science and technology, product rise that is more and more miniaturized and intelligent and Internet of Things, transducer is more and more integrated, such as temperature sensing module, humidity sensor module, and some gas sensing modules, single-chip microcomputer (MicroprogrammedControlUnit, MCU) only needs the Single-wire data reading their output just can gather the data wanting to obtain.Existing technology is when multiplexing module composition embedded system, and mostly adopt independently data channel between each sensing module, independently sheet selects control end, greatly waste MCU resource, waste communication interface resource, cost is higher, and is not easy to unified management multi-channel data transmission passage.
Summary of the invention
Embodiments providing a kind of time-sharing multiplex transmission circuit and data transmission device, for solving in prior art, an output interface being set for each data transmission channel, cause the problem that cost is higher.
For achieving the above object and other relevant objects, the invention provides a kind of time-sharing multiplex transmission circuit and data transmission device;
A kind of time-sharing multiplex transmission circuit, comprise: OR-NOT circuit, OR-NOT circuit comprises output, the first control end, multiple data input pin and at least one the second control end, and the first control end and the second control end are for controlling the transfer of data that inputs from multiple data transmission terminal to output; First control circuit, is connected with the first control end, for forbidding or allowing the transfer of data that inputs from multiple data transmission terminal to output; Second control circuit, be connected with the second control end, for controlling the level of the second control end, and when first control circuit to allow the transfer of data that inputs from multiple data transmission terminal to output, select the transfer of data of the data input pin of in multiple data input pin to output.
In one embodiment of the present invention, when the first control end is low level, OR-NOT circuit is input as low level, forbids the transfer of data that inputs from multiple data transmission terminal to output; When first control end is high level, OR-NOT circuit will be selected the transfer of data of the data input pin of in multiple data input pin to output according to the level of the second control end.
In one embodiment of the present invention, first control circuit comprises the first not gate, and control signal transfers to the first control end of OR-NOT circuit through the first not gate.
In one embodiment of the present invention, OR-NOT circuit comprises multiple with door with one or door, wherein, multiplely with the output of door be or the input of door, eachly comprise one first control end, at least one second control end and a data input pin with door, multiple be high level or low level with the first control end of door simultaneously, and synchronization, only has one to be all high level with the second control end of door.
In one embodiment of the present invention, one when being all high level with the first control end of door and the second control end, by the transfer of data of the data input pin with door to the output of OR-NOT circuit.
In one embodiment of the present invention, OR-NOT circuit comprise first with door, second with door, the 3rd with door, the 4th and door and one or door, first with door, second with door, the 3rd with door and the 4th and the output of door is all or the input of door, eachly comprise four inputs with door, one of them input is the first control end, 2 inputs are the second control end, an input is data input pin, synchronization, first is simultaneously high level with in door and the 4th and door with two the second control ends of door with door, the 3rd with door, second.
In one embodiment of the present invention, second control circuit comprises first input end, the second input, the first output, the second output, the 3rd output and the 4th output, wherein, first output connect second with door and the 4th with the second control end of door, second output connect first with door and the 3rd with the second control end of door, 3rd output connect first with door and second with the second control end of door, the 4th output connect the 3rd with door and the 4th and the second control end of door.
In one embodiment of the present invention, second control circuit comprises the second not gate, the 3rd not gate, the 4th not gate and the 5th not gate, first selects signal to export the second output to by the second not gate, and first selects signal to export the first output to through the second not gate and the 3rd not gate successively; Second selects signal to export the 3rd output to by the 4th not gate, and second selects signal to export the 4th output to through the 4th not gate and the 5th not gate successively.
The present invention also provides a kind of data transmission device, comprise single-chip microcomputer, multiple transducer, time-sharing multiplex transmission circuit and output port, single-chip microcomputer, multiple transducer and output port are connected with this time-sharing multiplex transmission circuit respectively, Single-chip Controlling timesharing utilizes transmission circuit to become a circuit-switched data to transfer to output port the data time-sharing multiplex of multiple transducer, wherein, this time-sharing multiplex transmission circuit comprises: OR-NOT circuit, this OR-NOT circuit comprises output, first control end, multiple data input pin and at least one the second control end, first control end and the second control end are for controlling the transfer of data that inputs from multiple data transmission terminal to output, first control circuit, is connected with the first control end, for forbidding or allowing the transfer of data that inputs from multiple data transmission terminal to output, second control circuit, be connected with the second control end, for controlling the level of the second control end, and when first control circuit to allow the transfer of data that inputs from multiple data transmission terminal to output, select the transfer of data of the data input pin of in multiple data input pin to output.
In one embodiment of the present invention, this transducer comprise temperature sensor, temperature sensor, gas sensor and pressure sensor one of at least.
A kind of time-sharing multiplex transmission circuit of the present invention and data transmission device, at least have following beneficial effect:
1, the transmission of employing one line cap time-sharing multiplex can be realized;
2, saved mcu resource from and data transmission port, greatly facilitate the management of multi-path transmission data.
Accompanying drawing explanation
Fig. 1 be an embodiment of time-sharing multiplex transmission circuit of the present invention structural representation;
Fig. 2 is the structural representation of the specific embodiment of time-sharing multiplex transmission circuit of the present invention;
Fig. 3 be an embodiment of data transmission device of the present invention structural representation.
Component symbol explanation
10 time-sharing multiplex transmission circuits
11 OR-NOT circuit
12 first control circuits
13 second control circuits
Y output
110 first control ends
D, D0, D1, D2, D3 data input pin
111 second control ends
A1 first not gate
A2 second not gate
A3 the 3rd not gate
A4 the 4th not gate
A5 the 5th not gate
B6 first and door
B7 second and door
B8 the 3rd and door
B9 the 4th and door
H1 or door
130 first input ends
131 second inputs
132 first outputs
133 second outputs
134 the 3rd outputs
135 the 4th output lines
C control signal
S0 first selects signal
S1 second selects signal
20 single-chip microcomputers
30 output ports
N0, n1, n2, n3 transducer
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.It should be noted that, when not conflicting, the feature in following examples and embodiment can combine mutually.
It should be noted that, the diagram provided in following examples only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment 1
As shown in Figure 1, time-sharing multiplex transmission circuit of the present invention an embodiment structural representation.This time-sharing multiplex transmission circuit 10 comprises: OR-NOT circuit 11, first control circuit 12 and second control circuit 13, and this OR-NOT circuit 11 is connected with this first control circuit 12 and second control circuit 13 respectively.Particularly, this OR-NOT circuit 11 comprises output Y, the first control end 110, multiple data input pin D and at least one corresponding with multiple data input pin D respectively second control end 111, first control end 110 and the second control end 111 for controlling the transfer of data that inputs from multiple data transmission terminal D to output Y.First control circuit 12 is connected with the first control end 110, for forbidding or allowing the transfer of data from multiple data transmission terminal D input to output Y.Second control circuit 13 is connected with the second control end 111, for controlling the level of the second control end 111, and when first control circuit 12 to allow the transfer of data that inputs from multiple data transmission terminal D to output Y, select the transfer of data of a data input pin D in multiple data input pin D to output Y.
In the present embodiment, when the first control end 110 is low level, OR-NOT circuit 11 is input as low level, forbids the transfer of data from multiple data transmission terminal D input to output Y.When first control end 110 is high level, OR-NOT circuit 11 will be selected the transfer of data of a data input pin D in multiple data input pin D to output Y according to the level of the second control end 111.So, the transmission of employing one line cap time-sharing multiplex can be realized, saved mcu resource from and data transmission port, simultaneously road first control end 110 just can shield or turn-on data transmission channel, greatly facilitates the management of multi-path transmission data.
Further, this OR-NOT circuit 11 comprises multiple with door with one or door, wherein, multiplely with the output of door be or the input of door, eachly comprise one first control end 110, at least one second control end 111 and data input pin D with door, multiple be high level or low level with the first control end 110 of door simultaneously, and synchronization, only has one to be all high level with the second control end 111 of door.
In a preferred version of the present embodiment, as shown in Figure 2, for the structural representation of the specific embodiment of time-sharing multiplex transmission circuit of the present invention, 4 data input pins should be comprised with time-sharing multiplex transmission circuit 10,4 with door and one or door be example, OR-NOT circuit 11 comprise first with door B6, second with door B7, the 3rd with door B8, the 4th and door B9 and one or door H1.First to be all with the output of door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second or the input of door H1, eachly comprise four inputs with door, one of them input is the first control end 110,2 inputs be the second control end 111, input is data input pin D.Synchronization, first is simultaneously high level with in door B8 and the 4th and door B9 with two the second control ends 111 of door with door B7, the 3rd with door B6, second.One when being all high level with the first control end 110 of door and the second control end 111, by the transfer of data of the data input pin D with door to the output Y of OR-NOT circuit 11.
Second control circuit 13 comprises first input end 130, second input 131, first output 132, second output 133, the 3rd output 134 and the 4th output 135.Wherein, first output 132 connects second control end 111 of second and door B7 and the 4th and door B9, second output 133 connects second control end 111 of first and door B6 and the 3rd and door B8,3rd output 134 connect first with second control end the 111, four output 135 of door B6 and second and door B7 connect the 3rd with second control end 111 of door B8 and the 4th and door B9.
More preferably, first control circuit 12 comprises the first not gate A1, and control signal C transfers to the first control end 110 of OR-NOT circuit 11 through the first not gate A1.Second control circuit 13 comprises the second not gate A2, the 3rd not gate A3, the 4th not gate A4 and the 5th not gate A5.First selects signal S0 to export the second output 133, first to by the second not gate A2 selects signal S0 to export the first output 132 to through the second not gate A2 and the 3rd not gate A3 successively; Second selects signal S1 to export the 3rd output 134, second to by the 4th not gate A4 selects signal S1 to export the 4th output 135 to through the 4th not gate A4 and the 5th not gate A5 successively.
For the ease of understanding, the operation principle specifically describing this time-sharing multiplex transmission circuit is below as follows:
Work as S0=0, during S1=0, and during control signal C=0, the 3rd not gate A3 exports high level 1, and this high level is added to an input of first and door B6.Because of S1=0, high level 1 is exported through the 5th not gate A5, this high level is added to another input of first and door B6, and control signal C=0, high level 1 is exported through the first not gate A1, now first is all high level with three inputs in four inputs of door B6, and obviously another input D0 just can determine the output state with door B6.Now second has one or two inputs to be low level 0 with door B7 and the 3rd and door B8, so the first state forming OR-NOT circuit 11 with door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second determines with door B6 by first, now input D0 just can determine first and door B6, second and door B7, the 3rd and door B8 and the 4th and door B9 form the output state of OR-NOT circuit 11.Namely the data selection now transmitted is that D0 road is as output data.
Work as S0=1, during S1=0, and during control signal C=0, export high level 1 when S0 is high level through the second not gate A2, the 3rd not gate A3, this high level is added to an input of second and door B7.Because S1 is that low level 0 exports high level 1 through the 5th not gate A5, this high flat another input being added to second and door B7, and control signal C=0, high level 1 is exported through the first not gate A1, now second is all high level with three inputs in four inputs of door B7, and obviously another input D1 just can determine the output state of first and door B6.Now first with door B6, second with door B7, the 3rd and door B8 have one or two inputs to be low level 0, so the first state forming OR-NOT circuit 11 with door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second determines with door B7 by second, now input D0 just can determine first and door B6, second and door B7, the 3rd and door B8 and the 4th and door B9 form the output state of OR-NOT circuit 11.Namely the data selection now transmitted is that D1 road is as output data.
Work as S0=0, during S1=1, and during control signal C=0, export high level 1 when S0 is low level through the 3rd not gate A3, this high level is added to an input of the 3rd and door B8.Because S1 is that high level 0 exports high level 1 through the 4th not gate A4, the 5th not gate A5, this high flat another input being added to the 3rd and door B8, and control signal C=0, high level 1 is exported through the first not gate A1, now the 3rd is all high level with three inputs in four inputs of door B8, and obviously another input D2 just can determine the output state of the 3rd and door B8.Now first with door B6, second with door B7, the 4th and door B9 have one or two inputs to be low level 0, so the first state forming OR-NOT circuit 11 with door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second determines with door B8 by the 3rd, now input D0 just can determine first and door B6, second and door B7, the 3rd and door B8 and the 4th and door B9 form OR-NOT circuit 11 output state.Namely the data selection now transmitted is that D2 road is done as output data.
Work as S0=1, during S1=1, and during control signal C=0, export high level 1 when S0 is high level through the second not gate A2, the 3rd not gate A3, this high level is added to an input of the 4th and door B9.Because S1 is that high level exports high level 1 through the 4th not gate A4, the 5th not gate A5, this high flat another input being added to the 4th and door B9, and control signal C=0, high level 1 is exported through the first not gate A1, now the 4th is all high level with three inputs in four inputs of door B9, and obviously another input D3 just can determine the output state of the 4th and door B9.Now first with door B6, second with door B7, the 3rd and door B8 have one or two inputs to be low level 0, so the first state forming OR-NOT circuit with door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second determines with door B9 by the 4th, now input D3 just can determine first and door B6, second and door B7, the 3rd and door B8 and the 4th and door B9 form the output state of OR-NOT circuit 11.Namely the data selection now transmitted is that D3 road is as output data.
As control signal C=1, through the first not gate A1 output low level 0, because it is input that is each and door (B6 ~ B9), so first to export with door B8 and the 4th and door B9 with door B7, the 3rd with door B6, second be all low level, first with door B6, second and door B7, the 3rd and the OR-NOT circuit 11 that forms of door B8 and the 4th and door B9 to export be low level 0.Namely, as the first control end C=1, all tunnel data transport can be shielded.
Particularly, in time-sharing multiplex transmission circuit 10, during control signal C=0, select the truth table of signal (first selects signal S0 and second to select signal S1) in table 1, transfer of data truth table is see table 2.
Signal truth table selected by table 1
| First selects signal S0 | Second selects signal S1 | Output Y (C=0) | Illustrate (C=0) |
| 1 | 1 | D3 | Export D3 5--> |
| 0 | 1 | D2 | Export D2 |
| 1 | 0 | D1 | Export D1 |
| 0 | 0 | D0 | Export D0 |
Table 2 transfer of data truth table
As can be seen from Table 1 and Table 2, control signal C=0, when first selection signal S0 and second selects signal S1 to be high level 1, the output Y of time-sharing multiplex transmission circuit 10 exports the data of data input pin D3, namely when data input pin D3 is low level 0, output Y output low level 0, when data input pin D3 is high level 1, output Y exports high level 1.
Control signal C=0, first selects signal S0 to be low level 0, when second selection signal S1 is high level 1, the output Y of time-sharing multiplex transmission circuit 10 exports the data of data input pin D2, namely when data input pin D2 is low level 0, output Y output low level 0, when data input pin D2 is high level 1, output Y exports high level 1.
Control signal C=0, first selects signal S0 to be high level 1, when second selection signal S1 is low level 0, the output Y of time-sharing multiplex transmission circuit 10 exports the data of data input pin D1, namely when data input pin D1 is low level 0, output Y output low level 0, when data input pin D1 is high level 1, output Y exports high level 1.
Control signal C=0, when first selection signal S0 and second selects signal S1 to be low level 0, the output Y of time-sharing multiplex transmission circuit 10 exports the data of data input pin D0, namely when data input pin D0 is low level 0, output Y output low level 0, when data input pin D0 is high level 1, output Y exports high level 1.
During control signal C=1, the output of output Y, not by the impact of data input pin D0-D3, exports 0 all the time, and then shields all tunnel data transport.
More than can find out, four circuit-switched data input D0-D3 time-sharing multiplexs can be that a road output Y exports by the embodiment of the present invention, realize employing one line cap time-sharing multiplex transmission, saved mcu resource from and data transmission port.Be simultaneously high level 1 or low level 0 according to control signal C, just can shield or turn-on data transmission channel, greatly facilitate the management of multi-path transmission data.
Embodiment 2
The present invention also provides a kind of data transmission device, as shown in Figure 3, for this data transmission device of structural representation of an embodiment of data transmission device of the present invention comprises time-sharing multiplex transmission circuit 10, single-chip microcomputer 20, multiple transducer n0, n1, n2, n3 and output port 30.Single-chip microcomputer 20, multiple transducer n0, n1, n2, n3 and output port 30 are connected with time-sharing multiplex transmission circuit 10.Single-chip microcomputer 20 controls timesharing and utilizes transmission circuit 10 to become a circuit-switched data to transfer to output port 30 the data D0 of multiple transducer n0, n1, n2, n3, D1, D2, D3 time-sharing multiplex.In embodiments of the present invention, this time-sharing multiplex transmission circuit 10 is above-mentioned Fig. 1 and Fig. 2 of structural reference of the time-sharing multiplex transmission circuit described in above-described embodiment, this time-sharing multiplex transmission circuit 10.Single-chip microcomputer 20 sends control signal C, first and selects signal S0 and second to select signal S1, and then the data D0 of transducer n0, n1, n2, n3, D1, D2, D3 time-sharing multiplex are that a circuit-switched data transfers to output port 30 by control time-sharing multiplex transmission circuit 10, concrete implementation procedure is see Fig. 2.The concrete structure of this time-sharing multiplex transmission circuit 10 and operation principle are repeated no more herein.
The data D0 of multiple transducer n0, n1, n2, n3 sensing, D1, D2, D3 time-sharing multiplex can be that a circuit-switched data exports output port 30 to by the embodiment of the present invention, realize employing one line cap time-sharing multiplex transmission, saved mcu resource from and data transmission port.Just can shield or turn-on data transmission channel according to control signal C simultaneously, greatly facilitate the management of multi-path transmission data.
Transducer n0, n1, n2, n3 comprise temperature sensor, temperature sensor, gas sensor and pressure sensor one of at least.Can certainly be other transducer, not repeat them here.
In sum, time-sharing multiplex transmission circuit of the present invention and data transmission device, this time-sharing multiplex transmission circuit comprises OR-NOT circuit, first control circuit and second control circuit, OR-NOT circuit comprises output, the first control end, multiple data input pin and at least one corresponding with multiple data input pin respectively second control end, is forbidden or allow the transfer of data that inputs from multiple data transmission terminal to output by first control circuit; The level of the second control end is controlled by second control circuit, and when first control circuit to allow the transfer of data that inputs from multiple data transmission terminal to output, select the transfer of data of the data input pin of in multiple data input pin to output, carry out transfer of data, the transmission of employing one line cap time-sharing multiplex can be realized, saved mcu resource from and data transmission port, greatly facilitate the management of multi-path transmission data.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a time-sharing multiplex transmission circuit, is characterized in that, described time-sharing multiplex transmission circuit comprises:
OR-NOT circuit, described OR-NOT circuit comprises output, the first control end, multiple data input pin and at least one the second control end, and described first control end and described second control end are for controlling the transfer of data from multiple described data transmission terminal input to described output;
First control circuit, is connected with described first control end, for forbidding or allowing the transfer of data from multiple described data transmission terminal input to described output;
Second control circuit, be connected with described second control end, for controlling the level of described second control end, and when described first control circuit to allow the transfer of data from multiple described data transmission terminal input to described output, select the transfer of data of a data input pin in multiple described data input pin to described output.
2. time-sharing multiplex transmission circuit according to claim 1, is characterized in that,
When described first control end is low level, described OR-NOT circuit is input as low level, forbids the transfer of data from multiple described data transmission terminal input to described output;
When described first control end is high level, described OR-NOT circuit will be selected the transfer of data of a data input pin in multiple described data input pin to described output according to the level of described second control end.
3. time-sharing multiplex transmission circuit according to claim 1, is characterized in that, described first control circuit comprises the first not gate, and control signal transfers to the first control end of described OR-NOT circuit through described first not gate.
4. time-sharing multiplex transmission circuit according to claim 3, it is characterized in that, described OR-NOT circuit comprises multiple with door with one or door, wherein, multiple output that is described and door is input that is described or door, data input pin described in the first control end described in, at least one described second control end and is comprised with door described in each, multiple described first control end that is described and door is high level or low level simultaneously, synchronization, only has described in one and is all high level with described second control end of door.
5. time-sharing multiplex transmission circuit according to claim 3, it is characterized in that, when being all high level with described first control end of door and described second control end described in one, by the described transfer of data with the described data input pin of door to the described output of described OR-NOT circuit.
6. time-sharing multiplex transmission circuit according to claim 4, it is characterized in that, described OR-NOT circuit comprises first and door, second and door, 3rd and door, 4th with door and one or door, described first and door, described second and door, described 3rd is all input that is described or door with door and the described 4th with the output of door, four inputs are comprised with door described in each, input described in one of them is the first control end, 2 described inputs are described second control end, a described input is data input pin, at synchronization, described first and door, described second and door, described 3rd with door and the described 4th be high level with two described second control ends of door described in door simultaneously.
7. time-sharing multiplex transmission circuit according to claim 6, it is characterized in that, described second control circuit comprises first input end, second input, first output, second output, 3rd output and the 4th output, wherein, described first output connect described second with door and the described 4th with described second control end of door, described second output connect described first with door and the described 3rd with described second control end of door, described 3rd output connect described first with door and described second with described second control end of door, described 4th output connect the described 3rd with door and the described 4th with described second control end of door.
8. time-sharing multiplex transmission circuit according to claim 7, it is characterized in that, described second control circuit comprises the second not gate, the 3rd not gate, the 4th not gate and the 5th not gate, first selects signal to export described second output to by the second not gate, and described first selects signal to export described first output to through described second not gate and described 3rd not gate successively; Second selects signal to export the 3rd output to by the 4th not gate, and described second selects signal to export described 4th output to through the 4th not gate and described 5th not gate successively.
9. a data transmission device, described data transmission device comprises: single-chip microcomputer, multiple transducer, output port, it is characterized in that, also comprise the time-sharing multiplex transmission circuit as described in claim 1-8 any one, described single-chip microcomputer, multiple described transducer and described output port are connected with described time-sharing multiplex transmission circuit respectively, and timesharing described in described Single-chip Controlling utilizes transmission circuit to become a circuit-switched data to transfer to described output port the data time-sharing multiplex of multiple described transducer.
10. data transmission device according to claim 9, is characterized in that, described transducer comprise temperature sensor, temperature sensor, gas sensor and pressure sensor one of at least.
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| CN106326156A (en) * | 2016-08-30 | 2017-01-11 | 西安翔腾微电子科技有限公司 | Single port communication processing circuit based on self-adaptive baud rate and method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5228027A (en) * | 1990-08-24 | 1993-07-13 | Noboru Yamaguchi | Data communication apparatus |
| CN2196054Y (en) * | 1994-03-07 | 1995-05-03 | 傅亚文 | Speech reading, alarm and instructing device for motor-driven vehicle |
| CN102169726A (en) * | 2011-05-03 | 2011-08-31 | 电子科技大学 | Universal byte circuit applied to FPGAs (Field Programmable Gate Arrays) and programming method |
| CN102290823A (en) * | 2011-08-26 | 2011-12-21 | 东北大学 | Alternating tidal current computing method and device for light high-voltage direct current transmission system |
-
2015
- 2015-12-15 CN CN201510934954.4A patent/CN105577347A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5228027A (en) * | 1990-08-24 | 1993-07-13 | Noboru Yamaguchi | Data communication apparatus |
| CN2196054Y (en) * | 1994-03-07 | 1995-05-03 | 傅亚文 | Speech reading, alarm and instructing device for motor-driven vehicle |
| CN102169726A (en) * | 2011-05-03 | 2011-08-31 | 电子科技大学 | Universal byte circuit applied to FPGAs (Field Programmable Gate Arrays) and programming method |
| CN102290823A (en) * | 2011-08-26 | 2011-12-21 | 东北大学 | Alternating tidal current computing method and device for light high-voltage direct current transmission system |
Non-Patent Citations (1)
| Title |
|---|
| 翁顺祺: "数据选择器在时序电路的应用开拓", 《电子技术应用》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326156A (en) * | 2016-08-30 | 2017-01-11 | 西安翔腾微电子科技有限公司 | Single port communication processing circuit based on self-adaptive baud rate and method thereof |
| CN106326156B (en) * | 2016-08-30 | 2024-04-05 | 西安翔腾微电子科技有限公司 | Single-port communication processing circuit and method based on self-adaptive baud rate |
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Application publication date: 20160511 |