CN105576965B - A kind of double loop charge pump design - Google Patents
A kind of double loop charge pump design Download PDFInfo
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- CN105576965B CN105576965B CN201510926823.1A CN201510926823A CN105576965B CN 105576965 B CN105576965 B CN 105576965B CN 201510926823 A CN201510926823 A CN 201510926823A CN 105576965 B CN105576965 B CN 105576965B
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- charge pump
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention provides a kind of double loop charge pump circuit, the double loop charge pump circuit by two belt switches current source and compare feedback control loop and form, determine electric charge being pumped into loop filter or pump out electric charge from loop filter according to feedback signal and two logic input signals.Circuit structure tool can realize the quick lock in of phaselocked loop and automatically adjusting for bandwidth, and the advantages that reduce the reference spur of phaselocked loop.
Description
Technical field
The invention belongs to field of radio frequency circuit design, is related to a kind of double loop charge pump design.
Background technology
Double loop charge pump is widely used in the phaselocked loop in SerDes circuits, and clock is provided for SerDes phaselocked loop
Frequency calibration.In the SerDes systems of multi-protocols unified shader, it is desirable to there is different input reference frequencies, and require to lock phase
The frequency and bandwidth of ring can adaptively adjust and reduce influence of the strong clock signal to other circuit modules as far as possible, therefore, lock
Xiang Huanzhong needs to use double loop charge pump, it is possible to achieve the quick lock in of phaselocked loop and automatically adjusting for bandwidth, and reduce lock
The reference spur of phase ring.
The content of the invention
The present invention provides a kind of double loop charge pump bandwidth self-adaption phaselocked loop, and the phaselocked loop is voltage-controlled using even level annular
Oscillator, double loop charge pump and voltage-current converter circuit, the phaselocked loop can realize the quick lock in of phaselocked loop, loop bandwidth
The advantages that adaptively being adjusted with concussion frequency.
The particular technique solution of the present invention is as follows：
A kind of double loop charge pump circuit, including path of integration charge pump B1, proportional path charge pump B2, I/V converter
B3, comparator B8 and V/I converter B9；
The path of integration charge pump B1 includes the first UP circuits B4 and the first DN circuits B5 being sequentially connected；The ratio
Path charge pump B2 includes the 2nd UP circuits B6 and the 2nd DN circuits B7 being sequentially connected；First UP circuits B4 input fetches
From the UPB signals of phase frequency detector, the first DN circuits B5 input is fetched from phase frequency detector DN signals, the 2nd UP circuits B6
Input fetch DNB signals from phase frequency detector, the 2nd DN circuits B7 input fetches the UP letters from phase frequency detector
Number；The I/V converters B3 DN circuits B5 of output end VB1 connections the first and the 2nd DN circuits B7 other end；I/V converters B3's
The UP circuits B4 of output end VB2 connections the first and the 2nd UP circuits B6 other end；First UP circuits B4's and the first DN circuits B5
Tie point is connected to ground and output voltage VINT by electric capacity C1；2nd UP circuits B6, the 2nd DN circuit B7 and I/V converters B3
Output end is connected to b points, and b points are connected to ground and output voltage VCTRL by electric capacity C2；I/V converters B3 output voltage
VREF is inputted to comparator B8 positive inputs, and voltage VCTRL is inputted to comparator B8 negative inputs, comparator B8 output
End is connected with V/I converters B9 input,
V/I converters B9 output end ICP is connected to I/V converters B3 input a.
Path of integration charge pump B1 is identical with proportional path charge pump B2 structure,
Path of integration charge pump B1 includes metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3 and metal-oxide-semiconductor M4,
Metal-oxide-semiconductor M4 G termination UP signals,
Metal-oxide-semiconductor M4 S termination Vdd, metal-oxide-semiconductor M4 D ends are connected with metal-oxide-semiconductor M2 S ends；
Metal-oxide-semiconductor M2G ends are connected with I/V converters B3 output end VB2, and metal-oxide-semiconductor M2 is connected output with metal-oxide-semiconductor M1 D ends
Vout, metal-oxide-semiconductor M1 S ends are connected with metal-oxide-semiconductor M3 D ends, and metal-oxide-semiconductor M1 G ends are connected with I/V converters B3 output end VB1；
Metal-oxide-semiconductor M3 G termination DN signals, metal-oxide-semiconductor M3 S terminations GND.
Advantages of the present invention is as follows：
A kind of double loop charge pump circuit design provided by the invention, the double loop charge pump can realize the fast of phaselocked loop
Speed locking automatically adjusts with bandwidth, and reduces the reference spur of phaselocked loop.
Brief description of the drawings
Fig. 1 is the circuit realiration figure of the present invention；
Fig. 2 is core charge pump circuit of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, technical scheme is clearly and completely stated.Obviously,
The embodiment stated only is part of the embodiment of the present invention, rather than whole embodiments, based on the embodiment in the present invention,
Those skilled in the art belong to the guarantor of the present invention in the every other embodiment do not made creative work premise and obtained
Protect scope.
The present invention provides a kind of double loop charge pump circuit design method, and this method comprises the following steps：
Including path of integration charge pump B1, proportional path charge pump B2, I/V converter B3, comparator B8, V/I converter
The modular circuits such as B9.
The path of integration charge pump B1 includes the UP circuits B4 of charge pump and the DN circuits B5 of charge pump.
The proportional path charge pump B2 includes the UP circuits B6 of charge pump and the DN circuits B7 of charge pump.
The tunnel input signal of UP, UPB, DN and DNB tetra- from phase frequency detector, in UPB connection path of integration charge pumps B1
UP B4 one end, one end of the DN B5 in DN connection path of integration charge pumps B1.In UP connection proportional path charge pumps B2
UP B7 one end, one end of the DN B6 in DNB connection proportional path charge pumps B2.
The I/V converters B3 output end VB1 connection B5 and B7 other end.
The I/V converters B3 output end VB2 connection B4 and B6 other end.
B4 and B5 tie point exports for VINT, and VINT is connected to ground by electric capacity C1.
B6 and B7 tie point exports for VCTRL, and VCTRL is connected to ground by electric capacity C2.
I/V converter B3 output ends meet at b point sinks with proportional path charge pump B2 outputs and are combined into VCTRL.
I/V converter B3 output ends VREF and VCTRL are connected to comparator B8 two inputs.
Comparator B8 output end is connected to V/I converters B9 input.
V/I converters B9 output end ICP is connected to I/V converters B3 a ends.
Wherein double loop charge pump circuit core circuit is path of integration charge pump and proportional path charge pump：M4、M5、M6
S termination Vdd, M4 D ends are connected with M2 S ends, and M4 G termination UP, M6 D ends are connected with M8 S ends, M5 D ends and M7
S ends be connected, M2, M7 and M8 G ends are connected and the current source that is connected with M7 D ends, the D ends that M9 and M1 G ends are connected with M8,
M2 is connected with M1 D ends exports Vout, and M9 S ends are connected with M10 D ends, and M1 S ends are connected with M3 D ends, M10 G terminations
Vdd, M3 G terminations DN, M3 and M10 S terminations GND.
Operation principle：Path of integration charge pump and proportional path charge pump, produce respectively control voltage VINT and
VCTRL, control voltage VINT caused by path of integration charge pump adjust control voltage VCTRL caused by proportional path charge pump,
By adjusting the gain of proportional path charge pump and path of integration charge pump, the dynamic decay factor and loop for adjusting phaselocked loop
Bandwidth, accelerate the lock speed of phaselocked loop.
The present invention provides a kind of double loop charge pump, and its path of integration charge pump and proportional path charge pump for including can
To realize automatically adjusting for the quick lock in of phaselocked loop and bandwidth, and reduce the reference spur of phaselocked loop.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
The present invention is described in detail, it will be understood by those within the art that：It still can be to foregoing each implementation
Technical scheme described in example is modified, or carries out equivalent substitution to which part technical characteristic；And these modification or
Replace, the essence of appropriate technical solution is departed from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (2)
- A kind of 1. double loop charge pump circuit, it is characterised in that：Including path of integration charge pump B1, proportional path charge pump B2, I/V converters B3, comparator B8 and V/I converter B9；The path of integration charge pump B1 includes the first UP circuits B4 and the first DN circuits B5 being sequentially connected；The proportional path Charge pump B2 includes the 2nd UP circuits B6 and the 2nd DN circuits B7 being sequentially connected；First UP circuits B4 input is fetched from mirror The UPB signals of frequency phase discriminator, the first DN circuits B5 input are fetched from phase frequency detector DN signals, and the 2nd UP circuits B6's is defeated Enter DNB signal of the termination from phase frequency detector, the 2nd DN circuits B7 input fetches the UP signals from phase frequency detector；I/ The V B3 DN circuits B5 of output end VB1 connections the first and the 2nd DN circuits B7 other end；I/V converters B3 output Hold the UP circuits B4 and the 2nd UP circuits B6 of VB2 connections the first other end；First UP circuits B4 and the first DN circuits B5 connection Point is connected to ground and output voltage VINT by electric capacity C1；2nd UP circuits B6, the 2nd DN circuit B7 and I/V converters B3 are exported End is connected to b points, and b points are connected to ground and output voltage VCTRL by electric capacity C2；I/V converters B3 output voltage VREF is defeated Enter to comparator B8 positive inputs, voltage VCTRL is inputted to comparator B8 negative inputs, comparator B8 output end and V/ I converters B9 input connection,V/I converters B9 output end ICP is connected to I/V converters B3 input a.
- 2. double loop charge pump circuit according to claim 1, it is characterised in that：Path of integration charge pump B1 is identical with proportional path charge pump B2 structure,Path of integration charge pump B1 includes metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3 and metal-oxide-semiconductor M4,Metal-oxide-semiconductor M4 G termination UP signals,Metal-oxide-semiconductor M4 S termination Vdd, metal-oxide-semiconductor M4 D ends are connected with metal-oxide-semiconductor M2 S ends；Metal-oxide-semiconductor M2G ends are connected with I/V converters B3 output end VB2, and metal-oxide-semiconductor M2 is connected with metal-oxide-semiconductor M1 D ends exports Vout, Metal-oxide-semiconductor M1 S ends are connected with metal-oxide-semiconductor M3 D ends, and metal-oxide-semiconductor M1 G ends are connected with I/V converters B3 output end VB1；Metal-oxide-semiconductor M3 G termination DN signals, metal-oxide-semiconductor M3 S terminations GND.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510926823.1A CN105576965B (en) | 2015-12-11 | 2015-12-11 | A kind of double loop charge pump design |
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| CN201510926823.1A CN105576965B (en) | 2015-12-11 | 2015-12-11 | A kind of double loop charge pump design |
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| CN105576965A CN105576965A (en) | 2016-05-11 |
| CN105576965B true CN105576965B (en) | 2017-11-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081427A (en) * | 1990-11-29 | 1992-01-14 | Motorola, Inc. | Fast lock time phase locked loop |
| CN103166631A (en) * | 2011-12-15 | 2013-06-19 | 瑞萨电子株式会社 | Pll circuit |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN104202048A (en) * | 2014-08-27 | 2014-12-10 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690240B2 (en) * | 2002-01-10 | 2004-02-10 | Cirrus Logic, Inc. | Low-jitter loop filter for a phase-locked loop system |
| US6909329B2 (en) * | 2003-09-02 | 2005-06-21 | Agere Systems Inc. | Adaptive loop bandwidth circuit for a PLL |
| US7777577B2 (en) * | 2007-09-28 | 2010-08-17 | Texas Instruments Incorporated | Dual path phase locked loop (PLL) with digitally programmable damping |
-
2015
- 2015-12-11 CN CN201510926823.1A patent/CN105576965B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081427A (en) * | 1990-11-29 | 1992-01-14 | Motorola, Inc. | Fast lock time phase locked loop |
| CN103166631A (en) * | 2011-12-15 | 2013-06-19 | 瑞萨电子株式会社 | Pll circuit |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN104202048A (en) * | 2014-08-27 | 2014-12-10 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
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| CN105576965A (en) | 2016-05-11 |
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Effective date of registration: 20221018 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No. 15, Jinye Second Road, Xi'an, Shaanxi 710065 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |