CN104348481B - For the active filter of phaselocked loop - Google Patents
For the active filter of phaselocked loop Download PDFInfo
- Publication number
- CN104348481B CN104348481B CN201310329487.3A CN201310329487A CN104348481B CN 104348481 B CN104348481 B CN 104348481B CN 201310329487 A CN201310329487 A CN 201310329487A CN 104348481 B CN104348481 B CN 104348481B
- Authority
- CN
- China
- Prior art keywords
- sub
- pmos
- capacitance module
- nmos tube
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of active filter for phaselocked loop, including：Operational amplifier, MOS transistor, four resistance, four capacitance modules and data signal control modules.Digital Signals module can adjust four capacitance sizes of capacitance module, can farthest meet the adjustable range of loop parameter, so as to meet requirement of the system to loop parameter.The connected mode of resistance, capacitance module and operational amplifier can active filter increased two low pass limits, clutter noise can be decayed.The biasing circuit of operational amplifier can reduce noise using bulky capacitor.The present invention can realize the active loop wave filter of low noise, high stability, and then can ensure the performance of ultra wide band phase-locked loop systems.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of active filter for phaselocked loop.
Background technology
Phase-locked loop circuit is the general module design for various chips, using extensive.Its loop filter module pair
The stability of whole phase-locked loop systems has vital influence, so the design of loop filter is quite important.Pair can
Adjust bandwidth do not have it is king-sized in the case of industry generally use Design of Passive Power Filter, but when to ultra wide band Design of PLL
When, the adjustable voltage of voltage controlled oscillator is likely larger than charge pump service voltage, the application of active loop wave filter be exactly it is necessary,
But active filter is always design active filter due to the influence of the factor such as noise, unstability of itself active device
Problem.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of active filter for phaselocked loop, can realize low noise
The active loop wave filter of sound, high stability, and then the performance of ultra wide band phase-locked loop systems can be ensured.
In order to solve the above technical problems, including provided by the present invention for the active filter of phaselocked loop：Operational amplifier,
First MOS transistor, first resistor, second resistance, 3rd resistor, the 4th resistance, the first capacitance module, the second capacitance module,
3rd capacitance module, the 4th capacitance module and data signal control module.
The charge pump current that the negative input end connection of the operational amplifier is exported by the charge pump of phaselocked loop.
The positive input terminal of the operational amplifier connects the first bias current, the positive input terminal and ground of the operational amplifier
Between connect the first resistor, the positive input terminal connection of the grid and the operational amplifier of first MOS transistor, institute
The source electrode and drain electrode for stating the first MOS transistor link together.
First capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module
All include four connection ends respectively, the first connection end is input, the second connection end is output end, the 3rd connection end is the first control
End processed, the 4th connection end are the second control end.
First capacitance module is connected on the fortune by the first connection end and the second connection end and the second resistance
Between the negative input end and output end of calculation amplifier.
Second capacitance module is connected to the negative defeated of the operational amplifier by the first connection end and the second connection end
Enter between end and the output end of the operational amplifier.
The 3rd resistor is connected between the first end of the output end of the operational amplifier and the 4th resistance, institute
The second end for stating the 4th resistance is the output end of the active filter, and the output end of the active filter is to the phaselocked loop
Voltage controlled oscillator output control voltage.
The first end of the 4th resistance is connected in first connection end and the second connection end of the 3rd capacitance module
One, another ground connection in first connection end and the second connection end of the 3rd capacitance module；The of 4th resistance
Two ends connect in first connection end and the second connection end of the 4th capacitance module, and the of the 4th capacitance module
Another ground connection in one connection end and the second connection end.
The Digital Signals module includes 5 inputs control end and two data output ends, 5 inputs control
End receives 5 control signals, 5 control signals that the Digital Signals module is received according to described 5 input control ends
Form two groups of data-signals and respectively from two data output end outputs, two groups of data-signals are all 5 and two groups of data-signals
It is each correspondence position data it is anti-phase each other.
First capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module
The 3rd connection end all connect the first data output end of the Digital Signals module, it is first capacitance module, described
4th connection end of the second capacitance module, the 3rd capacitance module and the 4th capacitance module all connects the data signal
Second data output end of control module.
First capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module
All use identical capacitance module structure.
The capacitance module structure includes six grades of sub- capacitor cells, and sub- electric capacity, first are all included per the sub- capacitor cell of one-level
PMOS and the first NMOS tube, the first end per the sub- electric capacity of one-level pass through first switching pmos and the electricity respectively
First connection end of molar block structure is connected and is switched by first NMOS tube and the capacitance module structure
First connection end is connected, and the second end per the sub- electric capacity of one-level is connected with the second connection end of the capacitance module structure.
First PMOS and the first NMOS tube of the sub- capacitor cell of the first order are all turned on, and make the sub- electric capacity of the first order always
It is connected between the first connection end of the capacitance module structure and the second connection end.
The grid of the first PMOS of the sub- capacitor cell in the second level connect first in first group of data-signal, first
The grid of NMOS tube connects first in second group of data-signal；The grid of the first PMOS of the sub- capacitor cell of the third level connects
Connect the second in first group of data-signal, the second in grid second group of data-signal of connection of the first NMOS tube；4th
The grid of the first PMOS of the sub- capacitor cell of level connects the 3rd, the grid company of the first NMOS tube in first group of data-signal
Meet the 3rd in second group of data-signal；The grid of the first PMOS of the sub- capacitor cell of level V connects first group of data letter
The 4th in number, the grid of the first NMOS tube connect in second group of data-signal the 4th；6th grade of sub- capacitor cell
The grid of the first PMOS connects the 5th, second group of data letter of grid connection of the first NMOS tube in first group of data-signal
The 5th in number.
The sub- electric capacity in the second level, institute are controlled by first group of data-signal and second group of data-signal respectively
State the sub- electric capacity of the third level, the sub- electric capacity of the fourth stage, the sub- electric capacity of the level V and the 6th grade of sub- electric capacity first end and
The conducting and disconnection of the first connection end of the capacitance module structure, so as to adjust the capacitance size of the capacitance module structure.
Further improvement is that the Digital Signals module includes 5 groups of identical Digital Signals units, each
Digital Signals unit is made up of together phase device and a phase inverter respectively, input connection 5 controls of the same phase device
One in signal processed, the output end of the same phase device connects the input of the phase inverter, and the output end of the same phase device is defeated
Go out the in-phase signal of connected control signal, the output end of the phase inverter exports the anti-phase letter of connected control signal
Number；The of the Digital Signals module is constituted by the output end of 5 phase inverters of the Digital Signals unit
One data output end simultaneously exports first group of data, by 5 outputs of the described same phase device of the Digital Signals unit
Second data output end of the end composition Digital Signals module simultaneously exports second group of data.
Further improvement is that the operational amplifier uses the fully differential Telescopic cascode structure of gain bootstrap,
Including：
Connected the fully differential common source for being formed and be total to by the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube
The source ground of grid structure, second NMOS tube and the 3rd NMOS tube, grid are a pair of inputs of differential signal, institute
The source electrode for stating the 4th NMOS tube connects the drain electrode of second NMOS tube, the source electrode of the 5th NMOS tube and connects the 3rd NMOS tube
Drain electrode, the drain electrode of the 4th NMOS tube and the 5th NMOS tube is a pair of output ends of differential signal.
The support structures for being formed are connected by the second PMOS, the 3rd PMOS, the 4th PMOS and the 5th PMOS, it is described
The drain electrode of drain electrode connection the 4th NMOS tube of the second PMOS, the drain electrode of the 3rd PMOS connects the 5th NMOS
The drain electrode of pipe, the source electrode of drain electrode connection second PMOS of the 4th PMOS, the drain electrode of the 5th PMOS connects
Connect the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and the 5th PMOS connects supply voltage.
First sub- operational amplifier, two differential input ends of the first sub- operational amplifier connect described second respectively
The drain electrode of NMOS tube and the 3rd NMOS tube, two difference output ends of the first sub- operational amplifier connect described respectively
The grid of the 4th NMOS tube and the 5th NMOS tube.
Second sub- operational amplifier, two differential input ends of the second sub- operational amplifier connect the described 4th respectively
The drain electrode of PMOS and the 5th PMOS, two difference output ends of the second sub- operational amplifier connect described respectively
The grid of the second PMOS and the 3rd PMOS.
Further improvement is that the first sub- operational amplifier is used by 2 the 6th PMOSs and 2 the 6th NMOS tubes
The fully differential folded cascode configuration of composition, 2 the 6th PMOSs are common source amplifier tube and 2 the 6th PMOS
The grid of pipe as the described first sub- operational amplifier differential input end, 2 the 6th NMOS tubes be common-gate amplifier tube simultaneously
And 2 drain electrodes of the 6th NMOS tube are used as the difference output end of the described first sub- operational amplifier.
The second sub- operational amplifier is using the fully differential folding being made up of 2 the 7th NMOS tubes and 2 the 7th PMOSs
Folded cascode structure, 2 the 7th NMOS tubes are for common source amplifier tube and 2 grids of the 7th NMOS tube are used as institute
The differential input end of the second sub- operational amplifier is stated, 2 the 7th PMOSs are common-gate amplifier tube and 2 the described 7th
The drain electrode of PMOS as the described second sub- operational amplifier difference output end.
The present invention has the advantages that：The present invention is set by four capacitance modules and data signal control module
Put, can realize that 5 grades of filter capacitor are adjustable, the adjustable range of loop parameter can be farthest met, so as to meet system
Requirement to loop parameter.Active filter of the invention increased two low pass limits, and clutter noise can be decayed.
The biasing circuit of operational amplifier of the invention can reduce noise using bulky capacitor.So the present invention can realize low noise, Gao Wen
Qualitatively active loop wave filter, and then the performance of ultra wide band phase-locked loop systems can be ensured.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structure chart of existing charge pump phase lock loop；
Fig. 2 is the phase model of existing charge pump phase lock loop；
Fig. 3 is the second order active loop filter circuit figure for being currently used for charge pump phase lock loop；
Fig. 4 A are the circuit diagrams of three rank active loop wave filter one for being currently used for charge pump phase lock loop；
Fig. 4 B are the circuit diagrams of three rank active loop wave filter two for being currently used for charge pump phase lock loop；
Fig. 5 is the active filter circuit figure that the embodiment of the present invention is used for phaselocked loop；
Fig. 6 is the circuit diagram of the Digital Signals module of the embodiment of the present invention；
Fig. 7 A are the circuit diagrams of the capacitance module structure of the embodiment of the present invention；
Fig. 7 B are the sub- condenser network figures of the capacitance module structure of the embodiment of the present invention；
Fig. 8 is the circuit diagram of the operational amplifier of the embodiment of the present invention；
Fig. 9 is the simulation result of the active filter of the embodiment of the present invention.
Specific embodiment
In the design of phaselocked loop, it is contemplated that the influence passive filter of the aspect such as cost, complexity, noise is than having
Source filter is more favourable, wherein what is be even more important is some the noise from active device.But at some in particular cases,
The characteristics of active filter still make its must not apply to design in, such as when voltage controlled oscillator adjustable voltage more than electricity
During the voltage that lotus pump can be supplied to, the use of active filter is exactly necessary.Need the voltage controlled oscillator of controllable voltage higher
It is very common in broadband application, the harmony device of such as cable television.Also it is very normal in low noise and high-power voltage controlled oscillator
See.Usual active loop wave filter is often selected more than second order, and the performance of active filter can be improved using multiple-order pole.This
Outward, higher order loop filters can allow broader loop bandwidth and more while identical phase demodulation spurious reduction is ensured
Phase demodulation frequency high, reduces frequency dividing ratio, so as to improve the in-band phase noise performance of phaselocked loop.Therefore, active loop is studied
The design of wave filter has great significance.
The phaselocked loop (CPLL) of charge pump construction has the advantages that to be easily integrated, low-power consumption, without difference locking, low jitter,
Thus it is used widely.Loop filter (LPF) is the pith of charge pump phase locking loop circuit, which determines phaselocked loop
Fundamental frequency characteristic.Due to the phase noise that active device can be introduced, therefore generally using passive filter as ring
Path filter.But when tuning broadband high pressure VCO, must active loop wave filter be used to provide output voltage higher.It is logical
Normal active loop wave filter is often selected more than second order, and the performance of active filter can be improved using multiple-order pole.Additionally, high-order
Loop filter can allow the phase demodulation of broader loop bandwidth and Geng Gao while identical phase demodulation spurious reduction is ensured
Frequency, reduces frequency dividing ratio, so as to improve the in-band phase noise performance of phaselocked loop.Therefore, active loop wave filter is studied
Design has great significance.
Charge pump phase lock loop structure is as shown in figure 1, be low including phase frequency detector 101, charge pump 102, loop filter
Bandpass filter 103, voltage controlled oscillator 104 and frequency divider 105.Phase frequency detector 101 compare two signals i.e. input signal ui and
The phase and difference on the frequency of the fractional frequency signal of output signal uopll, and produce control signal to charge pump 102, then charge pump 102
The discharge and recharge of loop filter 103 is correspondingly given, now the output frequency of voltage controlled oscillator 104 is proportional on loop filter 103
Control voltage uo, finally makes the reference clock frequency f of input signal uirWith the same same phase of frequency of the output signal of frequency divider 105, that is, press
The output signal frequency f of the output signal uopll of controlled oscillator 1040It is reference clock frequency frN times.
I.e.：f0=Nfr (1)
If a width of B of the band of input signal uir, then the output signal uopll bandwidth Bs for finally giving0For reference source is input into
Bandwidth BrN times.
I.e.：B0=NBr (2)
Charge pump phase lock loop is substantially a dynamical system for discrete time sampling, when loop bandwidth is far smaller than reference
During clock frequency, continuous-time approximation can be used；When phase error is in the range of the phase demodulation of PFD, can be using linear near
Seemingly.So when charge pump phase lock loop is in phase lock procedure, so that it may obtain a LINEAR CONTINUOUS time phase model, such as scheme
Shown in 2.
The wherein K of module 102adIt is phase detector gain that phase frequency detector (PFD) 101 and charge pump 102 are constituted together,
And have Kd=Icp/ 2 π, IcpIt is the charging and discharging currents of charge pump 102, the K of module 104avcoIt is the gain of voltage controlled oscillator 104, mould
The N of block 105a is the frequency dividing ratio of frequency divider 105, and the Z (s) of module 103a is the transfer function of loop filter 103.Locked in design
Phase loop serves the effect of frequency multiplication, and the noise of reference input deteriorates due to frequency multiplication.
SΦ.refF () is the noise power spectral density of reference input, SΦ.outF () is by output noise after phase-locked loop frequency multiplication
Power spectral density, according to signal theory, can obtain：
SΦ, out(∫)=| H (∫) |-N2.SΦ, ref(∫) (3)
Wherein, H (f) is the closed loop transfer function, of phaselocked loop：
Open-loop gain G (f)=KdKVCOZ (f)/j2 π are the monotone decreasings on frequency domain, therefore | H (f) | is presented low-pass characteristic,
Low-pass cut-off frequencies are fC, equal to the loop bandwidth of phaselocked loop.The less departure freqency scope f ＜ f in loop bandCPlace has | H
(f) | ≈ 1, the phase noise of now reference input influence of noise pll output signal.From formula (3), it is known that reference signal
The phase noise of input deteriorates 20lgN (dB) with spuious due to phase-locked loop frequency multiplication, thus frequency dividing ratio is unsuitable excessive, and relatively low
Frequency dividing ratio also imply that frequency resolution higher and improve lock speed；On the other hand, when frequency dividing ratio is relatively low, numeral
The output frequency bandwidth needs of formula frequency synthesizer (DDS) are sufficiently large, and this will necessarily increase output factors and phase noise.
The active loop wave filter for being generally used for phaselocked loop includes two kinds of simple gain type and feedback-type, in Practical Project
Use simple gain type, common is second order and third-order filter more.
Conventional second order active loop filter circuit is as shown in figure 3, ICPIt is the output current of charge pump 102, u0It is voltage-controlled
The control voltage of oscillator (VCO) 104.The circuit is generally used for the occasion of broader bandwidth, abundant by loop bandwidth and phase
Degree can be calculated filter parameter.
Can be obtained through analysis, the transmission function of second order active loop filter is：
In formulaτ2=R2C2,Ct=C1+C2；A is the multiplication factor of active loop wave filter, R2Correspondence
In resistance R2Resistance, C1Corresponding to electric capacity C1Capacitance, C2Corresponding to electric capacity C2Capacitance.
Therefore, phaselocked loop open-loop transmission function can be obtained：
S=j ω are substituted into above formula, then phaselocked loop open-loop frequency response function is：
The phase margin that can obtain phaselocked loop open-loop transmission function from (7) formula is：
Phase margin is sought to the differential of ω, and makes d ΦC/ d ω=0, can obtain the loop bandwidth of correspondence maximum phase nargin
ωC。
According to loop bandwidth ωCWith phase margin ΦC, τ can be obtained by (10), (11) formula1And τ2Value：
According to VCO control voltages, A=1+R is determinedb/RaValue, wherein, RaIt is resistance RaResistance value, RbIt is resistance Rb's
Resistance value；The parameter of loop filter can be tried to achieve by formula (12)~(15) again.
C2=Ct-C1 (14)
In actual applications, active loop wave filter is general all more than second order, and reason is active device operational amplifier
Output signal can be made increases extra phase noise, and the performance of active filter can be improved using multiple-order pole.Typically in VCO
Previous stage addition one series resistance and a shunt capacitance.The circuit increased a low pass limit for loop, can be right
Unwanted clutter noise is decayed.Conventional third order PLL path filter is as shown in Figure 4 A and 4 B shown in FIG..
Can be obtained through analysis, the transmission function of two kinds of three rank active loop wave filters of form is in Fig. 4：
In formulaτ2=R2C2；Ct=C1+C2；τ3=R3C3
Phaselocked loop open-loop transmission function：
S=j ω are substituted into above formula, then phaselocked loop open-loop frequency response function is：
The phase margin that can obtain phaselocked loop open-loop transmission function from (18) formula is：
Phase margin is sought to the differential of ω, and makes d Φ/d ω=0, the loop bandwidth of correspondence maximum phase nargin can be obtained
ωC。
Make τ3=τ 1T31
Wherein T31It is τ3And τ1Ratio, for the normal value 2.5 of active loop wave filter.Determine loop bandwidth ωCAnd phase
Nargin ΦCAfterwards, the value of τ 1, τ 2 and τ 3 can be tried to achieve by formula [5] (21)~(23).
τ3=τ1·T31 (23)
After trying to achieve the value of τ 1, τ 2 and τ 3, according to VCO control voltages, determine the i.e. A's of multiplication factor of active loop wave filter
Value, corresponding diagram 4B has, and the value of A=1+R4/R3, wherein R4 are the resistance value of resistance R4, and R3 is the resistance value of resistance R3；Again by formula
(24)~(29) can obtain the parameter of loop filter.
C2=Ct-C1 (27)
In order that the overall performance of phaselocked loop reaches most preferably, it should select suitable phase margin, loop bandwidth, and pass through
These parameters determine the concrete numerical value of loop filter.
Phase margin is closely related with the stability of system, is typically chosen between 40 °~55 °.Phase margin in theory
For 48 ° when have locking time of minimum, 50 ° of phase margin has the RMS phase errors of minimum.Bigger phase margin energy
Enough reduce the peak response of loop filter, but be the increase in locking time.
Loop bandwidth is the most important parameter of loop filter, if the loop bandwidth of selection is too small to improve reference spur
With RMS phase errors, but but increase locking time；The loop bandwidth of selection will improve locking time greatly very much, but can increase
Reference spur and RMS phase errors, therefore the loop bandwidth for selecting should meet the requirement of locking time, and a frequency is selected again
Rate makes PLL noise be equal to VCO noises, so that the design of RMS phase errors is optimal.Consider that design makes reference spur minimum, loop
Bandwidth is smaller, spuious lower.
As shown in figure 5, being the active filter circuit figure that the embodiment of the present invention is used for phaselocked loop；The embodiment of the present invention is used for
The active filter of phaselocked loop includes：Operational amplifier 1, the first MOS transistor M1, first resistor R101, second resistance R102,
3rd resistor R103, the 4th resistance R104, the first capacitance module C101, the second capacitance module C102, the 3rd capacitance module C103,
4th capacitance module C104 and data signal control module (ECP) 2.
The charge pump current Icp that the negative input end connection of the operational amplifier 1 is exported by the charge pump of phaselocked loop.
The positive input terminal of the operational amplifier connects the first bias current Ibias, the positive input of the operational amplifier 1
The first resistor R101 is connected between end and ground, the grid and the operational amplifier 1 of the first MOS transistor M1 are just
Input is connected, and the source electrode of the first MOS transistor M1 and drain electrode link together.The first resistor R101 and electric capacity connect
The the first MOS transistor M1 for connecing mode constitutes a low pass filter, and the first bias current Ibias passes through by described the
The low pass filter of one resistance R101 and the first MOS transistor M1 compositions is linked into the positive input of the operational amplifier
End, can reduce the additional noise that the first bias current Ibias is introduced.
The first capacitance module C101, the second capacitance module C102, the 3rd capacitance module C103 and described
4th capacitance module C104 includes four connection ends respectively, and the first connection end in is input, the second connection end out to export
End, the 3rd connection end are the first control end, the 4th connection end is the second control end.The first capacitance module C101 passes through first
Connection end in and the second connection end out and the second resistance R102 are connected on the negative input end of the operational amplifier 1 and defeated
Go out between end；The second capacitance module C102 is connected to the computing and puts by the first connection end in and the second connection end out
Greatly between the negative input end of device 1 and the output end of the operational amplifier 1；The 3rd resistor R103 is connected to the computing and puts
Greatly between the output end of device 1 and the first end of the 4th resistance R104, second end of the 4th resistance R104 has for described
The output end vo ut of source filter, the output end vo ut of the active filter exports control to the voltage controlled oscillator of the phaselocked loop
Voltage processed；The first connection end in and second that the first end of the 4th resistance R104 connects the 3rd capacitance module C103 connects
One in the out of end is met, another in the first connection end in and the second connection end out of the 3rd capacitance module C103 connects
Ground；Second end of the 4th resistance R104 connects the first connection end in and second connection end of the 4th capacitance module C104
One in out, another ground connection in the first connection end in and the second connection end out of the 4th capacitance module C104.
The Digital Signals module 2 includes 5 inputs control end and two data output ends, 5 inputs control
End processed receives 5 control signals, respectively Lpf_c0, Lpf_c1, Lpf_c2, Lpf_c3 and Lpf_c4.The data signal control
Molding block 2 forms two groups of data-signals and respectively from two data according to 5 control signals that described 5 input control ends are received
Output end is exported, and first group of data-signal is Calb in two groups of data-signals<4:0>, second group of data-signal is Cal<4:0>,
All for the data of 5 and two groups each correspondence positions of data-signal are anti-phase each other.
As shown in fig. 6, being the circuit diagram of the Digital Signals module of the embodiment of the present invention；The Digital Signals mould
Block 2 includes 5 groups of identical Digital Signals units, and each Digital Signals unit is anti-phase by together phase device 3 and respectively
Device 4 is constituted, and the input of the same phase device 3 connects one in 5 control signals, and the output end of the same phase device 3 connects
The input of the phase inverter 4 is connect, the output end of the same phase device 3 exports the in-phase signal of connected control signal, described
The output end of phase inverter 4 exports the inversion signal of connected control signal；As described in 5 Digital Signals units
The output end of phase inverter 4 constitutes the first data output end of the Digital Signals module 2 and exports first group of data
That is calb<4:0>, the data signal control is constituted by the output end of 5 described same phase devices 3 of the Digital Signals unit
Second data output end of molding block 2 simultaneously exports the i.e. cal of second group of data<4:0>.The same phase device 3 and the phase inverter
4 meet positive supply avdd by positive power source terminal vdd, and negative supply avss is met by negative power end vss.
The first capacitance module C101, the second capacitance module C102, the 3rd capacitance module C103 and described
3rd connection end of the 4th capacitance module C104 all connects the first data output end of the Digital Signals module 2, described
First capacitance module C101, the second capacitance module C102, the 3rd capacitance module C103 and the 4th capacitance module
4th connection end of C104 all connects the second data output end of the Digital Signals module 2.
As shown in Figure 7 A, be the embodiment of the present invention capacitance module structure 5 circuit diagram, as shown in Figure 7 B, be the present invention
The sub- condenser network figure of the capacitance module structure 5 of embodiment.The first capacitance module C101, second capacitance module
C102, the 3rd capacitance module C103 and the 4th capacitance module C104 use identical capacitance module structure 5；It is described
Capacitance module structure 5 includes six grades of sub- capacitor cells 6, and sub- electric capacity C100, the first PMOS are all included per the sub- capacitor cell 6 of one-level
MP1 and the first NMOS tube MN1, the first end per the sub- electric capacity C100 of one-level is switched by the first PMOS MP1 respectively
It is connected with the first connection end in of the capacitance module structure 5 and is switched and described by the first NMOS tube MN1
First connection end in of capacitance module structure 5 is connected, the second end and the capacitance module structure 5 per the sub- electric capacity C100 of one-level
Second connection end out is connected；The first PMOS MP1 and the first NMOS tube MN1 of the sub- capacitor cell 6 of the first order are turned on, and make institute
State the sub- electric capacity C100 of the first order be connected to always the capacitance module structure 5 the first connection end in and the second connection end out it
Between；The grid of the first PMOS MP1 of the sub- capacitor cell 6 in the second level connects first calb in first group of data-signal<0>、
The grid of the first NMOS tube MN1 connects first cal in second group of data-signal<0>；The first of the sub- capacitor cell 6 of the third level
The grid of PMOS MP1 connects the second calb in first group of data-signal<1>, the first NMOS tube MN1 grid connection the
Second cal in two groups of data-signals<1>；The grid of the first PMOS MP1 of the sub- capacitor cell 6 of the fourth stage connects first group
The 3rd calb in data-signal<2>, the first NMOS tube MN1 grid connect second group of data-signal in the 3rd cal<
2>；The grid of the first PMOS MP1 of the sub- capacitor cell 6 of level V connects the 4th calb in first group of data-signal<3>、
The grid of the first NMOS tube MN1 connects the 4th cal in second group of data-signal<3>；6th grade the first of sub- capacitor cell 6
The grid of PMOS MP1 connects the 5th calb in first group of data-signal<4>, the first NMOS tube MN1 grid connection the
The 5th cal in two groups of data-signals<4>；Controlled respectively by first group of data-signal and second group of data-signal
Make the sub- electric capacity in the second level, the sub- electric capacity of the third level, the sub- electric capacity of the fourth stage, the sub- electric capacity of the level V and described
The conducting and disconnection of the first end of six grades of sub- electric capacity and the first connection end in of the capacitance module structure 5, so as to adjust described
The capacitance size of capacitance module structure 5.
Amplifier is quite important as the core cell design in active filter, because it is in specific application, institute
Also not quite alike with common amplifier with its emphasis parameter value, the offset voltage of amplifier has no impact to system herein, and noise
The influence of voltage and noise current then to the phase noise of loop at amplifier bandwidth and outside bandwidth is very big.Another important ginseng
It is several, it is the switching rate of amplifier, its burr and locking time to loop all has an impact, if switching rate is too slow, can lead
Cause larger burr.And relative to locking time, switching rate influences then less substantially on it, unless locking time very little, then
Crossing slow conversion time can then cause locking time more long.Above principle is followed, the amplifier of the embodiment of the present invention is using such as Fig. 8
The fully differential Telescopic cascode structure of shown gain bootstrap, wherein should be noted that bias current can then be introduced and outer
Noise, in order to reduce the influence of noise, devise herein offset grid access larger capacitance come reduce its influence.
While with electric capacity and resistance composition wave filter, it shall be noted that form the structure of unit gain, so in the noise of input
The output end of wave filter would not be amplified to.As shown in figure 8, being the circuit diagram of the operational amplifier of the embodiment of the present invention；Institute
Fully differential Telescopic cascode structure of the operational amplifier 1 using gain bootstrap is stated, including：
Connect what is formed by the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 5th NMOS tube MN5
The source ground of fully differential cascode structure, the second NMOS tube MN2 and the 3rd NMOS tube MN3, grid are a pair
The input of differential signal vinp and vinn, the source electrode of the 4th NMOS tube MN4 connect the drain electrode of the second NMOS tube MN2,
The source electrode of the 5th NMOS tube MN5 connects the drain electrode of the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the described 5th
The drain electrode of NMOS tube MN5 is a pair of output ends of differential signal.
Connect what is formed by the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4 and the 5th PMOS MP5
Support structures, the drain electrode of drain electrode connection the 4th NMOS tube MN4 of the second PMOS MP2, the 3rd PMOS MP3
Drain electrode connection the 5th NMOS tube MN5 drain electrode, the drain electrode of the 4th PMOS MP4 connects second PMOS
The source electrode of MP2, the source electrode of drain electrode connection the 3rd PMOS MP3 of the 5th PMOS MP5, the 4th PMOS
The source electrode of MP4 and the 5th PMOS MP5 meets supply voltage VDD.
First sub- operational amplifier A 1, two differential input ends vi2- and vi2+ points of the first sub- operational amplifier A 1
The drain electrode of the second NMOS tube MN2 and the 3rd NMOS tube MN3, two of the first sub- operational amplifier A 1 are not connected
Difference output end vo2+ and vo2- connect the grid of the 4th NMOS tube MN4 and the 5th NMOS tube MN5 respectively.Described
One sub- operational amplifier A 1 is using the fully differential folding common source being made up of 2 the 6th PMOS MP6 and 2 the 6th NMOS tube MN6
Common gate structure, 2 the 6th PMOS MP6 are for common source amplifier tube and 2 grids of the 6th PMOS MP6 are used as institute
State the differential input end vi2- and vi2+ of the first sub- operational amplifier A 1,2 the 6th NMOS tube MN6 be common-gate amplifier tube simultaneously
And 2 drain electrodes of the 6th NMOS tube MN6 are used as the difference output end vo2+ and vo2- of the described first sub- operational amplifier A 1.
The current source being made up of two NMOS tubes, two described are connected between two source electrodes and ground of the 6th NMOS tube MN6
The active load being made up of 4 PMOSs is connected between the drain electrode of six NMOS tube MN6 and supply voltage VDD.
Second sub- operational amplifier A 2, two differential input ends vi1+ and vi1- points of the second sub- operational amplifier A 2
The drain electrode of the 4th PMOS MP4 and the 5th PMOS MP5, two of the second sub- operational amplifier A 2 are not connected
Difference output end vo1- and vo1+ connect the grid of the second PMOS MP2 and the 3rd PMOS MP3 respectively.Described
Two sub- operational amplifier A 2 is using the fully differential folding common source being made up of 2 the 7th NMOS tube MN7 and 2 the 7th PMOS MP7
Common gate structure, 2 the 7th NMOS tube MN7 are for common source amplifier tube and 2 grids of the 7th NMOS tube MN7 are used as institute
State the differential input end vi1+ and vi1- of the second sub- operational amplifier A 2,2 the 7th PMOS MP7 be common-gate amplifier tube simultaneously
And 2 drain electrodes of the 7th PMOS MP7 are used as the difference output end vo1- and vo1+ of the described second sub- operational amplifier A 2.
The active load being made up of four NMOS tubes is connected between the drain electrode of two the 7th PMOS MP7 and ground, described in two
The current source being made up of 2 PMOSs is connected between the source electrode and supply voltage VDD of the 7th PMOS MP7.
The embodiment of the present invention can realize filter capacitor by the setting of four capacitance modules and data signal control module
5 grades it is adjustable, the adjustable range of loop parameter can be farthest met, so as to meet requirement of the system to loop parameter.This
Active filter in inventive embodiments increased two low pass limits, and clutter noise can be decayed.The present invention is implemented
The biasing circuit of example operational amplifier can reduce noise using bulky capacitor.So the present invention can realize low noise, high stability
Active loop wave filter, and then the performance of ultra wide band phase-locked loop systems can be ensured.In order to the test design embodiment of the present invention is active
The performance of loop filter, phase discriminator and charge pump are accessed in its prime, and 480MHz is in incoming frequency, and input is advanced anti-
Emulated during feedback signal 800ps, simulation result is as shown in figure 9, wherein curve up and down are to be exported by the phase discriminator
Rise control signal and decline control signal, curve Vout is the output of the output end vo ut of the active filter of the embodiment of the present invention
Signal, by simulation result it can be seen that Vout voltage also has the fluctuation of smaller decline while growing steadily, because electric
Caused by the smaller mismatch that lotus pump is present, but it is smaller due to fluctuating, the performance of whole phaselocked loop is had no effect on, have on the whole
Effect eliminates the influence of noise of active filter.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (4)
1. a kind of active filter for phaselocked loop, it is characterised in that active filter includes：Operational amplifier, a MOS
Transistor, first resistor, second resistance, 3rd resistor, the 4th resistance, the first capacitance module, the second capacitance module, the 3rd electric capacity
Module, the 4th capacitance module and data signal control module；
The charge pump current that the negative input end connection of the operational amplifier is exported by the charge pump of phaselocked loop；
The positive input terminal of the operational amplifier connects the first bias current, between the positive input terminal and ground of the operational amplifier
Connect the first resistor, the positive input terminal connection of the grid and the operational amplifier of first MOS transistor, described the
The source electrode of one MOS transistor and drain electrode link together；
First capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module all divide
Not Bao Kuo four connection ends, the first connection end be input, the second connection end be output end, the 3rd connection end be first control
End, the 4th connection end is the second control end；
First capacitance module is connected on the computing by the first connection end and the second connection end with the second resistance
Between the negative input end and output end of amplifier；
Second capacitance module is connected to the negative input end of the operational amplifier by the first connection end and the second connection end
And the output end of the operational amplifier between；
The 3rd resistor is connected between the first end of the output end of the operational amplifier and the 4th resistance, and described
Second end of four resistance is the output end of the active filter, pressure from the output end of the active filter to the phaselocked loop
Controlled oscillator output control voltage；
The first end of the 4th resistance connects in first connection end and the second connection end of the 3rd capacitance module,
Another ground connection in first connection end and the second connection end of the 3rd capacitance module；Second end of the 4th resistance connects
Meet in first connection end and the second connection end of the 4th capacitance module, the first connection of the 4th capacitance module
Another ground connection in end and the second connection end；
The Digital Signals module includes 5 inputs control end and two data output ends, 5 inputs control termination
5 control signals are received, the Digital Signals module is formed according to 5 control signals that described 5 input control ends are received
Two groups of data-signals and respectively from the output of two data output ends, two groups of data-signals are each all for 5 and two groups data-signals
The data of correspondence position are anti-phase each other；
The of first capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module
Three connection ends all connect the first data output end of the Digital Signals module, first capacitance module, described second
4th connection end of capacitance module, the 3rd capacitance module and the 4th capacitance module all connects the Digital Signals
Second data output end of module；
First capacitance module, second capacitance module, the 3rd capacitance module and the 4th capacitance module are all adopted
With identical capacitance module structure；
The capacitance module structure includes six grades of sub- capacitor cells, and sub- electric capacity, a PMOS are all included per the sub- capacitor cell of one-level
Pipe and the first NMOS tube, the first end per the sub- electric capacity of one-level pass through first switching pmos and the electric capacity mould respectively
First connection end of block structure be connected and switched by first NMOS tube and the capacitance module structure first
Connection end is connected, and the second end per the sub- electric capacity of one-level is connected with the second connection end of the capacitance module structure；
First PMOS and the first NMOS tube of the sub- capacitor cell of the first order are all turned on, and the sub- electric capacity of the first order is connected always
Between first connection end and the second connection end of the capacitance module structure；
The grid of the first PMOS of the sub- capacitor cell in the second level connects first in first group of data-signal, the first NMOS tube
Grid connect second group of data-signal in first；The grid connection first of the first PMOS of the sub- capacitor cell of the third level
Second in group data-signal, the grid of the first NMOS tube connects the second in second group of data-signal；Fourth stage electricity
Hold the 3rd that the grid of the first PMOS of unit is connected in first group of data-signal, the grid connection second of the first NMOS tube
The 3rd in group data-signal；The grid of the first PMOS of the sub- capacitor cell of level V is connected in first group of data-signal
4th, the grid of the first NMOS tube connects the 4th in second group of data-signal；6th grade the first of sub- capacitor cell
The grid of PMOS connects the 5th in first group of data-signal, in grid second group of data-signal of connection of the first NMOS tube
The 5th；
The sub- electric capacity in the second level, described are controlled by first group of data-signal and second group of data-signal respectively
The first end of the sub- electric capacity of three-level, the sub- electric capacity of the fourth stage, the sub- electric capacity of the level V and the 6th grade of sub- electric capacity and described
The conducting and disconnection of the first connection end of capacitance module structure, so as to adjust the capacitance size of the capacitance module structure.
2. the active filter of phaselocked loop is used for as claimed in claim 1, it is characterised in that：The Digital Signals module
Including 5 groups of identical Digital Signals units, each Digital Signals unit is respectively by together phase device and a phase inverter group
Into the input of the same phase device connects one in 5 control signals, and the output end connection of the same phase device is described anti-
The input of phase device, the output end of the same phase device exports the in-phase signal of connected control signal, the phase inverter it is defeated
Go out the inversion signal of the connected control signal of end output；By the defeated of 5 phase inverters of the Digital Signals unit
Go out the first data output end of the end composition Digital Signals module and export first group of data, by 5 numbers
The output end of the described same phase device of word signaling control unit constitutes the second data output end of the Digital Signals module simultaneously
Export second group of data.
3. the active filter of phaselocked loop is used for as claimed in claim 1, it is characterised in that：The operational amplifier is using increasing
The fully differential Telescopic cascode structure of benefit bootstrapping, including：
The fully differential cascade knot for being formed is connected by the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube
The source ground and grid of structure, second NMOS tube and the 3rd NMOS tube are a pair of inputs of differential signal, described
The source electrode of the 4th NMOS tube connects the drain electrode of second NMOS tube, and the source electrode of the 5th NMOS tube connects the 3rd NMOS tube
The drain electrode of drain electrode, the 4th NMOS tube and the 5th NMOS tube is a pair of output ends of differential signal；
The support structures for being formed, described second are connected by the second PMOS, the 3rd PMOS, the 4th PMOS and the 5th PMOS
The drain electrode of drain electrode connection the 4th NMOS tube of PMOS, drain electrode connection the 5th NMOS tube of the 3rd PMOS
Drain electrode, the source electrode of drain electrode connection second PMOS of the 4th PMOS, the drain electrode connection institute of the 5th PMOS
State the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and the 5th PMOS connects supply voltage；
First sub- operational amplifier, two differential input ends of the first sub- operational amplifier connect the 2nd NMOS respectively
The drain electrode of pipe and the 3rd NMOS tube, two difference output ends of the first sub- operational amplifier connect the described 4th respectively
The grid of NMOS tube and the 5th NMOS tube；
Second sub- operational amplifier, two differential input ends of the second sub- operational amplifier connect the 4th PMOS respectively
The drain electrode of pipe and the 5th PMOS, two difference output ends of the second sub- operational amplifier connect described second respectively
The grid of PMOS and the 3rd PMOS.
4. the active filter of phaselocked loop is used for as claimed in claim 3, it is characterised in that：The first sub- operational amplifier
Using the fully differential folded cascode configuration being made up of 2 the 6th PMOSs and 2 the 6th NMOS tubes, 2 the described 6th
PMOS is defeated as the difference of the described first sub- operational amplifier for the grid of common source amplifier tube and 2 the 6th PMOSs
Enter end, 2 the 6th NMOS tubes are that common-gate amplifier tube and 2 drain electrodes of the 6th NMOS tube are transported as the described first son
Calculate the difference output end of amplifier；
The second sub- operational amplifier is folded altogether using the fully differential being made up of 2 the 7th NMOS tubes and 2 the 7th PMOSs
Source common gate structure, 2 the 7th NMOS tubes are common source amplifier tube and 2 grids of the 7th NMOS tube as described the
The differential input end of two sub- operational amplifiers, 2 the 7th PMOSs are common-gate amplifier tube and 2 the 7th PMOSs
Drain electrode as the described second sub- operational amplifier difference output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310329487.3A CN104348481B (en) | 2013-07-31 | 2013-07-31 | For the active filter of phaselocked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310329487.3A CN104348481B (en) | 2013-07-31 | 2013-07-31 | For the active filter of phaselocked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104348481A CN104348481A (en) | 2015-02-11 |
| CN104348481B true CN104348481B (en) | 2017-06-06 |
Family
ID=52503425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310329487.3A Active CN104348481B (en) | 2013-07-31 | 2013-07-31 | For the active filter of phaselocked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104348481B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111165A (en) * | 2018-01-31 | 2018-06-01 | 成都泰格微电子研究所有限责任公司 | A kind of fast frequency-hopped locking phase locked source |
| CN113595548B (en) * | 2021-06-24 | 2023-11-03 | 北京邮电大学 | Phase locking device and system capable of adaptively adjusting bandwidth |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85104174A (en) * | 1985-05-24 | 1986-12-31 | 夏敖敖 | Filter with same frequency |
| US4754226A (en) * | 1983-11-02 | 1988-06-28 | Stanford University | Switched capacitor function generator |
| CN101895264A (en) * | 2010-07-09 | 2010-11-24 | 复旦大学 | High-speed low-power consumption large-swing operational amplifier for analog-digital converter of production line |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0793553B2 (en) * | 1983-11-18 | 1995-10-09 | 株式会社日立製作所 | Switched capacitor filter |
| JPS61285809A (en) * | 1985-06-12 | 1986-12-16 | Nec Corp | Totally differential analog circuit |
-
2013
- 2013-07-31 CN CN201310329487.3A patent/CN104348481B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4754226A (en) * | 1983-11-02 | 1988-06-28 | Stanford University | Switched capacitor function generator |
| CN85104174A (en) * | 1985-05-24 | 1986-12-31 | 夏敖敖 | Filter with same frequency |
| CN101895264A (en) * | 2010-07-09 | 2010-11-24 | 复旦大学 | High-speed low-power consumption large-swing operational amplifier for analog-digital converter of production line |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104348481A (en) | 2015-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7400183B1 (en) | Voltage controlled oscillator delay cell and method | |
| CN103501175B (en) | A kind of millimeter wave phase-locked loop | |
| CN104202048B (en) | Broadband totally-integrated phase-locked loop frequency synthesizer | |
| CN103297041B (en) | Phase-locked loop circuit | |
| CN106788417A (en) | Using the low-noise phase-locked loop circuit of sub-sampling technology | |
| CN107896108B (en) | Charge pump circuit for phase locked loop | |
| CN105207670B (en) | It is segmented low pressure control gain ring oscillator and tuning slope change-over circuit | |
| CN101557213A (en) | Delay unit, annular oscillator and PLL circuit | |
| CN104348481B (en) | For the active filter of phaselocked loop | |
| CN106506001B (en) | A kind of high-performance VCO circuit applied to PLL | |
| CN106444344B (en) | A kind of high stable clock generation circuit based on automatic biasing frequency-locked loop | |
| CN104242923B (en) | Voltage controlled oscillator | |
| Chen et al. | A 0.13 um low phase noise and fast locking PLL | |
| US8536912B2 (en) | Phase locked loop | |
| CN110557119B (en) | Cascaded DAC feedback phase-locked loop of radio frequency millimeter wave subsampling | |
| CN208015710U (en) | A kind of High Performance Charge Pumps applied in phaselocked loop | |
| CN109547018A (en) | Multi-bias voltage-controlled oscillator with anti-irradiation function | |
| CN114024506B (en) | Open-loop crystal oscillator circuit | |
| CN107911112A (en) | A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology | |
| CN115102544A (en) | Low-noise broadband millimeter wave frequency source based on multiphase injection locking | |
| CN103795409B (en) | Phaselocked loop | |
| CN115118277A (en) | Charge pump, phase-locked loop and method for improving reference stray of phase-locked loop | |
| CN108540129A (en) | A kind of phase-locked loop circuit of the voltage controlled oscillator containing binary channel | |
| CN205566265U (en) | Phase -locked loop circuit that does not need loop filter | |
| CN213426145U (en) | Phase-locked loop circuit with high power supply noise rejection ratio |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |