CN105576084A - N-type IBC cell structure and preparation method thereof - Google Patents
N-type IBC cell structure and preparation method thereof Download PDFInfo
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- CN105576084A CN105576084A CN201610152526.0A CN201610152526A CN105576084A CN 105576084 A CN105576084 A CN 105576084A CN 201610152526 A CN201610152526 A CN 201610152526A CN 105576084 A CN105576084 A CN 105576084A
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- 238000002360 preparation method Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 135
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 135
- 239000010703 silicon Substances 0.000 claims abstract description 135
- 238000002161 passivation Methods 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 31
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 24
- 229910052796 boron Inorganic materials 0.000 claims description 24
- 229910052698 phosphorus Inorganic materials 0.000 claims description 24
- 239000011574 phosphorus Substances 0.000 claims description 24
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 21
- 238000007650 screen-printing Methods 0.000 claims description 21
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 18
- 235000008216 herbs Nutrition 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 15
- 239000012528 membrane Substances 0.000 claims description 15
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 210000002268 wool Anatomy 0.000 claims description 14
- 238000007639 printing Methods 0.000 claims description 13
- 239000000243 solution Substances 0.000 claims description 13
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 12
- 239000005297 pyrex Substances 0.000 claims description 12
- 238000000608 laser ablation Methods 0.000 claims description 8
- 239000002002 slurry Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000005245 sintering Methods 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000011259 mixed solution Substances 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000010329 laser etching Methods 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 229910000077 silane Inorganic materials 0.000 description 6
- 239000008367 deionised water Substances 0.000 description 5
- 229910021641 deionized water Inorganic materials 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- -1 hexafluorosilicic acid Chemical compound 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 235000013842 nitrous oxide Nutrition 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
- 238000003756 stirring Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an IBC cell structure and a manufacturing technology method thereof, and mainly solves the problems in the prior art that the IBC cell manufacturing technology is complex and manufacturing cost is high. The N-type IBC cell comprises an anti-reflection layer, a silicon substrate, doping layers, a passivation layer and metal electrodes. The N-type IBC cell is characterized in that the anti-reflection layer is arranged at the front surface of the silicon substrate. The silicon doping layers comprise an n+ heavily doping layer and a p+ heavily doping layer. The n+ heavily doping layer and the p+ heavily doping layer are arranged at the back surface of the silicon substrate in parallel. The passivation layer is arranged on the n+ heavily doping layer and the p+ heavily doping layer. The metal electrodes are led out of the n+ heavily doping layer and the p+ heavily doping layer to the back surface of the passivation layer. The anti-reflection layer and the passivation layer of a SiNx film or a laminated film are adopted so that the existing cell structure is simplified, production efficiency is enhanced and production cost is reduced.
Description
Technical field
The present invention relates to technical field of solar batteries, particularly a kind of N-type IBC battery structure and preparation method thereof, can be used for photovoltaic generation.
Prior art
Solar energy power generating because it is clean, safety, facility, the feature such as efficient, the new industry having become countries in the world common concern and given priority to.Therefore, further investigate and utilize solar energy resources, alleviation crisis of resource, tool of improving the ecological environment are of great significance.
IBC battery technology breaks traditions from structure the structural limitations of crystal silicon battery, and provide larger space for improving battery conversion efficiency, current industrialization battery efficiency reaches 23%.Look forward to the future, the N-type crystalline silicon battery of transformation efficiency more than 21% has become the development trend of conventional crystal silicon solar cell, is the forward position of current international research and industrialization.
For conventional N-type IBC battery, as shown in Figure 1, the basic structure of IBC battery comprises: N-type silicon chip matrix 100, and the surface of N-type silicon chip matrix is N+ doped layer 101, passivation layer 102 and antireflection layer 103 from inside to outside successively; The back side of N-type silicon chip matrix be spaced, the N+ doped region 104 of pectination and P+ doped region 105, surface, N+ doped region 104 is passivation layer 106 from inside to outside successively, increase reflector 108 and surface, negative electrode 109, P+ doped region 105 is passivation layer 107 from inside to outside successively, increases reflector 108 and positive electrode 110.
The technological process of the conventional IBC of making battery is roughly: go damage layer and making herbs into wool-Double side diffusion to form N+ layer-etch and go PSG-deposit or printing to form mask-corrosion to form P+ doped region-diffuse to form P+ doped layer-is formationed front passivation layer and antireflection layer-backside mask and form N+ surface passivation layer-backside mask and form P+ surface passivation layer-formation increasing reflector, the back side-etching formation electrode contact figure-print electrode-sinter.
Below be only the key step making IBC battery, and in actual production process, the making of IBC battery relates to very many ins and outs and corresponding operating procedure, make IBC battery production technology complicated, manufacturing cost is high, yields is lower, have impact on the development of IBC battery.
Goal of the invention
The invention provides a kind of IBC battery structure and process for making thereof, to simplify the manufacture craft of IBC battery, enhance productivity and yields, and reduce its production cost.
Summary of the invention
Technical thought of the present invention is: the structure simplifying IBC battery, and its technical scheme is as follows:
A kind of N-type IBC battery, comprise anti-reflection layer, N-type silicon chip matrix, doped layer, passivation layer and metal electrode, it is characterized in that: anti-reflection layer is located at the front of N-type silicon chip matrix, silicon doping layer comprises n+ heavily doped layer and p+ heavily doped layer, this n+ heavily doped layer back side of being located at N-type silicon chip matrix parallel with p+ heavily doped layer, passivation layer is located at above n+ heavily doped layer and p+ heavily doped layer; N+ heavily doped layer, p+ heavily doped layer are drawn metal electrode to the passivation layer back side.
The method making above-mentioned N-type IBC battery provides following three kinds of technical schemes:
Technical scheme 1:
Prepare a method for N-type IBC battery, comprise the steps:
(1) the two-sided making herbs into wool of N-type silicon chip: N-type silicon chip is placed in NaOH solution reaction 20 ~ 30min that mass fraction is 1% ~ 3%, carries out two-sided making herbs into wool and to silicon polished backside;
(2) in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
(3) silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index be 1.8 ~ 2.5 SiNx mask;
(4) silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
(5) employing concentration is the HF solution of 10% ~ 15%, removes phosphorosilicate glass PSG, Pyrex BSG and backside mask;
(6) adopt PECVD method to be 50nm ~ 200nm at doped layer back side deposition thickness, refractive index is the SiN of 2.0 ~ 2.3
xfilm is as passivation layer;
(7) adopt PECVD to be 60nm ~ 100nm at front side of silicon wafer deposit thickness, refractive index is the SiN of 1.8 ~ 2.3
xfilm is as antireflective film;
(8) form electrode contact figure in passivation layer backside laser etching, its laser ablation width is 30 μm ~ 80 μm, and etching depth is 50nm ~ 200nm, to remove passivation layer and not damage the silicon chip surface of doped layer;
(9) at the silicon chip back side depositing metal Ag/Al layer forming electrode contact figure, make electrode, complete the making of N-type IBC battery.
Technical scheme 2:
Prepare a method for N-type IBC battery, comprise the steps:
1) the two-sided making herbs into wool of N-type silicon chip: N-type silicon chip is placed in KOH solution reaction 20 ~ 30min that mass fraction is 1% ~ 3%, carries out two-sided making herbs into wool and to silicon polished backside;
2) in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
3) silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index is the SiN of 1.8 ~ 2.5
xmask;
4) silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
5) adopt the mixed solution of HF and HCL, remove backside mask and phosphorosilicate glass PSG, Pyrex BSG, wherein HF concentration is 3%-15%, HCL concentration is 5%-30%;
6) PECVD is adopted to deposit SiO at front side of silicon wafer
2/ Si
3n
4stack membrane as anti-reflection layer, wherein SiO
2film thickness is 10nm ~ 30nm, and refractive index is 1.4 ~ 1.7, Si
3n
4the thickness of film is 50nm ~ 70nm, and refractive index is 1.8 ~ 2.2;
7) adopt PECVD method at doped layer back side deposit SiO
2/ Si
3n
4stack membrane as passivation layer, wherein SiO
2film thickness is 15nm ~ 50nm, and refractive index is 1.4 ~ 1.7, Si
3n
4the thickness of film is 30nm ~ 150nm, and refractive index is 1.8 ~ 2.2;
8) carrying out width at the passivation layer back side is 30 μm ~ 80 μm, and the degree of depth is the laser ablation of 45nm ~ 200nm, forms electrode contact figure, to remove passivation layer and not damage the silicon chip surface of doped layer;
9) carry out silk screen printing at the silicon chip back side silver slurry forming electrode contact figure and form electrode pattern, then carry out high temperature sintering formation silver electrode, complete the making of N-type IBC battery.
Technical scheme 3:
A preparation method for N-type IBC battery, comprises the steps:
The first step: N-type silicon chip is placed in mass fraction be 1% ~ 3% NaOH solution react 20-30min, carry out two-sided making herbs into wool and to silicon polished backside;
Second step: in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
3rd step: silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index is the SiN of 1.8 ~ 2.5
xmask;
4th step: silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
5th step: the mixed solution adopting HF and HCL, remove Pyrex BSG, phosphorosilicate glass PSG and backside mask, wherein the concentration of HF is the concentration of 3%-15%, HCL is 5%-30%;
6th step: adopt PECVD to be 60nm ~ 100nm at front side of silicon wafer deposit thickness, refractive index is 1.8 ~ 2.3; SiN
xfilm is as anti-reflection layer;
7th step: adopt PECVD method at doped layer back side deposit Al
2o
3/ Si
3n
4stack membrane as passivation layer, wherein Al
2o
3the thickness of film is 15nm ~ 50nm, and refractive index is 1.3 ~ 1.6, Si
3n
4the thickness of film is 30nm ~ 150nm, and refractive index is 1.8 ~ 2.2;
8th step: form electrode contact figure in passivation layer backside laser etching, wherein laser ablation width is 30 μm ~ 80 μm, and etching depth is 45nm ~ 200nm, to remove passivation layer and not damage the silicon chip surface of doped layer;
9th step: carry out silk screen printing at the silicon chip back side aluminium paste forming electrode contact figure and form electrode pattern, then carry out high temperature sintering formation aluminium electrode, complete the making of N-type IBC battery.
The present invention has following beneficial effect:
The present invention is owing to adopting SiN at battery front side
xfilm or SiO
2/ Si
3n
4stack membrane replaces existing structure due to middle N+ doped layer, passivation layer and antireflection layer as anti-reflection layer, adopts SiN at cell backside
xfilm or SiO
2/ Si
3n
4or Al
2o
3/ Si
3n
4stack membrane replaces passivation layer in existing structure as passivation layer, increases reflector, thus simplifies battery structure and manufacturing process steps; In addition because the present invention uses silk-screen printing technique to replace photoetching process to form n+ and p+ doped layer, also greatly simplify IBC battery process flow process, improve production efficiency, reduce production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing conventional IBC battery;
Fig. 2 is the structural representation of IBC battery of the present invention;
Fig. 3 is the Making programme figure of a kind of N-type IBC battery structure of the present invention;
Fig. 4 is the Making programme figure of another kind of N-type IBC battery structure of the present invention.
Embodiment
With reference to Fig. 1, existing IBC battery structure comprises:
N-type silicon chip matrix 100, the surface of N-type silicon chip matrix is N+ doped layer 101, passivation layer 102 and antireflection layer 103 from inside to outside successively; The back side of N-type silicon chip matrix is by the N+ doped region 104 and the P+ doped region 105 that are spaced pectination, surface, N+ doped region 104 is passivation layer 106 from inside to outside successively, increase reflector 108 and surface, negative electrode 109, P+ doped region 105 is passivation layer 107 from inside to outside successively, increases reflector 108 and positive electrode 110.
With reference to Fig. 2, IBC battery structure of the present invention comprises: anti-reflection layer, N-type silicon chip matrix, doped layer, passivation layer and negative electrode and positive electrode, wherein: anti-reflection layer is located at the front of N-type silicon chip matrix, doped layer comprises n+ heavily doped layer and p+ heavily doped layer, this n+ heavily doped layer back side of being located at N-type silicon chip matrix parallel with p+ heavily doped layer, passivation layer is located at above n+ heavily doped layer and p+ heavily doped layer; N+ heavily doped layer, p+ heavily doped layer are drawn negative electrode and positive electrode to the passivation layer back side
Front side of silicon wafer anti-reflection layer adopts SiN
xfilm or SiO
2/ Si
3n
4stack membrane can be grown by chemical gas-phase deposition method, only needs a processing step to realize.
Silicon chip back side n+ doped layer, p+ doped layer adopt same passivating structure, and this passivating structure has passivation and increases back reflection double effects, adopts SiN
xfilm or SiO
2/ Si
3n
4or Al
2o
3/ Si
3n
4stack membrane, can be grown by chemical gas-phase deposition method, only needs a processing step to realize.
With reference to Fig. 3 and Fig. 4, the present invention makes the method for above-mentioned N-type IBC battery structure, provides following three kinds of embodiments:
Embodiment 1, prepares the N-type IBC battery of lamination anti-reflection layer and overlayer passivation layer.
Step one: carry out two-sided making herbs into wool in N-type silicon chip.
First N-type silicon chip is cleaned, remove surface contaminant;
Again N-type silicon chip is placed in mass fraction be 1% KOH solution stir, make itself and silicon chip tow sides fully react 20min, according to anisotropic corrosion principle, form gold turriform matte at N-type silicon chip tow sides;
After making herbs into wool completes, at N-type silicon chip front gluing, the NaOH solution being greater than 5% by concentration washes away the N-type silicon chip back side, carries out polishing to silicon chip back side;
Remove front colloid, and use deionized water rinsing N-type silicon chip.
Step 2: silk screen printing phosphorus source and boron source.
The first silk screen printing width of silicon chip back side be the Pyrex slurry of 50 μm as boron source, then silk screen printing width is that the phosphorosilicate glass slurry of 30 μm is as phosphorus source.
Step 3: deposit SiN
xmask.
Adopt at silicon chip back side that PECVD deposit a layer thickness is 75nm, refractive index is the SiN of 1.8
xmask, as mask layer during diffusion, preventing the Na+ ion in diffusion furnace from entering into silicon chip affects N-type silicon chip characteristic.
Step 4: High temperature diffusion forms n+ and p+ doped layer.
Silicon chip is placed in diffusion furnace, spread 90 minutes under temperature 800 DEG C of environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in N-type silicon chip, form n+ and p+ doped layer respectively, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15ohm/, p+ doped layer is 20ohm/.
Step 5: remove phosphorosilicate glass, Pyrex and SiN
xmask.
The silicon chip spread is immersed in HF concentration is 3%, HCL concentration is react in the mixed solution of 30%, makes itself and silicon chip back side phosphorosilicate glass PSG, Pyrex BSG and SiN
xmask simultaneous reactions, generates the complex compound hexafluorosilicic acid of solubility, more repeatedly rinses well with deionized water.
Step 6: deposit lamination anti-reflection layer.
The silicon chip cleaned in step 5 is put into PECVD device reative cell, passes into silane SiH
4with laughing gas N
2o, first is 10nm at front side of silicon wafer deposit thickness, and refractive index is the SiO of 1.4
2film;
Pass into silane and ammonia NH again
3, at SiO
2on film, deposition thickness is 50nm, and refractive index is the Si of 2.2
3n
4film, thus form SiO in N-type silicon chip front
2/ Si
3n
4stack membrane is as anti-reflection layer.
Step 7: deposit overlayer passivation layer.
SiO has been grown by step 6
2/ Si
3n
4stack membrane surface coating is protected, and the back side is upwards placed in PECVD device reative cell;
Pass into silane SiH
4with laughing gas N
2o is 15nm at n+ and p+ doped layer deposition thickness, and refractive index is the SiO of 1.4
2film.
Pass into silane and ammonia NH again
3, at SiO
2on film, deposition thickness is 30nm, and refractive index is the Si of 2.2
3n
4film, thus SiO is formed on n+ and p+ doped layer
2/ Si
3n
4stack membrane is as passivation layer.
Step 8: photoetching passivation layer forms contact pattern.
Carrying out width at the passivation layer back side is 30 μm, and the degree of depth is the laser ablation of 45nm, forms the groove of electrode contact figure, to remove passivation layer and not damage the silicon chip surface of doped layer.
Step 9: screen printing electrode, completes battery and makes.
The silver slurry being 50nm at the back side thickness of step 8 silicon chip carries out silk screen printing formation electrode pattern and covers the groove formed in step 8, high temperature sintering is carried out again at 850 DEG C, to form width be the negative electrode of 40 μm and width is the positive electrode of 40 μm, completes the making of N-type IBC battery.
Embodiment 2, prepares the N-type IBC battery of individual layer anti-reflection layer and individual layer passivation layer.
Step 1: carry out two-sided making herbs into wool in N-type silicon chip.
First N-type silicon chip is cleaned, remove surface contaminant;
Again N-type silicon chip is placed in mass fraction be 3% NaOH solution stir, make itself and silicon chip tow sides fully react 30min, according to anisotropic corrosion principle, form gold turriform matte at N-type silicon chip tow sides;
After making herbs into wool completes, at N-type silicon chip front gluing, the NaOH solution being greater than 5% by concentration washes away the N-type silicon chip back side, carries out polishing to silicon chip back side;
Remove front colloid, and use deionized water rinsing N-type silicon chip.
Step 2: silk screen printing phosphorus source and boron source.
The first silk screen printing width of silicon chip back side be the Pyrex slurry of 1.5mm as boron source, then silk screen printing width is that the phosphorosilicate glass slurry of 1.5mm is as phosphorus source.
Step 3: deposit SiN
xmask.
Adopt at silicon chip back side that PECVD deposit a layer thickness is 200nm, refractive index is the SiN of 2.5
xmask, as mask layer during diffusion, preventing the Na+ ion in diffusion furnace from entering into silicon chip affects N-type silicon chip characteristic.
Step 4: High temperature diffusion forms n+ and p+ doped layer.
Silicon chip is placed in diffusion furnace, spread 40 minutes under temperature 1000 DEG C of environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in N-type silicon chip, form n+ and p+ doped layer respectively, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 60ohm/, p+ doped layer is 80ohm/.
Step 5: remove phosphorosilicate glass, Pyrex and SiNx mask.
The silicon chip spread being immersed in concentration is react in the HF solution of 15%, makes itself and silicon chip back side phosphorosilicate glass PSG, Pyrex BSG and SiN
xmask simultaneous reactions, generates the complex compound hexafluorosilicic acid of solubility, more repeatedly rinses well with deionized water.
Step 6: deposit individual layer passivation layer.
PSG, BSG and SiN is removed by step 5
xsilicon chip back side upwards put into PECVD device reative cell;
Pass into silane and ammonia NH
3, deposit SiN on n+ and p+ doped layer
xthickness is 200nm, and refractive index is the SiN of 2.3
xfilm is as passivation layer.
Step 7: deposit individual layer anti-reflection layer.
By deposit SiN in step 6
xthe silicon chip back side Coating glue protect of passivation layer puts into PECVD device reative cell;
Pass into silane and ammonia NH again
3, be 100nm at N-type silicon chip front deposition thickness, refractive index is the SiN of 2.3
xfilm, as anti-reflection layer;
Remove front colloid, and clean with deionized water rinsing.
Step 8: photoetching passivation layer forms contact pattern.
Carrying out width at the passivation layer back side is 80 μm, and the degree of depth is the laser ablation of 200nm, forms the groove of electrode contact figure, to remove passivation layer and not damage the silicon chip surface of doped layer.
Step 9: depositing metal layers, annealing also lithography stripping forms deposit.
At the Ag layer that the silicon chip back side Atomic layer deposition method ALD deposit thickness forming electrode contact figure is 100nm, then deposit thickness is the Al layer of 5 μm, and carries out rapid thermal anneal process at 850 DEG C of temperature, forms ohmic contact respectively with n+ and p+ heavily doped layer,
Carry out lithography stripping again, to form width be the negative electrode of 40 μm and width is the positive electrode of 60mm, completes the making of N-type IBC battery.
Embodiment 3, prepares the N-type IBC battery of overlayer passivation layer and individual layer anti-reflection layer.
Steps A: carry out two-sided making herbs into wool in N-type silicon chip.
First N-type silicon chip is cleaned, remove surface contaminant; Again N-type silicon chip is placed in mass fraction be 2% NaOH solution stir, make itself and silicon chip tow sides fully react 25min, according to anisotropic corrosion principle, form gold turriform matte at N-type silicon chip tow sides; After making herbs into wool completes, at N-type silicon chip front gluing, the NaOH solution being greater than 5% by concentration washes away the N-type silicon chip back side, carries out polishing to silicon chip back side; Remove front colloid, and use deionized water rinsing N-type silicon chip.
Step B: silk screen printing phosphorus source and boron source.
The first silk screen printing width of silicon chip back side be the Pyrex slurry of 1mm as boron source, then silk screen printing width is that the phosphorosilicate glass slurry of 1.2mm is as phosphorus source.
Step C: deposit SiNx mask.
Adopt at silicon chip back side that PECVD deposit a layer thickness is 150nm, refractive index is the SiN of 2.0
xmask, as mask layer during diffusion, preventing the Na+ ion in diffusion furnace from entering into silicon chip affects N-type silicon chip characteristic.
Step D: High temperature diffusion forms n+ and p+ doped layer.
Silicon chip is placed in diffusion furnace, spread 70 minutes under temperature 800 DEG C of environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in N-type silicon chip, form n+ and p+ doped layer respectively, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 50ohm/, p+ doped layer is 70ohm/.
Step e: remove phosphorosilicate glass, Pyrex and SiN
xmask.
The silicon chip spread is immersed in HF concentration is 10%, HCL concentration is react in the mixed solution of 20%, makes itself and silicon chip back side phosphorosilicate glass PSG, Pyrex BSG and SiN
xmask simultaneous reactions, generates the complex compound hexafluorosilicic acid of solubility, more repeatedly rinses well with deionized water.
Step F: deposit individual layer anti-reflection layer.
PSG, BSG and SiN is removed by step e
xfront side of silicon wafer upwards put into PECVD device reative cell;
Pass into silane and ammonia NH
3, be 80nm at N-type silicon chip front deposition thickness, refractive index is the SiN of 2.1
xfilm, as anti-reflection layer.
Step G: deposit overlayer passivation layer.
SiN has been grown by step F
xthe front Coating glue protect of anti-reflection layer, and the back side is upwards placed in PECVD device reative cell;
Pass into Al (CH
3)
3and H
2o, at n+ and the p+ doped layer back side, deposition thickness is 35nm, and refractive index is the Al of 1.5
2o
3film.
Pass into silane and ammonia NH again
3, at Al
2o
3on film, deposition thickness is 100nm, and refractive index is the Si of 2.0
3n
4film, thus Al is formed on n+ and p+ doped layer
2o
3/ Si
3n
4stack membrane is as passivation layer.
Step H: photoetching passivation layer forms contact pattern.
Carrying out width at the passivation layer back side is 60 μm, and the degree of depth is the laser ablation of 120nm, forms the groove of electrode contact figure, to remove passivation layer and not damage the silicon chip surface of doped layer.
Step I: screen printing electrode, completes battery and makes.
The aluminium paste being 3 μm in the silicon chip back side thickness of step H carries out silk screen printing, form electrode pattern and cover the groove formed in step H, carry out high temperature sintering at 750 DEG C again, to form width be the negative electrode of 80 μm and width is the positive electrode of 1mm, completes the making of N-type IBC battery.
Claims (9)
1. a N-type IBC battery, comprise anti-reflection layer, silicon chip matrix, doped layer, passivation layer and metal electrode, it is characterized in that: anti-reflection layer is located at the front of silicon chip matrix, silicon doping layer comprises n+ heavily doped layer and p+ heavily doped layer, this n+ heavily doped layer back side of being located at silicon chip matrix parallel with p+ heavily doped layer, passivation layer is located at above n+ heavily doped layer and p+ heavily doped layer; N+ heavily doped layer, p+ heavily doped layer are drawn metal electrode to the passivation layer back side.
2. N-type IBC battery according to claim 1, is characterized in that, anti-reflection layer adopts SiN
xfilm or SiO
2/ Si
3n
4stack membrane.
3. N-type IBC battery according to claim 1, is characterized in that, passivation layer adopts SiN
xfilm or SiO
2/ Si
3n
4or Al
2o
3/ Si
3n
4stack membrane.
4. a preparation method for N-type IBC battery structure, it comprises the steps:
(1) the two-sided making herbs into wool of N-type silicon chip: N-type silicon chip is placed in NaOH solution reaction 20 ~ 30min that mass fraction is 1% ~ 3%, carries out two-sided making herbs into wool and to silicon polished backside;
(2) in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
(3) silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index be 1.8 ~ 2.5 SiNx mask;
(4) silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
(5) employing concentration is the HF solution of 10% ~ 15%, removes phosphorosilicate glass PSG, Pyrex BSG and backside mask;
(6) adopt PECVD method to be 50nm ~ 200nm at doped layer back side deposition thickness, refractive index is the SiN of 2.0 ~ 2.3
xfilm is as passivation layer;
(7) adopt PECVD to be 60nm ~ 100nm at front side of silicon wafer deposit thickness, refractive index is the SiN of 1.8 ~ 2.3
xfilm is as antireflective film;
(8) form electrode contact figure in passivation layer backside laser etching, its laser ablation width is 30 μm ~ 80 μm, and etching depth is 50nm ~ 200nm, to remove passivation layer and not damage the silicon chip surface of doped layer;
(9) at the silicon chip back side depositing metal Ag/Al layer forming electrode contact figure, make electrode, complete the making of N-type IBC battery.
5. according to Preparation Method described in claim 4, wherein depositing metal Ag/Al layer in step (9), first with the Ag layer that Atomic layer deposition method ALD deposit thickness is 50nm ~ 100nm, deposit thickness is the Al layer of 2 μm ~ 5 μm again, finally carry out lithography stripping, to form width be the negative electrode of 40 μm ~ 80 μm and width is the positive electrode of 40 μm ~ 1mm.
6. a preparation method for N-type IBC battery structure, it comprises the steps:
1) the two-sided making herbs into wool of N-type silicon chip: N-type silicon chip is placed in KOH solution reaction 20 ~ 30min that mass fraction is 1% ~ 3%, carries out two-sided making herbs into wool and to silicon polished backside;
2) in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
3) silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index is the SiN of 1.8 ~ 2.5
xmask;
4) silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
5) adopt the mixed solution of HF and HCL, remove backside mask and phosphorosilicate glass PSG, Pyrex BSG, wherein HF concentration is 3%-15%, HCL concentration is 5%-30%;
6) PECVD is adopted to deposit SiO at front side of silicon wafer
2/ Si
3n
4stack membrane as anti-reflection layer, wherein SiO
2film thickness is 10nm ~ 30nm, and refractive index is 1.4 ~ 1.7, Si
3n
4the thickness of film is 50nm ~ 70nm, and refractive index is 1.8 ~ 2.2;
7) adopt PECVD method at doped layer back side deposit SiO
2/ Si
3n
4stack membrane as passivation layer, wherein SiO
2film thickness is 15nm ~ 50nm, and refractive index is 1.4 ~ 1.7, Si
3n
4the thickness of film is 30nm ~ 150nm, and refractive index is 1.8 ~ 2.2;
8) carrying out width at the passivation layer back side is 30 μm ~ 80 μm, and the degree of depth is the laser ablation of 45nm ~ 200nm, forms electrode contact figure, to remove passivation layer and not damage the silicon chip surface of doped layer;
9) carry out silk screen printing at the silicon chip back side silver slurry forming electrode contact figure and form electrode pattern, then carry out high temperature sintering formation silver electrode, complete the making of N-type IBC battery.
7. according to a kind of described in claim 6 preparation method of N-type IBC battery structure, wherein step 9) silk screen printing silver slurry thickness be 50nm ~ 100nm, carry out high temperature sintering at 750 DEG C ~ 850 DEG C again, to form width be the negative electrode of 40 μm ~ 80 μm and width is the positive electrode of 40 μm ~ 1mm.
8. a preparation method for N-type IBC battery structure, it comprises the steps:
The first step: N-type silicon chip is placed in mass fraction be 1% ~ 3% NaOH solution react 20-30min, carry out two-sided making herbs into wool and to silicon polished backside;
Second step: in silicon chip back side silk screen printing boron source and phosphorus source, boron source printing width is 50 μm ~ 1.5mm, phosphorus source printing width is 30 μm ~ 1.5mm;
3rd step: silicon chip back side deposit a layer thickness be 75nm ~ 200nm, refractive index is the SiN of 1.8 ~ 2.5
xmask;
4th step: silicon chip is placed in diffusion furnace, spread 40 minutes ~ 90 minutes under temperature 800 DEG C ~ 1000 DEG C environment, the boron source and the phosphorus source that make to be printed on silicon chip back side are spread in silicon, form n+ and p+ doped layer, wherein the diffusion square resistance of n+ doped layer is the diffusion square resistance of 15 ~ 60ohm/, p+ doped layer is 20 ~ 80ohm/;
5th step: the mixed solution adopting HF and HCL, remove Pyrex BSG, phosphorosilicate glass PSG and backside mask, wherein the concentration of HF is the concentration of 3%-15%, HCL is 5%-30%;
6th step: adopt PECVD to be 60nm ~ 100nm at front side of silicon wafer deposit thickness, refractive index is 1.8 ~ 2.3; SiN
xfilm is as anti-reflection layer;
7th step: adopt PECVD method at doped layer back side deposit Al
2o
3/ Si
3n
4stack membrane as passivation layer, wherein Al
2o
3the thickness of film is 15nm ~ 50nm, and refractive index is 1.3 ~ 1.6, Si
3n
4the thickness of film is 30nm ~ 150nm, and refractive index is 1.8 ~ 2.2;
8th step: form electrode contact figure in passivation layer backside laser etching, wherein laser ablation width is 30 μm ~ 80 μm, and etching depth is 45nm ~ 200nm, to remove passivation layer and not damage the silicon chip surface of doped layer;
9th step: carry out silk screen printing at the silicon chip back side aluminium paste forming electrode contact figure and form electrode pattern, then carry out high temperature sintering formation aluminium electrode, complete the making of N-type IBC battery.
9. according to Claim 8 described in a kind of preparation method of N-type IBC battery structure, wherein in step the nine step, silk screen printing aluminium paste thickness is 1 μm ~ 4 μm, carry out high temperature sintering at 750 DEG C ~ 850 DEG C again, to form width be the negative electrode electrodes of 40 μm ~ 80 μm and width is the positive electrode of 40 μm ~ 1mm.
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| CN110676160A (en) * | 2019-10-10 | 2020-01-10 | 浙江晶科能源有限公司 | Solar cell and manufacturing method thereof |
| CN113284982A (en) * | 2021-05-28 | 2021-08-20 | 浙江爱旭太阳能科技有限公司 | Processing technology of IBC battery with passivation contact structure |
| CN115117181A (en) * | 2021-03-22 | 2022-09-27 | 黄河水电西宁太阳能电力有限公司 | Manufacturing method of low-cost single-side passivated contact IBC battery |
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| CN115117181A (en) * | 2021-03-22 | 2022-09-27 | 黄河水电西宁太阳能电力有限公司 | Manufacturing method of low-cost single-side passivated contact IBC battery |
| CN113284982A (en) * | 2021-05-28 | 2021-08-20 | 浙江爱旭太阳能科技有限公司 | Processing technology of IBC battery with passivation contact structure |
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Application publication date: 20160511 |