CN105551962A - 次常压无掺杂硅玻璃成膜方法 - Google Patents

次常压无掺杂硅玻璃成膜方法 Download PDF

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CN105551962A
CN105551962A CN201510971895.8A CN201510971895A CN105551962A CN 105551962 A CN105551962 A CN 105551962A CN 201510971895 A CN201510971895 A CN 201510971895A CN 105551962 A CN105551962 A CN 105551962A
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pressure
reaction chamber
glass film
method under
film forming
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CN105551962B (zh
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严玮
刘立成
周俊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator

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Abstract

本发明公开了一种次常压无掺杂硅玻璃成膜方法，通过渐进式压力管控，成膜时反应腔内压力达到600Torr，同时控制反应气体流量以防止气流扰动产生颗粒问题。形成的氧化膜具有良好的保形性，颗粒好，膜厚可控，适合量产。

Description

次常压无掺杂硅玻璃成膜方法
技术领域
本发明涉及半导体集成电路制造领域，特别涉及一种次常压(SAT)无掺杂硅玻璃成膜方法。
背景技术
功率MOS器件的沟槽衬垫层是一层用于隔离硅衬底和多晶硅的氧化膜,该氧化膜需要覆盖在一种深宽比很大(5:1)的沟槽上，后续多晶硅再填入。要求该衬垫氧化膜有完美的台阶覆盖能力，保形性好，较好的面内均匀性，无等离子损伤,满足这个要求的机台有LPCVD(TEOS)(LPCVD(：低压化学气相淀积)(TEOS：正硅酸乙酯)和SATTEOS，而它们都有各自一个缺点：无法适应量产。如下表所示：
采用SAT400℃或者LPCVD工艺都会使衬垫氧化膜产生悬突，如图1所示，所谓的悬突是指：图中硅衬底上的沟槽口沿是形状非常好的直角，而淀积衬垫氧化膜之后，其口沿处的保形性就变得比较差，如图1圆圈处所示，具有比较圆滑的弧度形成倒角。而采用SAT550℃虽然无悬突，但该工艺颗粒系统性不好，颗粒都在2000个，无法解决，如图2所示。
发明内容
本发明所要解决的技术问题是提供一种次常压无掺杂硅玻璃成膜方法，其具有高保形性，台阶覆盖性能好。
为解决上述问题，本发明所述的次常压无掺杂硅玻璃成膜方法通过渐进式压力管控，成膜时压力达到600Torr。
所述的渐进式压力管控，是反应腔在氧气和氦气氛围，400℃条件下，分步进行：
第一步，控制节流阀处于半开启状态；第二步，当反应腔压力上升达到200Torr时，本步骤停止；第三步，当反应腔压力上升达到400Torr时，本步骤停止；第四步，当反应腔压力上升达到500Torr时，本步骤停止；第五步，控制反应腔压力继续上升，在20S时间内上升达到600Torr时停止。
本发明所述的次常压无掺杂硅玻璃成膜方法，对TEOS采用渐进式压力控制，压力上升至非常高的600Torr。形成的氧化膜具有良好的保形性，颗粒好，膜厚可控，适合量产。
附图说明
图1是传统次常压工艺400℃成膜的剖面图。
图2是传统次常压工艺550℃成膜的剖面图。
图3～4是采用本发明工艺成膜的剖面图。
具体实施方式
本发明所述的次常压无掺杂硅玻璃成膜方法采用400℃反应腔室的温度，氧气和氦气氛围，通过渐进式压力管控，成膜前有4个步骤形成压力缓变，成膜时TEOS压力达到600Torr，接近大气压。同时防止气流扰动产生颗粒问题。
所述的渐进式压力管控，是反应腔在氧气和氦气氛围，400℃条件下，分步进行：
第一步，控制TEOS节流阀处于半开启状态；第二步，当反应腔压力缓慢上升达到200Torr时，本步骤停止；第三步，当反应腔压力缓慢上升达到400Torr时，本步骤停止；第四步，当反应腔压力缓慢上升达到500Torr时，本步骤停止；第五步，控制反应腔压力继续上升，在20S时间内缓慢上升达到600Torr时停止。
如果少于上述步骤，压力控制阀无法控制TEOS到压力600Torr。
采用上述工艺方法的关键在于两点：
1.采用渐进式压力控制，压力上升至非常高的600Torr；
2.TEOS的流量对氧化膜的疏松度和台阶覆盖性都有影响，而且是矛盾的。TEOS流量太大会产生台阶覆盖和颗粒的问题，而TEOS的流量过小又会导致膜质疏松，需要选用合适的值。一组典型的参数如下表所示：
通过上述工艺，生成的氧化膜台阶覆盖，侧墙能达到99％，底部能达到95％。如图3及图4所示，是采用本发明工艺后的剖面显微图，可以看到，图中形成的膜层紧紧贴附于沟槽上，无悬突，具有非常好的保形性。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种次常压下无掺杂硅玻璃成膜方法，其特征是，通过渐进式压力管控，成膜时压力达到600Torr。
2.如权利要求1所述的次常压下无掺杂硅玻璃成膜方法，其特征是，所述的渐进式压力管控，是反应腔在氧气和氦气氛围，400℃条件下，分步进行。
3.如权利要求2所述的次常压下无掺杂硅玻璃成膜方法，其特征是，第一步，控制节流阀处于半开启状态；第二步，当反应腔压力上升达到200Torr时，本步骤停止；第三步，当反应腔压力上升达到400Torr时，本步骤停止；第四步，当反应腔压力上升达到500Torr时，本步骤停止；第五步，控制反应腔压力继续上升，在20S时间内达到600Torr时停止。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217658B1 (en) * 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
CN101872739A (zh) * 2009-04-23 2010-10-27 上海华虹Nec电子有限公司 沟槽的填充方法
CN103579076A (zh) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 形成浅沟槽隔离区的方法
CN104157600A (zh) * 2014-08-15 2014-11-19 上海华力微电子有限公司 浅沟槽结构的制备方法
CN104795351A (zh) * 2014-01-20 2015-07-22 中芯国际集成电路制造(上海)有限公司 隔离结构的形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217658B1 (en) * 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
CN101872739A (zh) * 2009-04-23 2010-10-27 上海华虹Nec电子有限公司 沟槽的填充方法
CN103579076A (zh) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 形成浅沟槽隔离区的方法
CN104795351A (zh) * 2014-01-20 2015-07-22 中芯国际集成电路制造(上海)有限公司 隔离结构的形成方法
CN104157600A (zh) * 2014-08-15 2014-11-19 上海华力微电子有限公司 浅沟槽结构的制备方法

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