CN105551523B - Nand memory and its device for balancing the WL Voltage Establishment time - Google Patents
Nand memory and its device for balancing the WL Voltage Establishment time Download PDFInfo
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- CN105551523B CN105551523B CN201510919134.8A CN201510919134A CN105551523B CN 105551523 B CN105551523 B CN 105551523B CN 201510919134 A CN201510919134 A CN 201510919134A CN 105551523 B CN105551523 B CN 105551523B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The present invention provides a kind of nand memory and its devices of balance WL Voltage Establishment time, and device includes: balanced signal receiving module, receiving balance signal；First balance cock module is connected with the global control switch module of the first plane operation signal receiving end, balanced signal receiving module and first respectively；Second balance cock module is connected with the global control switch module of the 2nd plane operation signal receiving end, balanced signal receiving module and second respectively；When carrying out individually operated to the first plane or the 2nd plane, balanced signal controls the first and second balance cock modules and opens simultaneously；When operating to the first plane and the 2nd plane, the first plane operation signal controls the first balance cock module and opens, while the 2nd plane operation signal controls the second balance cock module and opens.The invention enables the WL Voltage Establishment times to be consistent in single double plane operations.
Description
Technical field
The present invention relates to memory technology fields, more particularly to a kind of device and one kind for balancing the WL Voltage Establishment time
Nand memory.
Background technique
When NAND (computer flash memory device) memory to double plane (storage matrix) structure operates, sometimes
It is double plane operation modes, i.e., two plane is operated simultaneously, sometimes list plane operation mode, i.e., only to two
A plane in plane carries out individually operated.
Traditional nand memory is as shown in Figure 1, under above two operation mode, needed for the charge pump of nand memory
The capacitor to be driven is not identical.Such as in double plane operation modes, to PLN0 ' and PLN1 ' it operates simultaneously, charge pump
It needs to drive capacitor CCGA’, capacitor CCG0’, capacitor CCG1’, capacitor CWL0’With capacitor CWL1’, at this point, key signal in nand memory
Schematic diagram is as shown in Figure 2.PLN0 ' or PLN1 ' is individually operated in single plane operation mode, charge pump is corresponding only to be needed
Drive capacitor CCGA’, capacitor CCG0’With capacitor CWL0’Or capacitor CCGA’, capacitor CCG1’With capacitor CWL1’, wherein to PLN1 ' individually into
When row operation, key signal schematic diagram is as shown in Figure 3 in nand memory.
Since under above two different operation mode, as shown in Figures 2 and 3, the driving capability of charge pump is the same, lead
Cause the recovery time t21' and t31' of the output signal PUMP ' of charge pump not identical, WL1 ' Voltage Establishment time t22' and t32'
Also not identical.
Summary of the invention
In view of the above problems, the embodiment of the present invention be designed to provide it is a kind of balance the WL Voltage Establishment time device and
A kind of corresponding nand memory, to solve traditional nand memory in different modes of operation, when establishing of WL voltage
Between different problem.
To solve the above-mentioned problems, the embodiment of the invention discloses a kind of devices for balancing the WL Voltage Establishment time, comprising:
Balanced signal receiving module, the balanced signal receiving module receiving balance signal；First balance cock module, described first is flat
Weigh switch module respectively in nand memory the first plane operation signal receiving end, the balanced signal receiving module and
The first global control switch module in nand memory is connected；Second balance cock module, the second balance cock module
Respectively with the 2nd plane operation signal receiving end, the balanced signal receiving module and the nand memory in nand memory
In the second global control switch module be connected；Wherein, when in nand memory the first plane or the 2nd plane it is independent
When being operated, the balanced signal controls the first balance cock module and the second balance cock module is beaten simultaneously
It opens；When being operated simultaneously to the first plane and the 2nd plane, the first plane operation signal receiving end
Received first plane operation signal controls the first balance cock module and opens, while the 2nd plane operation signal
The received 2nd plane operation signal in receiving end controls the second balance cock module and opens.
Specifically, the balanced signal receiving module includes the balanced signal receiving end for receiving the balanced signal, wherein
When individually operating to 2nd plane of the first plane or described, the balanced signal receiving end is received described flat
Weighing apparatus signal is high level；When operating simultaneously to the first plane and the 2nd plane, the balanced signal is connect
The received balanced signal of receiving end is low level.
Specifically, the first balance cock module includes: first or door, described first or door first input end and
Two input terminals are connected with the first plane operation signal receiving end and the balanced signal receiving end respectively, described first or
The output end of door is connected with the described first global control switch module.
Specifically, the second balance cock module includes: second or door, described second or door first input end and
Two input terminals are connected with the 2nd plane operation signal receiving end and the balanced signal receiving end respectively, described second or
The output end of door is connected with the described second global control switch module.
Specifically, described first or door and described second or Men Xiangtong.
To solve the above-mentioned problems, the embodiment of the invention also discloses a kind of nand memories, comprising: the first plane and
2nd plane；First plane operation signal receiving end and the 2nd plane operation signal receiving end；First global control switch mould
Block and the second global control switch module；The device of the described balance WL Voltage Establishment time, when the balance WL Voltage Establishment
Between device respectively with the first plane operation signal receiving end, the 2nd plane operation signal receiving end, described
One global control switch module is connected with the described second global control switch module.
The nand memory of the embodiment of the present invention and its device for balancing the WL Voltage Establishment time include following advantages: being passed through
Balanced signal receiving module receiving balance signal, and setting the first balance cock module respectively with first in nand memory
Plane operation signal receiving end, balanced signal receiving module are connected with the first global control switch module in nand memory,
Second balance cock module respectively with the 2nd plane operation signal receiving end in nand memory, balanced signal receiving module
It is connected with the second global control switch module in nand memory.And when to the first plane or second in nand memory
Plane individually operated i.e. single plane operation mode constantly, balanced signal controls the first balance cock module and second flat
Weighing apparatus switch module opens simultaneously, and operates mould in double plane when being operated simultaneously to the first plane and the 2nd plane
When formula, the received first plane operation signal in the first plane operation signal receiving end controls the first balance cock module and opens,
The received 2nd plane operation signal in the 2nd plane operation signal receiving end controls the second balance cock module and opens simultaneously.From
And make the capacitor base of the charge pump of nand memory required driving in single plane operation mode and double plane operation modes
This is identical, realizes that the WL Voltage Establishment time is consistent in single plane operation mode and double plane operation modes, extends
The service life of nand memory.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional nand memory；
Fig. 2 is key signal schematic diagram of traditional nand memory in double plane operation modes；
Fig. 3 is key signal schematic diagram of traditional nand memory when individually operating to PLN1 '；
Fig. 4 is a kind of structural block diagram of the Installation practice of balance WL Voltage Establishment time of the invention；
Fig. 5 is a kind of structural schematic diagram of the Installation practice of balance WL Voltage Establishment time of the invention；
Fig. 6 is the device that nand memory has the balance WL Voltage Establishment time shown in fig. 5, operates mould in double plane
Key signal schematic diagram when formula；
Fig. 7 is the device that nand memory has the balance WL Voltage Establishment time shown in fig. 5, operates mould in single plane1
Key signal schematic diagram when formula.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Referring to Fig. 4, a kind of structural block diagram of 1 embodiment of device of balance WL Voltage Establishment time of the invention is shown,
It can specifically include following module: balanced signal receiving module 10, the first balance cock module 20 and the second balance cock module
30.Wherein, 10 receiving balance signal EQUAL of balanced signal receiving module；First balance cock module 20 is stored with NAND respectively
The first global control in the first plane operation signal receiving end 2, balanced signal receiving module 10 and nand memory in device
Switch module g_sw0 is connected；Second balance cock module 30 is received with the 2nd plane operation signal in nand memory respectively
End 3, balanced signal receiving module 10 are connected with the second overall situation control switch module g_sw1 in nand memory；Wherein, when right
When the first plane PLN0 or the 2nd plane PLN1 in nand memory are individually operated, balanced signal EQUAL control
First balance cock module 20 and the second balance cock module 30 open simultaneously；When to the first plane PLN0 and the 2nd plane
When PLN1 is operated simultaneously, the received first plane operation signal PLNSEL0 control in the first plane operation signal receiving end 2
First balance cock module 20 is opened, while the received 2nd plane operation signal in the 2nd plane operation signal receiving end 3
PLNSEL1 controls the second balance cock module 30 and opens.
Specifically, in one embodiment of the invention, referring to Fig. 5, balanced signal receiving module 10 may include receiving
The balanced signal receiving end 11 of balanced signal EQUAL, wherein when to the first plane PLN0 or the 2nd plane PLN1 individually into
When row operation, the received balanced signal EQUAL in balanced signal receiving end 11 can be high level；When to the first plane PLN0 and
When 2nd plane PLN1 is operated simultaneously, the received balanced signal EQUAL in balanced signal receiving end 11 can be high level
Or low level.
Specifically, in one embodiment of the invention, the first balance cock module 20 may include first or door, and first
Or door first input end and the second input terminal respectively with the first plane operation signal receiving end 2 and balance signal receiving end 11
Be connected, first or the output end of door be connected with the first overall situation control switch module g_sw0.Second balance cock module 30 can wrap
Include second or door, second or door first input end and the second input terminal respectively with 3 peace of the 2nd plane operation signal receiving end
The signal receiving end 11 that weighs is connected, second or the output end of door be connected with the second overall situation control switch module g_sw1.Wherein, first
Or door and second or door can be identical.
Therefore, when balanced signal EQUAL is high level and/or the first plane operation signal PLNSEL0 is high level,
First or door export high level, the first overall situation control switch module g_sw0 opening；When balanced signal EQUAL be high level and/or
When 2nd plane operation signal PLNSEL1 is high level, second or door export high level, the second global control switch module g_
Sw1 is opened.
It should be noted that in another embodiment of the present invention, the first balance cock module 20 may include can be with
Realize the other modules or circuit of first or door function, the second balance cock module 30 may include that second or Men Gong may be implemented
The other modules or circuit of energy, which is not limited by the present invention.
In embodiments of the present invention, the device 1 for balancing the WL Voltage Establishment time is applied to nand memory, referring to Fig. 5,
It includes device 1, the first plane PLN0, the 2nd plane PLN1, first for balancing the WL Voltage Establishment time that nand memory, which removes,
Plane operation signal receiving end 2, the 2nd plane operation signal receiving end 3, the global control switch module g_ of charge pump 4, first
It can also include parasitic capacitance C outside the global control switch module g_sw1 of sw0 and secondCGA, parasitic capacitance CCG0, parasitic capacitance
CCG1, parasitic capacitance CWL0With parasitic capacitance CWL1, overall situation WL decoder cgdec, the first row address decoder BLKDEC0, the first WL
Driving switch WL_drv0, the second row address decoder BLKDEC1, the 2nd WL driving switch WL_drv1.Wherein, the first plane
PLN0 and the 2nd plane PLN1 are identical, the global control switch module g_sw1 of the first overall situation control switch module g_sw0 and second
Identical, the first row address decoder BLKDEC0 and the second row address decoder BLKDEC1 are identical, the first WL driving switch WL_
Drv0 and the 2nd WL driving switch WL_drv1 are identical.In Fig. 5, RA0 is the line of input of the first row address decoder BLKDEC0
Location, RA1 are the input row address of the second row address decoder BLKDEC1.
Specifically, in double plane operation modes, the first plane operation signal PLNSEL0 and the 2nd plane operation letter
Number PLNSEL1 is high level simultaneously, and balanced signal EQUAL is high level or low level, the first balance cock module 20 and second
Balance cock module 30 opens simultaneously, and the global control switch module g_sw1 of the first overall situation control switch module g_sw0 and second is same
When open, the first row address decoder BLKDEC0 and the second row address decoder BLKDEC1 are opened simultaneously, the first WL driving open
It closes WL_drv0 and the 2nd WL driving switch WL_drv1 to open simultaneously, charge pump 4 drives all capacitors in nand memory (parasitic
Capacitor CCGA, parasitic capacitance CCG0, parasitic capacitance CCG1, parasitic capacitance CWL0With parasitic capacitance CWL1)。
In single plane0 operation mode, the first plane operation signal PLNSEL0 and balanced signal EQUAL are high simultaneously
Level, the first balance cock module 20 and the second balance cock module 30 open simultaneously, the first global control switch module g_sw0
It is opened simultaneously with the second overall situation control switch module g_sw1, the first row address decoder BLKDEC0 is opened, and the second row address is translated
Code device BLKDEC1 is closed, and the first WL driving switch WL_drv0 is opened, and the 2nd WL driving switch WL_drv1 is closed, only to first
Plane PLN0 is operated, and cannot be operated to the 2nd plane PLN1, and charge pump 4 drives parasitic electricity in nand memory
Hold CCGA, parasitic capacitance CCG0, parasitic capacitance CCG1, parasitic capacitance CWL0。
In single plane1 operation mode, the 2nd plane operation signal PLNSEL1 and balanced signal EQUAL are high simultaneously
Level, the first balance cock module 20 and the second balance cock module 30 open simultaneously, the first global control switch module g_sw0
It is opened simultaneously with the second overall situation control switch module g_sw1, the first row address decoder BLKDEC0 is closed, and the second row address is translated
Code device BLKDEC1 is opened, and the first WL driving switch WL_drv0 is closed, and the 2nd WL driving switch WL_drv1 is opened, only to second
Plane PLN1 is operated, and cannot be operated to the first plane PLN0, and charge pump 4 drives parasitic electricity in nand memory
Hold CCGA, parasitic capacitance CCG0, parasitic capacitance CCG1, parasitic capacitance CWL1。
Since compared with double plane operation modes, in single plane0 operation mode, the capacitor that charge pump 4 need to drive is only
Parasitic capacitance C is lackedWL1, and parasitic capacitance CWL1All capacitors are small part in opposite nand memory, therefore, electricity
The electricity of the output voltage signal WL0 of the recovery time and the first WL driving switch WL_drv0 of the driving signal PUMP of 4 output of lotus pump
Press settling time almost the same under two kinds of operation modes.Similarly, due to compared with double plane operation modes, in single plane1
When operation mode, the capacitor that charge pump 4 need to drive only has lacked parasitic capacitance CWL0, and parasitic capacitance CWL0In opposite nand memory
All capacitors are small part, therefore, the recovery time for the driving signal PUMP that charge pump 4 exports and the 2nd WL driving
The Voltage Establishment time of the output voltage signal WL1 of switch WL_drv1 is almost the same under two kinds of operation modes.That is WL voltage is built
It is almost the same when single plane is operated with double plane operations between immediately, so as to extend the service life of nand memory.
Wherein, when nand memory shown in fig. 5 is in double plane operation modes, key signal shows in nand memory
It is intended to as shown in fig. 6, when nand memory shown in fig. 5 is in single plane1 operation mode, key signal in nand memory
Schematic diagram is as shown in Figure 7.Wherein, CGSEL is the control signal of overall situation WL decoder cgdec, and CGA is overall situation WL decoder
The output signal of cgdec, CG0 are the output signal of the first global control switch module g_sw0, and CG1 is that the second global control is opened
Close the output signal of module g_sw1.
From Fig. 6 and Fig. 7 it can be found that nand memory shown in fig. 5, in double plane operation, what charge pump 4 exported
When the Voltage Establishment of the output voltage signal WL1 of the recovery time t61 of driving signal PUMP and the 2nd WL driving switch WL_drv1
Between t62, with single plane1 operate when, charge pump 4 export driving signal PUMP recovery time t71 and the 2nd WL driving open
The Voltage Establishment time t72 for closing the output voltage signal WL1 of WL_drv1 is consistent substantially.
The device of the balance WL Voltage Establishment time of the embodiment of the present invention includes following advantages: receiving mould by balanced signal
Block receiving balance signal, and setting the first balance cock module respectively with the first plane operation signal in nand memory
Receiving end, balanced signal receiving module are connected with the first global control switch module in nand memory, the second balance cock
Module respectively with the 2nd plane operation signal receiving end, balanced signal receiving module and the nand memory in nand memory
In the second global control switch module be connected.And works as and the first plane or the 2nd plane in nand memory are individually grasped
Make i.e. in single plane operation mode, balanced signal controls the first balance cock module and the second balance cock module is beaten simultaneously
It opens, and when being operated i.e. in double plane operation modes simultaneously to the first plane and the 2nd plane, the first plane is grasped
Make the received first plane operation signal of signal receiving end and control the first balance cock module opening, while the 2nd plane is operated
The received 2nd plane operation signal of signal receiving end controls the second balance cock module and opens.So that nand memory
Charge pump required driving in single plane operation mode and double plane operation mode capacitor it is essentially identical, realize WL voltage
Settling time is consistent in single plane operation mode and double plane operation modes, and extend nand memory uses the longevity
Life.
The embodiment of the present invention also proposed a kind of nand memory, comprising: the first plane PLN0, the 2nd plane
PLN1, the first plane operation signal receiving end 2, the 2nd the 3, first global control switch module g_ of plane operation signal receiving end
The device 1 of sw0, the second overall situation control switch module g_sw1 and above-mentioned balance WL Voltage Establishment time.Wherein, balance WL electricity
Press settling time device 1 respectively with the first plane operation signal receiving end 2, the 2nd plane operation signal receiving end 3, first
The overall situation control switch module g_sw1 of global control switch module g_sw0 and second is connected.
The nand memory of the embodiment of the present invention includes following advantages: the device by increasing the balance WL Voltage Establishment time
Carry out the capacitor base so that charge pump required driving in single plane operation mode and double plane operation modes of nand memory
This is identical, realizes that the WL Voltage Establishment time is consistent in single plane operation mode and double plane operation modes, NAND is deposited
The service life is longer for reservoir.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases
This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
Above to a kind of device and a kind of nand memory for balancing the WL Voltage Establishment time provided by the present invention, carry out
It is discussed in detail, used herein a specific example illustrates the principle and implementation of the invention, above embodiments
Explanation be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art,
According to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion in this specification
Appearance should not be construed as limiting the invention.
Claims (6)
1. a kind of device for balancing the WL Voltage Establishment time characterized by comprising
Balanced signal receiving module, the balanced signal receiving module receiving balance signal；
First balance cock module, the first balance cock module is operated with the first plane in nand memory respectively to be believed
Number receiving end, the balanced signal receiving module are connected with the first global control switch module in nand memory, and described the
One plane operation signal receiving end is also connect with the first row address decoder BLKDEC0 in nand memory, the first row address
Decoder BLKDEC0 is also connected with the first WL driving switch WL_drv0, the first WL driving switch WL_ in nand memory
Drv0 is also connect with the overall situation of the first plane PLN0 and first control switch module g_sw0 respectively；
Second balance cock module, the second balance cock module is operated with the 2nd plane in nand memory respectively to be believed
Number receiving end, the balanced signal receiving module are connected with the second global control switch module in nand memory, and described the
Two plane operation signal receiving ends are also connect with the second row address decoder BLKDEC1 in nand memory, the second row address
Decoder BLKDEC1 is also connected with the 2nd WL driving switch WL_drv1, the 2nd WL driving switch WL_ in nand memory
Drv1 is also connect with the overall situation of the 2nd plane PLN1 and second control switch module g_sw1 respectively；
Wherein, when in nand memory the first plane or the 2nd plane individually operate when, the balanced signal control
It makes the first balance cock module and the second balance cock module opens simultaneously, in single plane0 operation mode, the
The overall situation of one overall situation control switch module g_sw0 and second control switch module g_sw1 is opened simultaneously, the first row address decoder
BLKDEC0 is opened, and the second row address decoder BLKDEC1 is closed, and the first WL driving switch WL_drv0 is opened, the 2nd WL driving
Switch WL_drv1 is closed；
In single plane1 operation mode, the global control switch module g_sw1 of the first overall situation control switch module g_sw0 and second
It opens simultaneously, the first row address decoder BLKDEC0 is closed, and the second row address decoder BLKDEC1 is opened, and the first WL driving is opened
It closes WL_drv0 to close, the 2nd WL driving switch WL_drv1 is opened；When to the first plane and the 2nd plane simultaneously
When being operated, the received first plane operation signal control in the first plane operation signal receiving end first balance
Switch module is opened, while the received 2nd plane operation signal in the 2nd plane operation signal receiving end control described the
Two balance cock modules are opened, and the overall situation of the first overall situation control switch module g_sw0 and second control switch module g_sw1 is beaten simultaneously
It opens, the first row address decoder BLKDEC0 and the second row address decoder BLKDEC1 are opened simultaneously, the first WL driving switch WL_
Drv0 and the 2nd WL driving switch WL_drv1 are opened simultaneously.
2. the apparatus according to claim 1, which is characterized in that the balanced signal receiving module includes receiving the balance
The balanced signal receiving end of signal, wherein
When individually being operated to 2nd plane of the first plane or described, the received institute in balanced signal receiving end
Stating balanced signal is high level；
When being operated simultaneously to the first plane and the 2nd plane, the received institute in balanced signal receiving end
Stating balanced signal is low level.
3. the apparatus of claim 2, which is characterized in that the first balance cock module includes:
First or door, described first or door first input end and the second input terminal respectively with the first plane operation signal
Receiving end is connected with the balanced signal receiving end, described first or door output end and the first global control switch module
It is connected.
4. device according to claim 3, which is characterized in that the second balance cock module includes:
Second or door, described second or door first input end and the second input terminal respectively with the 2nd plane operation signal
Receiving end is connected with the balanced signal receiving end, described second or door output end and the second global control switch module
It is connected.
5. device according to claim 4, which is characterized in that described first or door and described second or Men Xiangtong.
6. a kind of nand memory characterized by comprising
First plane and the 2nd plane；
First plane operation signal receiving end and the 2nd plane operation signal receiving end；
First global control switch module and the second global control switch module；
The device of balance WL Voltage Establishment time according to any one of claims 1-5, the balance WL Voltage Establishment
The device of time respectively with the first plane operation signal receiving end, the 2nd plane operation signal receiving end, described
First global control switch module is connected with the described second global control switch module.
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| JP2007188612A (en) * | 2006-01-16 | 2007-07-26 | Renesas Technology Corp | Nonvolatile storage device |
| CN101989457B (en) * | 2009-08-04 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Nonrolatile storage system capable of reducing filter capacitor |
| CN102237788B (en) * | 2010-04-29 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit and memory |
| US8325534B2 (en) * | 2010-12-28 | 2012-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Concurrent operation of plural flash memories |
| CN102956267B (en) * | 2011-08-30 | 2016-04-27 | 旺宏电子股份有限公司 | Memory programming method and apply its flash memory device |
| WO2014033851A1 (en) * | 2012-08-29 | 2014-03-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| KR20140093855A (en) * | 2013-01-18 | 2014-07-29 | 삼성전자주식회사 | Memory system comprising nonvolatile memory device and control method thereof |
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