CN102956267B - Memory programming method and apply its flash memory device - Google Patents
Memory programming method and apply its flash memory device Download PDFInfo
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- CN102956267B CN102956267B CN201110254197.8A CN201110254197A CN102956267B CN 102956267 B CN102956267 B CN 102956267B CN 201110254197 A CN201110254197 A CN 201110254197A CN 102956267 B CN102956267 B CN 102956267B
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Abstract
The invention discloses a kind of memory programming method and apply its flash memory device.Wherein, memory programming method, is applied to the flash memory comprising first and second storer aspect (Plane), comprises the following steps: to receive the programming instruction comprising programmed logic address; Set up the first logic to entity (Logic-to-Physical, the L2P) table of comparisons and programmed logic address corresponded to main storage space in first memory aspect; Do you judge that flash memory operates in extract operation (Random? Access) pattern; If so, set up the 2nd L2P table of comparisons and programmed logic address is corresponded to back up memory space in second memory aspect; Programming data is write simultaneously the back up memory space of main storage space and second memory aspect; Then judge whether main storage space programmes successfully; If not, back up memory space is pointed in the address corresponding to main storage space.
Description
Technical field
The invention relates to a kind of memory programming method and apply its flash memory device, and relate to especially and a kind ofly carry out the memory programming method of error return for data programing mistake and apply its flash memory device.
Background technology
In the epoch now that development in science and technology is maked rapid progress, non-volatile memory device is widely used in multiple electronic product; For example, flash memory is one of the most widely used nonvolatile memory.In general, the storage unit in flash memory has programmable threshold voltage, and this programmable threshold voltage is in order to indicate the value data stored in this storage unit.
In the data program operation of flash memory, the situation of program fail can be there is contingently.Accordingly, such as error correcting code (ErrorCorrectionCode, ECC) need be performed, to carry out the reply operation of being correlated with.But in the misprogrammed that some are serious, still cannot reply the data of program fail even if perform ECC, and will data degradation be caused.Accordingly, how more perfect programmed method to be proposed, effectively to reply the data of program fail when program fail occurs, for industry constantly endeavours one of direction for flash memory.
Summary of the invention
The present invention has about a kind of memory programming method and the flash memory device applying it, its be applied to there is first and second storer aspect (MemoryPlane) flash memory in.The memory programming method that the present invention is correlated with and apply it flash memory device more in this flash disk operation when with extract operation (RandomAccess) pattern, then set up the first logic to entity (Logic-to-Physical, the L2P) table of comparisons programmed logic address of reception to be corresponded to main storage space in first memory aspect, set up the 2nd L2P table of comparisons and programmed logic address corresponded to the back up memory space in second memory aspect and programming data write according to this in this main storage space and this back up memory space simultaneously.When main storage space generation program fail, the memory programming method that the present invention is correlated with and apply its flash memory device can will correspond to main storage space address point to back up memory space, with this, bug patch is carried out to flash memory.Accordingly, compared to conventional flash memory, the memory programming method that the present invention is correlated with and apply its flash memory device accordingly can effectively to the advantage that the data of program fail are replied.
According to a first aspect of the invention, a kind of memory programming method is proposed, be applied to flash memory, wherein flash memory comprises first and second storer aspect (Plane), and memory programming method comprises the following steps: first to receive the programming instruction comprising programmed logic address; Then set up the first logic to entity (Logic-to-Physical, the L2P) table of comparisons and programmed logic address corresponded to main storage space in first memory aspect; Then judge whether flash memory operates in extract operation (RandomAccess) pattern; If so, set up the 2nd L2P table of comparisons and programmed logic address is corresponded to back up memory space in second memory aspect; Then first and second storer aspect is programmed the back up memory space programming data to be write main storage space and second memory aspect simultaneously; Then judge whether main storage space programmes successfully; If not, back up memory space is pointed in the address corresponding to main storage space.
According to a second aspect of the invention, propose a kind of flash memory device, carry out data program operation in response to programming instruction, programming instruction comprises programmed logic address.Flash memory device comprises flash memory, buffer and Memory Controller.Flash memory comprises first and second storer aspect.Buffer keeps in the programming data corresponding to programming instruction.Memory Controller sets up a L2P table of comparisons in response to programming instruction, programmed logic address to be corresponded to the main storage space of first memory aspect; Memory Controller more judges whether this flash memory operates in extract operation pattern; If so, then set up the 2nd L2P table of comparisons, programmed logic address is corresponded to the back up memory space of second memory aspect.Memory Controller is more programmed to first and second storer aspect simultaneously, so that programming data is write main storage space and back up memory space.Memory Controller more judges whether main storage space programmes successfully, if not, then back up memory space is pointed in the address corresponding to main storage space.
In order to have better understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating institute's accompanying drawings, being described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the calcspar of the flash memory device according to the embodiment of the present invention.
Fig. 2 illustrates according to logic to the operation chart of entity table of comparisons L2P_1.
Fig. 3 illustrates according to logic to the operation chart of entity table of comparisons L2P_2.
Fig. 4 illustrates the process flow diagram of the memory programming method according to the embodiment of the present invention.
Fig. 5 illustrates the part process flow diagram of the memory programming method according to the embodiment of the present invention.
[main element symbol description]
1: flash memory device
2: main frame
10: flash memory
20: buffer
30: Memory Controller
10_P1,10_P2: storer aspect
Page_M: primary storage paging
Page_T: back-up storage paging
B (L): logical storage block
P (L_N)-P (L_N+M): logical storage paging
B (P), B (P_X)-B (P_Z): physical memory blocks
P (P_N)-P (P_N+M): physical storage paging
Embodiment
Please refer to Fig. 1, it illustrates the calcspar of the flash memory device according to the embodiment of the present invention.The programming instruction CMD that the flash memory device 1 of the present embodiment provides in response to main frame 2 carries out data program operation, and programming instruction CMD comprises programmed logic address Addr_P.Flash memory device 1 comprises flash memory 10, buffer 20 and Memory Controller 30.The temporary programming data Data corresponding to programming instruction CMD of buffer 20.
Flash memory 10 comprises storer aspect (Plane) 10_P1 and 10_P2.For example, storer aspect 10_P1 comprises multiple memory block (Block), and each memory block comprises storage paging (Page); Storer aspect 10_P2 comprises back-up storage block.Furthermore, memory block is the operating unit of the clear operation (Erase) of Sheffer stroke gate (NAND) flash memory, and stores the operating unit of programming operation (Program) that paging is nand flash memory and read operation (Read).
Memory Controller 30 sets up logic to entity (Logic-to-Physical, L2P) table of comparisons L2P_1 in response to programming instruction CMD, programmed logic address Addr_P to be corresponded to the main storage space in storer aspect 10_P1.For example, L2P table of comparisons L2P_1 corresponds to blocks operation pattern (BlockMode), and it is in order to correspond to the primary storage paging Page_M in specific memory block by programmed logic address Addr_P.
For example, the L2P table of comparisons L2P_1 corresponding to blocks operation pattern is in units of block, the page address of logic level is corresponded to physical storage paging, as shown in Figure 2.Furthermore, multiple logical storage paging P (L_N) of a logical storage block B (L), P (L_N+1) ..., P (L_N+M) are belonged to together for logic level, it also corresponds to multiple physical storage paging P (P_N) in an identical physical memory blocks B (P), P (P_N+1) ..., P (P_N+M) in entity aspect, and wherein N and M is natural number.
Memory Controller 30 more judges whether flash memory 10 operates in extract operation (RandomAccess) pattern.For example, Memory Controller 30 is the capacity with reference to programming instruction CMD and storer aspect 10_P1 and 10_P2, judges whether flash memory 10 operates in in extract operation pattern.
When flash memory 10 operates in extract operation pattern, Memory Controller 30 sets up L2P table of comparisons L2P_2, programmed logic address CMD to be corresponded to the back up memory space in storer aspect 10_P2.For example, L2P table of comparisons L2P_2 corresponds to paging activity pattern (PageMode), and it is in order to correspond to the temporary storage paging Page_T in storer aspect 10_P2 in a scratch block Block_T by programmed logic address Addr_P.After setting up the L2P table of comparisons L2P_1 and LTP_2, Memory Controller 30 is more programmed to storer aspect 10_P1 and 10_P2 simultaneously, with the back-up storage paging Page_T of the primary storage paging Page_M and write storer aspect 10_p2 that programming data Data are write storer aspect 10_P1.
For example, the L2P table of comparisons L2P_2 corresponding to paging activity pattern is in units of paging, the page address of logic level is corresponded to physical storage paging, as shown in Figure 3.Furthermore, multiple logical storage paging P (L_N) of a logical storage block B_L, P (L_N+1) ..., P (L_N+M) are belonged to together for logic level, it may correspond to part paging P (L_N+1) in different memory block B (P_X), B (P_Y) and B (P_Z), P (L_N+2) ..., P (L_N+M) in entity aspect, and wherein N and M is natural number.
After the programming operation to primary storage paging Page_M and back-up storage paging Page_T, Memory Controller 30 more judges whether primary storage paging Page_M programmes successfully.For example, whether Memory Controller 30 reference state mark Status is failed to judge the programming operation of main storage space Page_M and back up memory space Page_T.When status indicator Status indicate main storage space Page_M and back up memory space Page_T part or all of programming operation wherein be unsuccessfully time, whether unsuccessfully Memory Controller 30 is further judges the operation of main storage space Page_M.
When primary storage paging Page_M program fail, back-up storage paging Page_T is pointed in the address corresponding to primary storage paging Page_T by Memory Controller 30.In other words, Memory Controller 30 is when the programming operation failure of primary storage paging Page_M, the instruction of access primary storage paging is corresponded to the instruction of access back-up storage paging Page_T, provide the programming data Data stored in back-up storage paging Page_T to carry out bug patch to flash memory 10 with this.
Similar in appearance to aforesaid operation, Memory Controller 30 can according to the L2P table of comparisons L2P_1 and L2p_2, storer aspect 10_P1 and 10_P2 is programmed simultaneously, the programming data Data of other primary storage paging corresponding to storer aspect 10_P1 is write in the back-up storage paging of this other primary storage paging and correspondence simultaneously, and when this other primary storage paging generation program fail, with the data stored in the back-up storage paging of correspondence, bug patch is carried out to it.
In other operational instances, when flash memory 10 not operation is in extract operation pattern, and when such as operating in series of operations (SequentialAccess) pattern, programming data Data is write the main storage space Page_M of storer aspect 10_P1 by Memory Controller 30, and does not perform and carry out the operation of programming for back-up storage paging.
Please refer to Fig. 4, it illustrates the process flow diagram of the memory programming method according to the embodiment of the present invention.First as step (a), Memory Controller 30 receives programming instruction CMD, comprising programmed logic address Addr_P.Then as step (b), Memory Controller 30 sets up L2P table of comparisons L2P_1, programmed logic address CMD to be corresponded to the primary storage paging Page_M in storer aspect 10_P1.
Then as step (c), Memory Controller 30 judges whether flash memory 10 operates in extract operation pattern; If perform step (d), Memory Controller 30 sets up L2P table of comparisons L2P_2, programmed logic address Addr_P to be corresponded to the back-up storage paging Page_T in storer aspect 10_P2.
Then as step (e), Memory Controller 30 couples of storer aspect 10_P1 and 10_P2 programme simultaneously, with the back-up storage paging Page_T of the primary storage paging Page_M and write storer aspect 10_P2 that programming data Data are write storer aspect 10_P1.
Then as step (f), Memory Controller 30 judges whether primary storage paging Page_M programmes successfully.For example, step (f) comprises sub-step (f1) and (f2), as shown in Figure 5.In step (f1), Memory Controller 30 reference state mark Status, judges that whether the programming operation of primary storage paging Page_M and back-up storage paging Page_T is failed; If perform step (f2), Memory Controller 30 judges that whether the operation of primary storage paging Page_M is failed further.
Perform step (g) when primary storage paging Page_M program fail, back-up storage paging Page_T is pointed in the address corresponding to primary storage paging Page_M by Memory Controller 30, carries out bug patch with this to flash memory 10.
After step (c), when flash memory 10 not operation is when with extract operation pattern, perform step (h), programming data Data writes in the primary storage paging Page_M of storer aspect 10_P1 by Memory Controller 30, and does not perform the operation of programming to back-up storage paging Page_T.
The memory programming method of the embodiment of the present invention and the flash memory device applying it be applied to there is first and second storer aspect flash memory in.The memory programming method of the embodiment of the present invention and apply it flash memory device more in this flash disk operation when with extract operation pattern, then set up a L2P table of comparisons and the programmed logic address of reception corresponded to main storage space in first memory aspect, set up the 2nd L2P table of comparisons and programmed logic address corresponded to the back up memory space in second memory aspect and programming data write according to this in this main storage space and this back up memory space simultaneously.When main storage space generation program fail, back up memory space is pointed in the address that the memory programming method of the embodiment of the present invention and the flash memory device applying it can correspond to main storage space, carries out bug patch with this to flash memory.Accordingly, compared to conventional flash memory, the memory programming method of the embodiment of the present invention and apply its flash memory device accordingly can effectively to the advantage that the data of program fail are replied.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (6)
1. a memory programming method, is applied to a flash memory, and wherein this flash memory comprises a first memory aspect (Plane) and a second memory aspect, and this memory programming method comprises:
Receive a programming instruction, comprise a programmed logic address;
Set up one first logic to entity (Logic-to-Physical, the L2P) table of comparisons, this programmed logic address to be corresponded to the main storage space in this first memory aspect;
Judge whether this flash memory operates in one with extract operation (RandomAccess) pattern;
When this flash disk operation is when this is with extract operation pattern, set up one the 2nd L2P table of comparisons, this programmed logic address to be corresponded to the back up memory space in this second memory aspect;
To this first and this second memory aspect programme, a programming data write this main storage space of this first memory aspect and to write this back up memory space of this second memory aspect simultaneously; And
Judge whether main storage space programmes successfully; If not, back up memory space is pointed in the address corresponding to main storage space.
2. memory programming method according to claim 1, wherein when this flash memory not operation performs in this with during extract operation pattern:
This programming data is write this main storage space of this first memory aspect.
3. memory programming method according to claim 1, wherein judges that this main storage space successful step of whether programming more comprises:
With reference to a status indicator, judge that whether the programming operation of this main storage space and this back up memory space is failed; And
When this status indicator indicate the programming operation of this main storage space and this back up memory space be unsuccessfully time, judge the operation whether failure of this main storage space.
4. a flash memory device, carries out data program operation in response to a programming instruction, and this programming instruction comprises a programmed logic address, and this flash memory device comprises:
One flash memory, comprises a first memory aspect (Plane) and a second memory aspect;
One buffer, in order to the temporary programming data corresponding to this programming instruction; And
One Memory Controller, one first logic is set up to entity (Logic-to-Physical in response to this programming instruction, L2P) table of comparisons, this programmed logic address to be corresponded to the main storage space in this first memory aspect, this Memory Controller more judges whether this flash memory operates in one with extract operation (RandomAccess) pattern;
Wherein, when this flash disk operation is when this is with extract operation pattern, this Memory Controller sets up one the 2nd L2P table of comparisons, this programmed logic address to be corresponded to the back up memory space in this second memory aspect, this Memory Controller more to this first and this second memory aspect programme, this programming data write this main storage space of this first memory aspect and to write this back up memory space of this second memory aspect simultaneously; Memory Controller more judges whether main storage space programmes successfully, if not, then back up memory space is pointed in the address corresponding to main storage space.
5. flash memory device according to claim 4, wherein when this flash memory not operation is when this is with extract operation pattern, this programming data is write this main storage space of this first memory aspect by this Memory Controller.
6. flash memory device according to claim 4, whether wherein this Memory Controller is with reference to a status indicator, failed to judge the programming operation of this main storage space and this back up memory space;
When this status indicator indicate the programming operation of this main storage space and this back up memory space be unsuccessfully time, this Memory Controller judges the operation whether failure of this main storage space further.
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| CN101241769A (en) * | 2007-02-08 | 2008-08-13 | 三星电子株式会社 | A repairable semiconductor memory device and method of repairing the same |
| CN101872644A (en) * | 2009-04-24 | 2010-10-27 | 威刚科技（苏州）有限公司 | Electronic storage device and storage method thereof |
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| CN101561749A (en) * | 2008-04-17 | 2009-10-21 | 旺玖科技股份有限公司 | Flash-memory control circuit and control method |
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| CN101241769A (en) * | 2007-02-08 | 2008-08-13 | 三星电子株式会社 | A repairable semiconductor memory device and method of repairing the same |
| CN101872644A (en) * | 2009-04-24 | 2010-10-27 | 威刚科技（苏州）有限公司 | Electronic storage device and storage method thereof |
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