CN101561749A - Flash-memory control circuit and control method - Google Patents
Flash-memory control circuit and control method Download PDFInfo
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- CN101561749A CN101561749A CNA200810092223XA CN200810092223A CN101561749A CN 101561749 A CN101561749 A CN 101561749A CN A200810092223X A CNA200810092223X A CN A200810092223XA CN 200810092223 A CN200810092223 A CN 200810092223A CN 101561749 A CN101561749 A CN 101561749A
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- data block
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Abstract
The invention relates to a flash-memory control circuit and a control method. The flash-memory control circuit comprises a host interface, a flash-memory controller, a predicting unit, a progressive data block access unit and a non-progressive data block assess unit, wherein the host interface is used for receiving a first access command outputted by a host, the predicting unit judges the progressive storage or random storage of the host on the flash memory according to the first access command to selectively output the first access request or the second access request, the progressive data block access unit controls the flash-memory controller to execute the write-in operation of the progressive data block according to the first access request, and the non-progressive data block access unit controls the flash-memory controller to execute the write-in operation of the non-progressive data block according to the second access request.
Description
Technical field
The present invention relates to a kind of control circuit and control method of flash memory, and particularly to relate to a kind of be sequential access or random access and dynamically select the control circuit and the control method of the flash memory of preferable page or leaf mapping mode according to main frame to flash memory.
Background technology
Please refer to Fig. 1, it shows is with the synoptic diagram of dummy data block mapping to the solid data piece.Existing flash memory file system (FFS) is a mode of utilizing data block mapping (Block Mapping), dummy data block 120 is distinguished mappings in solid data piece 140, that is the elementary cell of mapping is a data block.Wherein, existing flash memory file system is to find out and dummy data block 120 corresponding solid data pieces 140 by a data block mapping table (Block Mapping Table).
Dummy data block 120 and solid data piece 140 comprise virtual page and physical page respectively, and the mapping mode of virtual page and physical page can be following first kind of page or leaf mapping mode or second kind of page or leaf mapping mode.
First kind of page or leaf mapping mode
Please refer to Fig. 2, it shows the synoptic diagram of first kind of page or leaf mapping mode.Dummy data block 120 shown in Fig. 1 is to represent with dummy data block 120 (1) to dummy data block 120 (m) in Fig. 2, and dummy data block 120 (1) to dummy data block 120 (m) comprises that respectively virtual page 122 (0) is to virtual page 122 (n).And
Aforesaid first kind of page or leaf mapping mode is called data block (In-Order Block) in proper order.In first kind of page or leaf mapping mode, the 1st virtual page 122 (1) of first dummy data block 120 (1) is 1st physical page 142 (1) of mapping to first solid data piece 140 (1), and the 2nd virtual page 122 (2) of first dummy data block 120 (1) is 2nd virtual page 142 (2) of mapping to first solid data piece 140 (1), by that analogy.Similarly, the 1st virtual page 122 (1) of second dummy data block 120 (2) is the 1st physical page 122 (1) of mapping to the second a solid data piece 140 (2), and the 2nd virtual page 122 (2) of second dummy data block 120 (2) is the 2nd physical page 142 (2) of mapping to the second a solid data piece 140 (2), by that analogy.
Because dummy data block 120 (1) to the virtual page in the dummy data block 120 (m) is and the physical page in regular turn mapping of solid data piece 140 (1) to the solid data piece 140 (m), therefore, do not need extra page or leaf mapping table (Page Mapping Table) can find out and physical page 142 corresponding physical page 122.
Second kind of page or leaf mapping mode
Second kind of page or leaf mapping mode is called non-data block in proper order (Out-of-Order Block).In second kind of page or leaf mapping mode, physical page 122 in each dummy data block 120 and the virtual page 142 in the solid data piece 140 there is no the relation of above-mentioned mapping in regular turn.So, need set up extra page or leaf mapping table (PageMapping Table) and just can find out and virtual page 142 corresponding physical page 122.
Yet when main frame is during to flash memory random access (Random Write Sequence), first kind of page or leaf mapping mode will cause the reduction of usefulness.In addition, when main frame is during to flash memory sequential access (SequentialWrite Sequence), second kind of page or leaf mapping mode also will cause the reduction of usefulness.Therefore, how to propose preferable settling mode, promptly become present institute urgent problem to improve the reduction of usefulness.
Summary of the invention
The present invention relates to a kind of control circuit and control method of flash memory, is sequential access or random access and dynamically select preferable page or leaf mapping mode (as data block (In-OrderBlock) or non-data block in proper order (Out-Of-Order Block) in proper order) according to main frame to flash memory, and then improves usefulness.。
According to the present invention, a kind of control circuit of flash memory is proposed.The control circuit of flash memory is used for the data access between main control system and the flash memory, and control circuit comprises host interface, flash controller, predicting unit, data block (In-Order Block) access unit and non-data block in proper order (Out-Of-Order Block) access unit in proper order.
Host interface is in order to receiving first access command of main frame output, with access one more new data block to flash memory.Predicting unit judges that according to first access command main frame is to flash memory sequential access (SequentialWrite Sequence) or random access (Random Write Sequence), optionally to export one first access request (Access Request) or one second access request.
Data block (In-Order Block) access unit is carried out a data block write operation in proper order (In-Order Block Write Operation) according to first access request control flash controller to flash memory in proper order.But not data block (Out-Of-Order Block) access unit is carried out a non-data block in proper order (Out-Of-Order Block Write Operation) write operation according to second access request control flash controller in proper order.
According to the present invention, a kind of control method of flash memory is proposed.The control method of flash memory is used for the data access between main control system and the flash memory, and control method comprises: (a) receive first access command of main frame output, first access command in order to access more new data block to flash memory.(b) judge that according to write command main frame is to flash memory sequential access (Sequential Write Sequence) or random access (Random WriteSequence), optionally to export first access request (Access Request) or second access request.(c) control this flash controller according to first access request flash memory is carried out data block (In-Order Block) write operation in proper order.(d) carry out non-data block in proper order (Out-Of-Order Block) write operation according to second access request control flash controller.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
It is with the synoptic diagram of dummy data block mapping to the solid data piece that Fig. 1 shows.
It is the synoptic diagram of first kind of page or leaf mapping mode that Fig. 2 shows.
Fig. 3 shows the synoptic diagram according to the control circuit of a kind of flash memory of a preferred embodiment of the present invention.
It is the synoptic diagram of access command that Fig. 4 shows.
Fig. 5 shows the process flow diagram according to the control method of a kind of flash memory of a preferred embodiment of the present invention.
The reference numeral explanation
20: main frame
30: the control circuit of flash memory
40: flash memory
120,120 (1)～120 (m): dummy data block
122 (1)～122 (n): virtual page
140,140 (1)～140 (m): solid data piece
144 (1)～142 (n): virtual page
310: host interface
320: predicting unit
330: data block access unit in proper order
340: the non-access unit of data block in proper order
350: flash controller.
Embodiment
The control circuit of flash memory
Please refer to Fig. 3, it shows the synoptic diagram according to the control circuit of a kind of flash memory of a preferred embodiment of the present invention.The control circuit 30 of flash memory is coupled between main frame 20 and the flash memory 40, and is used for the data access between main control system 20 and the flash memory 40.Control circuit 30 comprises host interface 310, predicting unit 320, data block (In-Order Block) access unit 330, non-data block in proper order (Out-Of-Order Block) access unit 340 and flash controller 350 in proper order.Wherein, predicting unit 320, in proper order data block access unit 330, the non-access unit of data block in proper order 340 can hardware or software mode realize, or with the collocation of part hardware partly software realize.
When main frame 20 is during to flash memory 40 sequential access, predicting unit 320 output access request S2 are to data block (In-Order Block) access unit 330 in proper order.To indicate more new data block according to access request S2 be a data block in proper order to data block access unit 330 in proper order, and carry out data block write operations in proper order (In-Order Block WriteOperation) according to 350 pairs of flash memories of access request S2 control flash controller 40.
On the contrary, when main frame 20 is during to flash memory 40 random accesses, predicting unit 320 output access request S3 are to non-data block in proper order (Out-Of-Order Block) access unit 340.Non-data block in proper order (Out-Of-Order Block) access unit 340 indicates more according to access request S3 that new data block is a non-data block in proper order, and sets up one page mapping table (Page Mapping Table) according to new data block more.In addition, the non-access unit of data block in proper order 340 and carry out a non-data block in proper order (Out-Of-Order Block Write Operation) write operations according to access request S3 control flash controller 350.
Please refer to Fig. 4, it shows is the synoptic diagram of access command.Furthermore, predicting unit 320 for example is to judge that according to access command S1 and a pre-set criteria (Predefined Criteria) main frame 310 is to flash memory 40 sequential access or random access, and the visual demand of pre-set criteria and different enforcement aspects is arranged.
For instance, aforesaid host interface 310 was to receive access command S4 before receiving access command S1, and host interface 310 received access command S5 before receiving access command S4.Access command S1, access command S4 and access command S5 comprise respectively access type (as reading or writing), logical data block address (Logical Block Address, LBA) and sector counter values (Sector Count).And predicting unit 320 more writes down the logical data block address and the sector counter values of each access command.
Does and pre-set criteria for example equal the logical data block address of access command S1 for the summation of the logical data block address of calculating access command S4 and sector counter values? if the summation of the logical data block address of access command S4 and sector counter values equals the logical data block address of access command S1, expression main frame 20 is to flash memory 40 sequential access.
Perhaps, does the summation of further calculating the logical data block address of access command S5 and sector counter values again equal the logical data block address of access command S4? if the summation of the logical data block address of access command S5 and sector counter values equals the logical data block address that the summation of the logical data block address of the logical data block address of access command S4 and access command S4 and sector counter values equals access command S1, expression main frame 20 is to flash memory 40 sequential access.
Aforesaid pre-set criteria is not limited thereto, and whether the summation that pre-set criteria also can be calculated the logical data block address of n-1 access command and sector counter values equals the logical data block address of n access command.Wherein, n=2-N, and N is a positive integer.The visual demand of pre-set criteria and determine N value size.
The control method of flash memory
Please refer to Fig. 5, it shows the process flow diagram according to the control method of a kind of flash memory of a preferred embodiment of the present invention.The control method of flash memory is used to control the data access between above-mentioned main frame 20 and the flash memory 40, and control method comprises the steps:
At first shown in step 510, host interface 310 receives the access command S1 of main frames 20 outputs, access command S1 in order to access one more new data block to flash memory 40.Then shown in step 520, note down logical data block address and the sector counter values of access command S1.
And then shown in step 530, judge that according to write command S1 main frame 20 is to flash memory 40 sequential access or random access (Random Write Sequence), with optionally output access request S2 or access request S3.If predicting unit 320 output access request S2 represent that main frame 20 is to flash memory 40 sequential access.On the contrary, if predicting unit 320 output access request S3 represent that main frame 20 is to flash memory 40 random accesses.
When main frame 20 is during to flash memory 40 sequential access, be shown in step 540, to indicate more new data block be a data block in proper order to data block access unit 330 in proper order.Then shown in step 550, data block access unit 330 is carried out data block (In-Order Block) write operation in proper order according to 350 pairs of flash memories of access request S2 control flash controller 40 in proper order.
On the contrary, when main frame 20 is during to flash memory 40 random accesses, be shown in step 560, the non-access unit of data block in proper order 340 indicates more that new data block is a non-data block in proper order.Then shown in step 570, the non-access unit of data block in proper order 340 bases more new data block are set up one page mapping table (PageMapping Table).Then shown in step 580, the non-access unit of data block in proper order 340
Carry out non-data block in proper order (Out-Of-Order Block) write operation according to access request S3 control flash controller 350.
The control circuit of the disclosed flash memory of the above embodiment of the present invention and control method, be to be flash memory 40 sequential access or random access dynamically to be selected preferable page or leaf mapping mode (as data block (In-Order Block) or non-data block in proper order (Out-Of-Order Block) in proper order), and then improve usefulness according to main frame 20.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (16)
1. the control circuit of a flash memory is used to control the data access between a main frame and the flash memory, and this control circuit comprises:
One host interface, in order to receiving one first access command of this main frame output, with access one more new data block to this flash memory;
One flash controller;
One predicting unit is in order to judge that according to this first access command this main frame is to the flash memory sequential access, optionally to export one first access request or one second access request;
One data block access unit is in proper order carried out a data block write operation in proper order in order to control this flash controller according to this first access request to this flash memory; And
The one non-access unit of data block is in proper order carried out a non-data block in proper order write operation in order to control this flash controller according to this second access request.
2. the control circuit of flash memory as claimed in claim 1, wherein, when this main frame during to the flash memory sequential access, this in proper order the data block access unit indicate this more new data block be a data block in proper order.
3. flash memory as claimed in claim 1 is sent out control circuit, wherein, when this main frame during to the flash memory random access, this non-access unit of data block in proper order indicate this more new data block be a non-data block in proper order.
4. flash memory as claimed in claim 1 is sent out control circuit, wherein, when this main frame during to the flash memory random access, this non-access unit of data block in proper order according to this more new data block set up one page mapping table.
5. flash memory as claimed in claim 1 is sent out control circuit, and wherein, this predicting unit judges that according to this first access command and a pre-set criteria this main frame is to flash memory sequential access or random access.
6. flash memory as claimed in claim 1 is sent out control circuit, wherein, before this first access command of the little reception of this host interface, receive one second access command, this first access command comprises one first logical data block address and one first sector counter values, this second access command comprises one second logical data block address and one second sector counter values, this pre-set criteria is whether the summation of calculating this second logical data block address and this second sector counter values equals this first logical data block address, is to flash memory sequential access or random access to judge this main frame.
7. the control circuit of flash memory as claimed in claim 6, wherein, this host interface is before receiving this second access command, receive one the 3rd access command, the 3rd access command comprises one the 3rd logical data block address and one the 3rd sector counter values, this pre-set criteria is whether the summation of calculating the 3rd logical data block address and the 3rd sector counter values equals this second logical data block address, is to flash memory sequential access or random access to judge this main frame.
8. the control circuit of flash memory as claimed in claim 1, wherein, this first access command comprises one first logical data block address and one first sector counter values, this default unit also writes down this first logical data block address and this first sector counter values.
9. the control method of a flash memory is used to control the data access between a main frame and the flash memory, and this control method comprises:
(a) receive one first access command of this main frame output, this first access command in order to access one more new data block to this flash memory;
(b) judge that according to this write command this main frame is to this flash memory sequential access or random access, optionally to export one first access request or one second access request;
(c) control this flash controller according to this first access request this flash memory is carried out a data block write operation in proper order; And
(d) control this flash controller according to this second access request and carry out a non-data block in proper order write operation.
10. flash memory as claimed in claim 9 is sent out control method, also comprises:
(e) when this main frame be during to the flash memory sequential access, this in proper order the data block access unit indicate this more new data block be a data block in proper order.
11. the control method of flash memory as claimed in claim 9 also comprises:
(e) when this main frame be during to the flash memory random access, this non-access unit of data block in proper order indicate this more new data block be a non-data block in proper order.
12. the control method of flash memory as claimed in claim 9 also comprises:
(e) wherein, when this main frame is during to the flash memory random access, this non-access unit of data block in proper order according to this more new data block set up one page mapping table.
13. the control method of flash memory as claimed in claim 9 wherein, is to judge that according to this first access command and a pre-set criteria this main frame is to flash memory sequential access or random access in this step (b).
14. the control method of flash memory as claimed in claim 9 also comprises:
(e) receive one second access command, this second access command is before this first access command, this first access command comprises one first logical data block address and one first sector counter values, and this second access command comprises one second logical data block address and one second sector counter values;
(f) this pre-set criteria is whether the summation of calculating this second logical data block address and this second sector counter values equals this first logical data block address, is to flash memory sequential access or random access to judge this main frame.
15. the control method of flash memory as claimed in claim 14 also comprises:
(g) receive one the 3rd access command, the 3rd access command is before this second access command, and the 3rd access command comprises one the 3rd logical data block address and one the 3rd sector counter values; And
(h) this pre-set criteria is whether the summation of calculating the 3rd logical data block address and the 3rd sector counter values equals this second logical data block address, is to flash memory sequential access or random access to judge this main frame.
16. the control method of flash memory as claimed in claim 9 also comprises:
(e) write down the one first logical data block address and one first sector counter values of this first access command.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200810092223XA CN101561749A (en) | 2008-04-17 | 2008-04-17 | Flash-memory control circuit and control method |
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| CNA200810092223XA CN101561749A (en) | 2008-04-17 | 2008-04-17 | Flash-memory control circuit and control method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521160A (en) * | 2011-12-22 | 2012-06-27 | 上海交通大学 | Write buffer detector, addressing method of written data and parallel channel write method |
| CN102956267A (en) * | 2011-08-30 | 2013-03-06 | 旺宏电子股份有限公司 | Memory programming method and flash memory device using same |
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2008
- 2008-04-17 CN CNA200810092223XA patent/CN101561749A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956267A (en) * | 2011-08-30 | 2013-03-06 | 旺宏电子股份有限公司 | Memory programming method and flash memory device using same |
| CN102521160A (en) * | 2011-12-22 | 2012-06-27 | 上海交通大学 | Write buffer detector, addressing method of written data and parallel channel write method |
| CN102521160B (en) * | 2011-12-22 | 2015-04-01 | 上海交通大学 | Write buffer detector and parallel channel write method |
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Application publication date: 20091021 |