CN107179877B - Data transmission method, memory control circuit unit and memory storage device - Google Patents

Data transmission method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN107179877B
CN107179877B CN201610133382.4A CN201610133382A CN107179877B CN 107179877 B CN107179877 B CN 107179877B CN 201610133382 A CN201610133382 A CN 201610133382A CN 107179877 B CN107179877 B CN 107179877B
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data
unit
memory
speed
temperature
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CN107179877A (en
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陈国荣
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The invention provides a data transmission method, a memory control circuit unit and a memory storage device. The method comprises the following steps: detecting a temperature of the memory storage device; and determining whether the temperature of the memory storage device is greater than a temperature threshold. If the temperature is larger than the temperature threshold, the first data is written into the rewritable non-volatile memory module within the first delay time according to the delay velocity counter value corresponding to a unit temperature. Based on the above, the technology provided by the invention can effectively control the speed of data transmission and access when the temperature of the memory storage device is too high, so that the heat generation and the heat dissipation of the memory storage device reach a stable state.

Description

Data transmission method, memory control circuit unit and memory storage device
Technical Field
The present invention relates to a data transmission method, and more particularly, to a data transmission method for a memory storage device having a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage device using the same.
Background
Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, fast reading and writing speed, etc., it is most suitable for portable electronic products, such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a relatively popular part of the electronics industry in recent years.
However, since the size of the conventional storage device with a rewritable nonvolatile memory is smaller and smaller, the rewritable nonvolatile memory storage device is prone to data loss and aging caused by accumulated heat. In addition, when such a memory storage device with a rewritable non-volatile memory is operated at a high speed, for example, when writing of a large amount of data is performed, a large amount of energy is consumed and a large amount of heat is generated, which may cause the memory storage device to be over-heated, thereby reducing the access performance or damaging the memory storage device. Therefore, it is an objective of those skilled in the art to effectively control the speed and performance of data transmission of a memory storage device to avoid system overheating during operation of the memory storage device.
Disclosure of Invention
The invention provides a data transmission method, a memory control circuit unit and a memory storage device, which can effectively control the speed and the efficiency of data transmission and access of the memory storage device, thereby avoiding the overheating of a memory storage system caused by continuous access of a large amount of data.
An exemplary embodiment of the present invention provides a data transmission method for a memory storage device having a rewritable non-volatile memory module. The data transmission method comprises the following steps: and detecting the temperature of the memory storage device, and judging whether the temperature of the memory storage device is greater than a temperature threshold value. If the temperature of the memory storage device is larger than the temperature threshold value, writing first data into the rewritable non-volatile memory module within a first delay time according to a delay velocity counter value corresponding to a unit temperature.
In an exemplary embodiment of the invention, the data transmission method further includes: setting the maximum allowable temperature value and the full-speed execution speed of the memory storage device; and calculating the delay speed count value according to the full-speed execution speed, the highest allowable temperature value and the temperature threshold value.
In an exemplary embodiment of the invention, the step of calculating the delay speed count value according to the full speed execution speed, the maximum allowable temperature value and the temperature threshold value includes: the full speed execution speed is divided into a plurality of delay speed halves according to a first temperature difference value between the highest allowable temperature value and the temperature threshold, wherein the value of each delay speed half is equal to the delay speed count value.
In an exemplary embodiment of the invention, the step of writing the first data into the rewritable non-volatile memory module within the first delay time according to the delay speed counter value corresponding to the unit temperature includes: according to a first unit size of data transmitted or accessed by the memory storage device, respectively forming a plurality of parts of first data into a plurality of first data groups, wherein the size of one first data group is equal to the first unit size; and sequentially writing each first data group into the first idle physical erasing units extracted from the at least one idle physical erasing unit within a second delay time corresponding to each first data group according to the delay speed counter value.
In an exemplary embodiment of the invention, the step of sequentially writing each first data group into the first idle physical erase units extracted from the at least one idle physical erase unit within the second delay time corresponding to each first data group according to the delay speed count value comprises: obtaining a target access speed according to a second temperature difference value between the temperature of the memory storage device and the temperature threshold value and a delay speed count value; and calculating a second delay time corresponding to each of the first data groups according to the target access speed and the size of each of the first data groups, wherein the first unit size is equal to the size of one physical programming unit.
In an exemplary embodiment of the invention, the step of writing the first data into the rewritable non-volatile memory module within the first delay time further includes: the first data is received from the host system within a third delay time according to the delayed speed meter value.
In an exemplary embodiment of the present invention, the step of receiving the first data from the host system within a third delay time according to the delayed speed meter value includes: obtaining a target access speed according to a second temperature difference value between the temperature of the memory storage device and the temperature threshold value and a delay speed count value; calculating a fourth delay time of the first data corresponding to each part according to the target access speed and the size of each first data; and sequentially receiving the first data of each portion within a fourth delay time corresponding to the first data of each portion, wherein the size of the first data of one portion is smaller than a second unit size of one physical programming unit.
In an exemplary embodiment of the invention, the data transmission method further includes: selecting a first physical erasing unit from the physical erasing units, wherein the first physical erasing unit does not comprise a first idle physical erasing unit and stores a plurality of data; forming at least one valid datum in the data into a plurality of second data groups according to a first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one second data group is equal to a second unit size; sequentially writing each second data group from the cache unit to a second idle physical erasing unit extracted from at least one idle physical erasing unit within a second delay time corresponding to each second data group according to the delay speed counting value, wherein the second idle physical erasing unit is different from the first idle physical erasing unit; and erasing the first physical erase unit.
In an exemplary embodiment of the invention, the step of writing each of the second data groups into the second idle physical erase units extracted from the at least one idle physical erase unit sequentially within the second delay time corresponding to each of the second data groups according to the delay speed count value comprises: obtaining a target access speed according to a second temperature difference value between the temperature of the memory storage device and the temperature threshold value and a delay speed count value; and calculating a second delay time corresponding to each second data group according to the target access speed and the size of each second data group, wherein the first unit size is equal to the size of one physical programming unit.
An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device having a rewritable non-volatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is coupled to a host system, the memory interface is coupled to the rewritable non-volatile memory module, and the memory management circuit is coupled to the host interface and the memory interface. Memory management circuitry is used to detect a temperature of the memory storage device. The memory management circuit is further used for judging whether the temperature of the memory storage device is larger than a temperature threshold value or not, and if the temperature is larger than the temperature threshold value, the memory management circuit is further used for issuing a first write-in instruction sequence to indicate that the first data is written into the rewritable non-volatile memory module according to the delay speed counter value corresponding to a unit temperature within a first delay time.
In an exemplary embodiment of the invention, the memory management circuit is further configured to set a maximum allowable temperature value and a full speed execution speed of the memory storage device, and calculate the delay speed count value according to the full speed execution speed, the maximum allowable temperature value and a temperature threshold.
In an exemplary embodiment of the invention, in the calculating the delay speed count value according to the full-speed execution speed, the highest allowable temperature value and the temperature threshold, the memory management circuit is further configured to divide the full-speed execution speed into a plurality of delay speed halves according to a first temperature difference between the highest allowable temperature value and the temperature threshold, wherein a value of each delay speed half is equal to the delay speed count value.
In an exemplary embodiment of the invention, the rewritable non-volatile memory module includes a plurality of physical erase units, and the physical erase units include at least one idle physical erase unit, and the memory management circuit issues the first write command sequence to instruct the operation of writing the first data into the rewritable non-volatile memory module within a first delay time according to the delay speed counter value corresponding to the unit temperature, and the memory management circuit respectively combines a plurality of portions of the first data into a plurality of first data groups according to a first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one first data group is equal to the first unit size. In addition, the memory management circuit issues the first write command sequence to instruct each first data group to be written into the first idle physical erasing unit extracted from the at least one idle physical erasing unit within the second delay time corresponding to each first data group in sequence according to the delay speed count value.
In an exemplary embodiment of the invention, the memory management circuit obtains the target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value in the operation of issuing the first write command sequence to instruct writing of each first data group into the first idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each first data group in sequence according to the delay speed count value; and calculating a second delay time corresponding to each of the first data groups according to the target access speed and the size of each of the first data groups, wherein the first unit size is equal to the size of one physical programming unit.
In an exemplary embodiment of the invention, before the first write command sequence is issued to instruct the first data to be written into the rewritable non-volatile memory module within the first delay time, the memory management circuit is further configured to receive the first data from the host system within a third delay time according to the latency counter value.
In an exemplary embodiment of the invention, in the operation of receiving the first data from the host system within the third delay time according to the latency counter value, the memory management circuit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold value and the latency counter value; calculating a fourth delay time of the first data corresponding to each part according to the target access speed and the size of each first data; and sequentially receiving the first data of each portion within a fourth delay time corresponding to the first data of each portion, wherein the size of the first data of one portion is smaller than a second unit size of one physical programming unit.
In an exemplary embodiment of the invention, the memory management circuit is further configured to select a first physical erase unit from the physical erase units, wherein the first physical erase unit does not include a first idle physical erase unit and stores a plurality of data. The memory management circuit combines at least one valid data of the data into a plurality of second data groups according to a first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one second data group is equal to the first unit size. In addition, the memory management circuit issues a second write command sequence to instruct each second data group to be written into a second idle physical erasing unit extracted from at least one idle physical erasing unit in sequence within a second delay time corresponding to each second data group according to the delay speed count value, wherein the second idle physical erasing unit is different from the first idle physical erasing unit. Then, the memory management circuit erases the first physical erase unit.
In an exemplary embodiment of the invention, the memory management circuit obtains the target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value in the operation of issuing the second write command sequence to instruct writing of each second data group into the second idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each second data group in sequence according to the delay speed count value; and calculating a second delay time corresponding to each second data group according to the target access speed and the size of each second data group, wherein the first unit size is equal to the size of one physical programming unit.
An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and the memory control circuit unit. The connection interface unit is coupled to the host system, and the memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for detecting the temperature of the memory storage device and judging whether the temperature is greater than a temperature threshold value. If the temperature is higher than the temperature threshold, the memory control circuit unit issues a first write command sequence to instruct to write a first data into the rewritable non-volatile memory module according to the delay speed counter value corresponding to a unit temperature within a first delay time.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to set a maximum allowable temperature value and a full-speed execution speed of the memory storage device, and calculate the delay speed count value according to the full-speed execution speed, the maximum allowable temperature value and the temperature threshold.
In an exemplary embodiment of the invention, in the operation of calculating the delay speed count value according to the full-speed execution speed, the highest allowable temperature value and the temperature threshold value, the memory control circuit unit divides the full-speed execution speed into a plurality of delay speed halves according to a first temperature difference value between the highest allowable temperature value and the temperature threshold value, wherein a value of each delay speed half is equal to the delay speed count value.
In an exemplary embodiment of the invention, the rewritable non-volatile memory module includes a plurality of physical erase units, and the physical erase units include at least one idle physical erase unit. The memory control circuit unit is further configured to combine a plurality of portions of the first data into a plurality of first data groups according to a first unit size of data transmitted or accessed by the memory storage device, wherein the size of one first data group is equal to the first unit size. The memory control circuit unit is further configured to issue the first write command sequence to instruct each of the first data groups to be written into the first idle physical erase unit extracted from the at least one idle physical erase unit within a second delay time corresponding to each of the first data groups in sequence according to the delay velocity indicator value.
In an exemplary embodiment of the invention, the memory control circuit unit obtains the target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value in the operation of issuing the first write command sequence to instruct writing of each first data group into the first idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each first data group in sequence according to the delay speed count value; and calculating a second delay time corresponding to each first data group according to the target access speed and the size of each first data group, wherein the first unit size is equal to the size of one physical programming unit.
In an exemplary embodiment of the invention, in the above operation before the first write command sequence is issued to indicate the first data is written into the rewritable non-volatile memory module within the first delay time, the memory control circuit unit receives the first data from the host system within a third delay time according to the latency counter value.
In an exemplary embodiment of the invention, in the operation of receiving the first data from the host system within the third delay time according to the latency counter value, the memory control circuit unit is further configured to obtain a target access speed according to a second temperature difference between a temperature of the memory storage device and a temperature threshold value and the latency counter value; calculating a fourth delay time of the first data corresponding to each part according to the target access speed and the size of each first data; and sequentially receiving each of the first data within a fourth delay time corresponding to each of the portions of the first data, wherein the size of one portion of the first data is smaller than the second unit size of one physical program cell.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to select a first physical erase unit from the physical erase units, wherein the first physical erase unit does not include a first idle physical erase unit and stores a plurality of data, and the memory control circuit unit is further configured to group at least one valid data of the data into a plurality of second data groups according to a first unit size of data transmitted or accessed by the memory storage device, wherein a size of one second data group is equal to the first unit size. In addition, the memory control circuit unit issues a second write command sequence to instruct each second data group to be written into a second idle physical erasing unit extracted from at least one idle physical erasing unit in sequence within a second delay time corresponding to each second data group according to the delay speed count value, wherein the second idle physical erasing unit is different from the first idle physical erasing unit. Then, the memory control circuit unit is further used for erasing the first physical erasing unit.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to obtain the target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value in the operation of issuing the second write command sequence to instruct writing of each second data group from the cache unit to the second idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each second data group in sequence according to the delay speed count value; and the memory control circuit unit is further used for calculating a second delay time corresponding to each second data group according to the target access speed and the size of each second data group, wherein the first unit size is equal to the size of one physical programming unit.
Based on the above, the exemplary embodiments of the present invention control the speed and performance of data transmission and access to the memory storage device by limiting the amount of data transmitted from the host system to the memory storage device and the amount of data written by the memory control circuit unit (or the memory management circuit) in the memory storage device to the rewritable non-volatile memory module. Therefore, when the temperature of the memory storage device is overhigh, the speed of data transmission and access can be effectively controlled, and the heat generation and the heat dissipation of the memory storage device can reach a stable state.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment;
FIG. 6 is a diagram illustrating a buffer memory according to an example embodiment;
FIGS. 7A and 7B illustrate exemplary diagrams of managing physically erased cells in accordance with an exemplary embodiment;
FIG. 8 illustrates an example of temperature versus speed for data access speed control of a memory storage device, according to an example embodiment;
fig. 9 is a flowchart illustrating a data transmission method according to an exemplary embodiment of the invention.
Description of reference numerals:
10. 30: a memory storage device;
11. 31: a host system;
12: an I/O device;
110: a system bus;
111: a processor;
112: random Access Memory (RAM);
113: read Only Memory (ROM);
114: a data transmission interface;
20: a main board;
201: a U disk;
202: a memory card;
203: a solid state disk;
204: a wireless memory storage device;
205: a Global Positioning System (GPS) module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card (eMMC);
342: an embedded multi-chip package memory device (eMCP); 402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable non-volatile memory module;
408：DDR DRAM；
410(0) to 410 (N): a physical erase unit;
502: a memory management circuit;
504: a host interface;
506: a memory interface;
508: a buffer memory;
510: a power management circuit;
512: an error checking and correcting circuit;
610(0) to 610 (511): a buffer unit;
702: a data area;
704: an idle area;
706: a system area;
708: a substitution region;
710(0) -710 (D): a logic unit;
s901: step (detecting the temperature of the memory storage device);
s903: a step of judging whether the temperature of the memory storage device is greater than a temperature threshold value;
s905: writing the first data into the rewritable non-volatile memory module within a first delay time according to a delay velocity counter value corresponding to a unit temperature.
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to the system bus 110.
In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 is coupled to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 over system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be coupled to the memory storage device 10 via the data transmission interface 114 in a wired or wireless manner. Coupled or wirelessly transmitted to the memory storage device 10, wherein the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be various types of memory storage devices based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or low power Bluetooth memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be coupled to various types of I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package memory devices (eMCP) 342, which directly couple the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Chip Package) interface standard, the Multimedia storage Card (Multi-Media, Multimedia Card (Multimedia Card, Multimedia Card) interface (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-chip package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented by hardware or software, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 has physical erasing units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each physical erasing unit is respectively provided with a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each physical erase unit may be composed of 64 physical program units, 256 physical program units, or any other physical program units.
In more detail, the physical erase unit is the minimum unit of erase. That is, each physical erase cell contains the minimum number of memory cells that are erased together. The physical programming unit is the smallest unit of a program. That is, the physical programming unit is the smallest unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program cell includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.
In the exemplary embodiment, the rewritable nonvolatile memory module 406 is a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory Cell). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a Single Level Cell (SLC) NAND-type flash memory module (i.e., a flash memory module that can store 1 data bit in one memory Cell), a multiple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 data bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.
In another exemplary embodiment of the invention, the memory storage device 10 further includes a Double Data Rate dynamic random access memory (DDR DRAM)408 for temporarily storing a plurality of logic gates or control commands implemented in software executed by the memory control circuit unit 404, for example, when the memory control circuit unit 404 is enabled, the memory control circuit unit 404 executes a driving code to load the control commands stored in the rewritable nonvolatile memory module 406 into the DDR DRAM408, and accordingly, the memory control circuit unit 404 can write, read and erase Data in the rewritable nonvolatile memory module 406 according to the control commands. Here, the driving code is, for example, burned into the rom of the memory control circuit unit 404. However, the present invention is not limited to the location of the DDRDRAM 408, for example, in another exemplary embodiment, the DDR DRAM408 may be implemented in the memory control circuit unit 404.
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an example embodiment.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.
In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in the form of program codes in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown), and in an example in which the DDR DRAM408 is disposed in the memory control circuit unit 404, the random access memory of the memory management circuit 502 may be, for example, the DDR DRAM408 described above. In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in hardware. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing the memory cells or the group thereof of the rewritable non-volatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable non-volatile memory module 406 so as to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an exemplary embodiment, the memory management circuit 502 may also issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is coupled to the memory management circuit 502 and is used for being coupled to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transfer standards.
The memory interface 506 is coupled to the memory management circuit 502 and is used for accessing the rewritable non-volatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program codes. For example, the read command sequence includes read identification code, memory address, and the like.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.
The buffer memory 508 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406.
FIG. 6 is a diagram illustrating a buffer memory according to an example embodiment.
Referring to FIG. 6, the buffer 508 has 512 buffer units (i.e., buffer units 610(0) - (610) (511)), and each buffer unit has a size of 4 KB. Specifically, the size of the four buffer units corresponds to the size of a physical programming unit (also referred to as a first unit size) of the rewritable non-volatile memory. However, it should be understood that the number of cache units disposed in the cache memory 508, the size of the cache units, and the size of the data transmitted by the host system 11 are not limited in the exemplary embodiment. For example, in other example embodiments, the number of cache molecules in the cache memory 508 may be greater or less than 512 cache molecules in size. In addition, the host system 11 transfers or accesses data in units of, for example, 4KB (also referred to as a second unit size), and the memory control circuit unit 404 (or the memory management circuit 502) transfers or accesses data in units of, for example, 16KB (i.e., a first unit size). Alternatively, in another exemplary embodiment, the size of the data transferred or accessed by the host system 11 at a time may be larger or smaller than 4KB, and the size of the data transferred or accessed by the memory control circuit unit 404 (or the memory management circuit 502) at a time may be larger or smaller than 16 KB.
Referring to fig. 5, the power management circuit 510 is coupled to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
The error checking and correcting circuit 512 is coupled to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the corresponding error checking and correcting code is simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting procedure on the read data according to the error checking and correcting code.
FIGS. 7A and 7B illustrate exemplary diagrams of managing physically erased cells according to an exemplary embodiment.
It should be understood that, when describing the operation of the physical erase unit of the rewritable non-volatile memory module 406, it is a logical concept to operate the physical erase unit by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable non-volatile memory module are not changed, but the physical erase units of the rewritable non-volatile memory module are logically operated.
Referring to FIG. 7A, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 702, an idle area 704, a system area 706 and a replacement area 708.
The physical erase units logically belonging to the data area 702 and the idle area 704 are used to store data from the host system 11. Specifically, the physical erase cells in the data area 702 are regarded as the physical erase cells with stored data, and the physical erase cells in the idle area 704 are used to replace the physical erase cells in the data area 702. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 extracts physical erase cells from the idle region 704 and writes the data into the extracted physical erase cells to replace the physical erase cells of the data region 702.
The physical erase unit logically belonging to the system area 706 is used to record system data. For example, the system data includes information about the manufacturer and model of the rewritable non-volatile memory module, the number of physically erased cells of the rewritable non-volatile memory module, the number of physically programmed cells of each physically erased cell, and the like.
The physically erased cells logically belonging to the replacement area 708 are used in the bad physically erased cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physical erase cells in the replacement area 708 and the physical erase cells in the data area 702 are damaged, the memory management circuit 502 extracts the normal physical erase cells from the replacement area 708 to replace the damaged physical erase cells.
In particular, the number of physically erased cells in the data area 702, the idle area 704, the system area 706 and the replacement area 708 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of memory storage device 10, the grouping of physically erased cells associated with data region 702, idle region 704, system region 706, and replacement region 708 may dynamically change. For example, when the physical erased cells in the idle area 704 are damaged and replaced by the physical erased cells in the replacement area 708, the physical erased cells in the replacement area 708 are associated with the idle area 704.
Referring to FIG. 7B, as mentioned above, the physical erase units in the data area 702 and the idle area 704 are used to store data written by the host system 11 in an alternating manner. In the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) configures the logic units 710(0) to 710(D) to the host system 11 to map to the physical erase units 414(0) to 410(F-1) in the portion of the data area 702 for facilitating data access in the physical erase units storing data in the above-mentioned alternate manner. In particular, host system 11 accesses data in data area 702 through logic units 710(0) -710 (D). In addition, the memory control circuit unit 404 (or the memory management circuit 502) establishes a logical-physical mapping table (logical-physical mapping table) to record the mapping relationship between the logical units and the physical erase units. The logical-physical mapping table may also record various logical and physical corresponding relationships, such as mapping relationships between logical units and physical programming units, between logical program units and physical programming units, and/or between logical program units and physical erasing units, for example, and the invention is not limited thereto.
In the present exemplary embodiment, when the host system 11 performs a write operation, the memory control circuit unit 404 (or the memory management circuit 502) extracts physical erase cells from the idle area 704 and writes the write data corresponding to the write operation directly into the extracted physical erase cells, and replaces the extracted physical erase cells from the idle area 704 with the physical erase cells of the data area 702 by mapping the logical cells to be written by the write operation to the extracted physical erase cells. However, the present invention is not limited thereto, for example, in another exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) temporarily stores the data from the host system 11 to be written into the rewritable non-volatile memory module 406 in the extracted temporary physical erase unit, and moves the data in the temporary physical erase unit to the physical erase unit mapped by the written logical unit when performing data merging. In another exemplary embodiment of the invention, the cache units 610(0) - (610) (511) are used to temporarily store data and instructions from the host system 11 to be written into the rewritable non-volatile memory module 406 or data from the rewritable non-volatile memory module 406. Therefore, when the host system 11 performs a write operation, the memory control circuit unit 404 (or the memory management circuit 502) may first temporarily store the write data corresponding to the write operation into the unoccupied cache memory cells in the cache memory cells 610(0) -610 (511) of the cache memory 508.
That is, the physical erase units and the buffer units 610(0) - (610) (511) in the idle area 704 can be used in the memory control circuit unit 404 (or the memory management circuit 502) of the memory storage device 10 to perform the data temporary storage area during the foreground operation or the background operation. Here, the data from the host system 11 to be written into the rewritable non-volatile memory module 406 belongs to a data stream generated by performing foreground work, and the data written into the rewritable non-volatile memory module 406 during performing mapping table storage, garbage collection (garbagecollection) or error correction (error correction) belongs to a data stream generated by performing background work. The present invention controls the speed and efficiency of data transmission and access to the memory storage device 10 by limiting the amount of data written by the host system 11 into the temporary physical erase unit or the buffer unit (e.g., data stream generated by performing foreground operations) and the amount of data written from the temporary physical erase unit or the buffer unit into the rewritable non-volatile memory module 406 (e.g., data stream generated by performing foreground operations and data stream generated by performing background operations) within a limited time.
Referring to fig. 4 and 5 again, in order to avoid the system overheating phenomenon caused by the operation of the memory storage device 10, the memory control circuit unit 404 (or the memory management circuit 502) detects the temperature of the memory storage device 10 to perform the operation of controlling the data transmission speed and the data access speed when the temperature of the memory storage device 10 is greater than the temperature threshold. Here, the temperature of the memory storage device 10 may be the temperature of the memory control circuit unit 404 (or the memory management circuit 502) itself, the temperature of the DDR DRAM408, and the temperature of the rewritable non-volatile memory module 406 or the entire memory storage device 10. In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) sets the maximum allowable temperature value and the full speed execution speed of the memory storage device 10. Generally, the maximum temperature that the memory control circuit unit 404 (or the memory management circuit 502) can bear is 120 ℃, and when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) exceeds the maximum temperature, the memory control circuit unit 404 (or the memory management circuit 502) may stop operating or burn due to overheating, thereby causing data loss. In this example, the temperature of the memory control circuit unit 404 (or the memory management circuit 502) itself is detected, so that the memory control circuit unit 404 (or the memory management circuit 502) sets the maximum allowable temperature value of the memory storage device 10 to 120 ℃. However, the maximum allowable temperature value is not limited by the present invention, and for example, the maximum allowable temperature value may be set according to the technical specification of the memory storage device 10 at the time of factory shipment, or may be set according to the performance of the memory storage device 10.
In addition, under normal conditions (i.e., when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) does not reach the temperature threshold), the memory control circuit unit 404 (or the memory management circuit 502) performs data writing and reading at the full-speed execution speed, for example, the full-speed execution speed of the memory storage device 10 is set to 1400 million bits per second (MB/sec) by the memory control circuit unit 404 (or the memory management circuit 502). However, the present invention is not limited thereto, and for example, the memory control circuit unit 404 (or the memory management circuit 502) can set the full-speed execution speed of the memory storage device 10 to be greater than 1400MB/sec or less than 1400MB/sec according to the actual operation condition of the memory storage device 10 as a whole.
The temperature threshold is used as a basis for the memory control circuit unit 404 (or the memory management circuit 502) to determine whether the temperature of the memory storage device 10 is too hot, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) and the DDR DRAM408 have respective highest temperature, for example, the highest temperature that the memory control circuit unit 404 (or the memory management circuit 502) can bear is 120 ℃, the highest temperature that the DDR DRAM408 can bear is 90 ℃, since the highest temperature that the DDR DRAM408 can bear is lower than the memory control circuit unit 404 (or the memory management circuit 502), therefore, in the operation of comparing the temperature of the memory control circuit unit 404 (or the memory management circuit 502) and the temperature threshold, the temperature threshold is set to 80 ℃ to avoid that when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) is greater than the temperature threshold, the temperature of the DDR DRAM408 has exceeded the highest temperature that it can withstand (i.e., 90℃.). For example, when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) reaches 100 ℃, the temperature of the DDR DRAM408 may already exceed 80 ℃ (i.e. approach the highest temperature that can be sustained by the DDR DRAM), and therefore, setting the temperature threshold to 80 ℃ allows the operations of data transmission speed control, access speed control and temperature reduction to be performed before the temperature of the memory control circuit unit 404 (or the memory management circuit 502) and the temperature of the DDR DRAM408 have not yet reached the respective highest temperatures that can be sustained, so as to avoid the system overheating phenomenon caused by the operation of the memory storage device 10. It is noted that the temperature threshold is set according to the actually detected temperature of the memory control circuit unit 404 (or the memory management circuit 502) and the temperature of the DDR DRAM408, and the size of the temperature threshold is not limited by the invention, for example, in other exemplary embodiments, the temperature threshold may be set to be greater than 80 ℃ or less than 80 ℃.
In an exemplary embodiment of the invention, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the temperature of the memory storage device 10 (e.g., the temperature of the memory control circuit unit 404 (or the memory management circuit 502)) is greater than a temperature threshold, and if the temperature of the memory control circuit unit 404 (or the memory management circuit 502) is not greater than the temperature threshold, the memory control circuit unit 404 (or the memory management circuit 502) performs data writing and reading at the full-speed execution speed. On the contrary, if the temperature of the memory control circuit unit 404 (or the memory management circuit 502) is greater than the temperature threshold, the memory control circuit unit 404 (or the memory management circuit 502) calculates a delay speed count value corresponding to each unit temperature between the maximum allowable temperature value and the temperature threshold according to the full speed execution speed, so as to further perform the operations of data transmission speed control, access speed control and temperature reduction according to the calculated delay speed count value. Specifically, the delay speed count value is used as a basis for the memory control circuit unit 404 (or the memory management circuit 502) to reduce the data transmission speed and the access speed, for example, the memory control circuit unit 404 (or the memory management circuit 502) divides the full-speed execution speed into a plurality of delay speed halves according to a difference (also referred to as a first temperature difference) between a maximum allowable temperature value and a temperature threshold value, where each delay speed half has a size of 35MB/sec (i.e., 1400/(120 ℃ -80 ℃) in the case that the maximum allowable temperature value is 120 ℃, the temperature threshold value is 80 ℃ and the full-speed execution speed is 1400MB/sec, and the memory control circuit unit 404 (or the memory management circuit 502) sets the delay speed count value to 35 MB/sec. In this way, when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) exceeds the temperature threshold (i.e., 80 ℃) and the temperature of the memory control circuit unit 404 (or the memory management circuit 502) increases by 1 ℃, the memory control circuit unit 404 (or the memory management circuit 502) decreases the current execution speed of the memory control circuit unit 404 (or the memory management circuit 502) by 35MB/sec according to the latency rate count value. It should be noted that the invention is not limited to the method for calculating the delay speed count value or the magnitude of the delay speed count value, for example, in another exemplary embodiment of the invention, the delay speed count value can be set to be greater than 35MB/sec or less than 35MB/sec according to the requirement.
In more detail, in an example of processing a data stream generated by performing foreground work, when the host system 11 performs a write operation to write data (also referred to as first data), the memory control circuit unit 404 (or the memory management circuit 502) receives the first data from the host system 11 within a delay time (also referred to as a third delay time) according to the latency counter value, and sends a write command sequence (also referred to as a first write command sequence) to instruct to write the first data to the rewritable nonvolatile memory module 406 within another delay time (also referred to as a first delay time) according to the latency counter value. When the host system 11 performs a write operation, the memory control circuit unit 404 (or the memory management circuit 502) temporarily stores write data corresponding to the write operation into the physical erase unit of the idle area 704 or the unoccupied cache unit of the cache units 610(0) -610 (511) of the cache memory 508. Therefore, when the write data is buffered to the physical erase unit or the buffer 508 of the idle area 704, the memory control circuit unit 404 (or the memory management circuit 502) sends a confirmation message to the host system 11 to notify the host system 11 that the write operation is completed. In other words, the third delay time is the total time from the host system 11 to the memory control circuit unit 404 (or the memory management circuit 502) to the host system 11 for transmitting all the write data corresponding to the write operation to the memory storage device 10; the first delay time is the total time for the memory control circuit unit 404 (or the memory management circuit 502) to write all the write data corresponding to the write operation from the physical erase unit or the buffer unit in the idle area 704 into the rewritable non-volatile memory module 406.
For example, the memory control circuit unit 404 (or the memory management circuit 502) obtains the target access speed according to the detected difference (also referred to as a second temperature difference) between the temperature of the memory control circuit unit 404 (or the memory management circuit 502) and the temperature threshold and the delay speed counter value. Assuming that the detected temperature of the memory control circuit unit 404 (or the memory management circuit 502) is 90 ℃ and the temperature threshold and the latency rate are 80 ℃ and 35MB/sec, respectively, since the memory control circuit unit 404 (or the memory management circuit 502) decreases its current execution speed by 35MB/sec every time the temperature of the memory control circuit unit 404 (or the memory management circuit 502) exceeds the temperature threshold (i.e., 80 ℃) and the temperature of the memory control circuit unit 404 (or the memory management circuit 502) increases by 1 ℃, the memory control circuit unit 404 (or the memory management circuit 502) determines that it needs to decrease the current execution speed by 350MB/sec (i.e., (90 ℃ -80 ℃) by 35 MB/sec). In a state where the current execution speed of the memory control circuit unit 404 (or the memory management circuit 502) is the full-speed execution speed (i.e., 1400MB/sec), the memory control circuit unit 404 (or the memory management circuit 502) further obtains a target access speed of 1050MB/sec (i.e., 1400MB/sec-350 MB/sec).
Next, the memory control circuit unit 404 (or the memory management circuit 502) calculates a delay time (also referred to as a fourth delay time) of the first data corresponding to each portion according to the target access speed (i.e., 1050MB/sec) and the size of the first data of each portion. For example, the fourth latency is the time when the host system 11 starts to transmit the write command corresponding to the write operation and a 4KB write data to the memory storage device 10 and the memory control circuit unit 404 (or the memory management circuit 502) sends an acknowledge message to the host system 11. In other words, the memory control circuit unit 404 (or the memory management circuit 502) calculates a time required for the host system 11 to transfer a portion of the first data with a size of 4KB to the memory storage device 10, and the memory control circuit unit 404 (or the memory management circuit 502) temporarily stores a portion of the first data in the buffer unit of the buffer memory 508 until the host system 11 receives a confirmation message sent by the memory control circuit unit 404 (or the memory management circuit 502), so that the memory control circuit unit 404 (or the memory management circuit 502) can perform the write operation belonging to the data stream generated by performing the foreground operation at the target access speed. Here, the fourth delay time of the first data corresponding to each portion calculated by the memory control circuit unit 404 (or the memory management circuit 502) is 3.9 (microseconds) (i.e., (4 × 1024)/1050), that is, after each portion of the first data is received by the memory control circuit unit 404 (or the memory management circuit 502), it will temporarily store the portion of the first data in 3.9 to an unoccupied one of the extracted temporary physical erase unit or the cache unit, and send a confirmation message to the host system 11. If there is more than one first data to be written into the rewritable non-volatile memory module 406 transmitted by the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will temporarily store each part of the first data into the buffer unit within the fourth delay time in sequence, that is, temporarily store each part of the first data into the temporary physical erase unit or the buffer unit every 3.9, so that the memory control circuit unit 404 (or the memory management circuit 502) performs the write operation pertaining to the data stream generated by performing the foreground operation within the third delay time at 1050MB/sec, thereby achieving the effect of cooling.
FIG. 8 is a graph illustrating an example of temperature versus speed for data access speed control of a memory storage device, according to an example embodiment.
Referring to FIG. 8, in the above example where the memory control circuit unit 404 (or the memory management circuit 502) performs the write operation at 1050MB/sec for the data stream generated by performing the foreground operation, the memory control circuit unit 404 (or the memory management circuit 502) can decrease the speed of the data stream generated by the foreground operation from the full-speed execution speed (i.e., 1400MB/sec) to the target execution speed (i.e., 1050MB/sec) by sequentially buffering a portion of the first data into the temporary physical erase unit or the buffer unit at every fourth delay time, so that the current temperature (i.e., 90 ℃) of the memory control circuit unit 404 (or the memory management circuit 502) does not continuously increase. At this time, if the host system 11 does not continuously write data, the memory control circuit unit 404 (or the memory management circuit 502) sets the speed of processing the data stream generated by the foreground operation to the full-speed execution speed. Thereafter, if the host system 11 starts writing data into the memory storage device 10, the memory control circuit unit 404 (or the memory management circuit 502) determines to perform the data stream generated by foreground operation at full speed or perform the data transmission and access speed control operations according to the detected temperature and temperature threshold.
After the memory control circuit unit 404 (or the memory management circuit 502) sequentially writes the plurality of portions of the first data of 4KB size received from the host system 11 into the plurality of buffer units, the memory control circuit unit 404 (or the memory management circuit 502) transfers the plurality of portions of the first data to a Flash Translation Layer (FTL). Specifically, the flash translation layer provides a write and erase operation interface between the file system of the host system 11 and the rewritable non-volatile memory module 406. For example, the fast translation layer is formed by a controller between the operating system of the host system 11 and the memory storage device 10, and the fast translation layer can map the logical units generated by the file system of the host system 11 onto the physically erased units of the rewritable non-volatile memory module 406 during the write operation of the rewritable non-volatile memory module 406. In the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) transfers or accesses data in units of 16KB, which is the size (i.e., the first unit size) of a physically programmed unit of the rewritable non-volatile memory, and accordingly, the memory control circuit unit 404 (or the memory management circuit 502) groups the first data of every four portions into a data group of 16KB, and transfers the data group of 16KB to the rewritable non-volatile memory module 406 to be programmed and written into the rewritable non-volatile memory module 406.
In an exemplary embodiment of the invention, in addition to the memory control circuit unit 404 (or the memory management circuit 502) reducing the bus bandwidth for processing the first data written from the host system 11 to the cache unit to achieve the cooling and speed reduction, the memory control circuit unit 404 (or the memory management circuit 502) further controls the writing speed for temporarily storing the physical erase unit or the portions of the first data in the cache unit to be written into the rewritable non-volatile memory module 406. Specifically, the memory control circuit unit 404 (or the memory management circuit 502) respectively combines the first data from the multiple parts of the host system 11 into multiple first data sets according to the first unit size (i.e. the size of one physical programming unit) of the data transmitted or accessed by the memory storage device 10, for example, every four parts of the first data are combined into one first data set, i.e. the size of one first data set is equal to 16 KB. Similarly, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) obtains the delay speed count value "35 MB/sec" and the target access speed "1050 MB/sec" according to the highest allowable temperature value "120 ℃", the temperature threshold "80 ℃", the detected temperature "90 ℃" of the memory control circuit unit 404 (or the memory management circuit 502) and the full-speed execution speed "1400 MB/sec".
Then, the memory control circuit unit 404 (or the memory management circuit 502) calculates a delay time (also referred to as a second delay time) corresponding to each of the first data sets according to the target access speed (i.e., 1050MB/sec) and the size of each of the first data sets (i.e., the size of one physical program unit). In other words, the memory control circuit unit 404 (or the memory management circuit 502) calculates the time required for the memory control circuit unit 404 (or the memory management circuit 502) to program a first data set to the rewritable non-volatile memory module 406, so that the memory control circuit unit 404 (or the memory management circuit 502) can perform the write operation pertaining to the data stream generated by performing the foreground operation at the above-mentioned target access speed. Here, the second delay time corresponding to each first data group calculated by the memory control circuit unit 404 (or the memory management circuit 502) is 15.6 (microseconds) (i.e., (16 × 1024)/1050), that is, the memory control circuit unit 404 (or the memory management circuit 502) sequentially sends the first write command sequence to instruct to write each first data group into the rewritable non-volatile memory module 406 within the second delay time corresponding to each first data group. For example, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase unit (also referred to as a first idle physical erase unit) from the idle area 704 of the rewritable non-volatile memory module 406 and writes a first data set into the first idle physical erase unit within 15.6, i.e., programs a first data set into the rewritable non-volatile memory module 406 every 15.6. Therefore, not only the bus bandwidth of the upper layer of the memory storage device 10 for processing the first data written from the host system 11 to the cache unit is reduced, but also the bus bandwidth of the lower layer of the memory storage device 10 for processing the first data set written from the temporary storage physical erasing unit or the cache unit to the rewritable non-volatile memory module 406 is reduced, and the overall cooling effect can be effectively achieved by controlling the data transmission and access speed of the upper layer and the lower layer.
It should be noted that, while the memory control circuit unit 404 (or the memory management circuit 502) executes foreground work, it may also execute background work at the same time, for example, while the memory control circuit unit 404 (or the memory management circuit 502) processes data from the host system 11 to be written into the rewritable non-volatile memory module 406, the memory control circuit unit 404 (or the memory management circuit 502) may also execute background work such as garbage collection, so as to release redundant memory space. In other words, when the temperature of the memory control circuit unit 404 (or the memory management circuit 502) exceeds the temperature threshold, if only the data stream generated by the foreground operation is controlled to have the data transmission and access speed, the data stream generated by the background operation may be continuously written into the rewritable non-volatile memory module 406 at the bottom layer at the full-speed execution speed, which may affect the temperature of the memory storage device 10 and may not effectively cool down the memory storage device 10.
In another exemplary embodiment of the invention, the memory control circuit unit 404 (or the memory management circuit 502) considers the execution speed of the data stream generated by executing the background operation when writing the data stream from the buffer unit to the rewritable non-volatile memory module 406. Specifically, when the memory control circuit unit 404 (or the memory management circuit 502) performs the garbage collection procedure, one or more physical erase units (also referred to as first physical erase units) are selected from the physical erase units in the data area 702 to copy valid data from the data stored in the one or more first physical erase units, and the valid data are grouped into a plurality of data sets (also referred to as second data sets) according to a first unit size (i.e., the size of one physical program unit, for example, 16KB), for example, the size of one second data set is equal to 16 KB. Then, the memory control circuit unit 404 (or the memory management circuit 502) copies and temporarily stores each second data set into the unoccupied buffer memory cells among the temporarily stored physical erase cells or buffer memory cells in the extracted idle area 704.
Here, the steps of the memory control circuit unit 404 (or the memory management circuit 502) obtaining the latency counter and the target access speed are the same as the operation in the foregoing exemplary embodiment, and will not be repeated here. For example, the memory control circuit unit 404 (or the memory management circuit 502) can obtain the delay speed count value "35 MB/sec" and the target access speed "1050 MB/sec" based on its highest allowable temperature value "120 ℃", the temperature threshold value "80 ℃", the detected temperature "90 ℃" of the memory control circuit unit 404 (or the memory management circuit 502), and the full-speed execution speed "1400 MB/sec".
Then, the memory control circuit unit 404 (or the memory management circuit 502) calculates a second delay time corresponding to each second data set according to the target access speed (i.e., 1050MB/sec) and the size of each second data set (i.e., the size of one physical program unit). That is, the memory control circuit unit 404 (or the memory management circuit 502) calculates the time required for the memory control circuit unit 404 (or the memory management circuit 502) to program a second data set to the rewritable nonvolatile memory module 406, so that the memory control circuit unit 404 (or the memory management circuit 502) can also perform the write operation belonging to the data stream generated by executing the background operation at the above-mentioned target access speed. Similarly, the second delay time corresponding to each second data group calculated by the memory control circuit unit 404 (or the memory management circuit 502) is 15.6 (microseconds) (i.e., (16 × 1024)/1050), that is, the memory control circuit unit 404 (or the memory management circuit 502) sends a sequence of write commands (also referred to as a second write command sequence) to instruct each second data group to be written into the rewritable nonvolatile memory module 406 sequentially within the second delay time corresponding to each second data group. For example, the memory control circuit unit 404 (or the memory management circuit 502) writes a second data set stored in the temporary physical erase unit or the buffer unit into a recovery physical erase unit within 15.6, i.e., programs a second data set into the rewritable non-volatile memory module 406 every 15.6. Here, the recovered physical erase unit is, for example, a physical erase unit (also referred to as a second idle physical erase unit) extracted from the idle region 704. After writing the copied valid data to the second idle physical erase unit, the memory control circuit unit 404 (or the memory management circuit 502) erases the first physical erase unit. As such, the method for controlling data transmission and access speed according to the exemplary embodiment of the present invention not only reduces the bus bandwidth for processing the foreground data from the host system 11 to be written into the rewritable non-volatile memory module 406 at the upper layer and the bottom layer of the memory storage device 10, but also reduces the bus bandwidth for processing the background data written from the cache unit to the rewritable non-volatile memory module 406 at the bottom layer of the memory storage device 10, and can ensure that the heat generation and the heat dissipation of the memory storage device 10 can reach a stable state by controlling the transmission speed and the access speed of the foreground data and the background data.
In particular, the present invention is not limited to the time point when the memory control circuit unit 404 (or the memory management circuit 502) performs the garbage collection procedure, for example, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the available physical erase units in the physical erase units are smaller than a predetermined available number, and performs the garbage collection procedure when the available physical erase units in the physical erase units are smaller than the predetermined available number. Alternatively, in another exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) performs the garbage collection procedure at regular intervals. The garbage collection process is performed synchronously while the memory control circuit unit 404 (or the memory management circuit 502) writes the first data from the host system 11 to the extracted first idle physical erase unit. Therefore, the first physical erase unit does not include the first idle physical erase unit currently used for writing data from the host system 11. In addition, the first physical erase unit also includes a second idle physical erase unit currently used as a recovery physical erase unit, and the first idle physical erase unit is different from the second idle physical erase unit.
It should be noted that the above exemplary embodiments calculate the delay speed count value corresponding to each unit temperature between the maximum allowable temperature value and the temperature threshold value at the full speed execution speed, so as to further perform the data transmission speed control, the access speed control and the temperature reduction operation according to the calculated delay speed count value. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the magnitude of the delay counter value can also be directly set according to different requirements to achieve the cooling effect faster or to slow down the heating rate, for example, the delay counter value can be set to 50MB/sec when the cooling effect is to be achieved faster. In other words, in the example where the detected temperature of the memory control circuit unit 404 (or the memory management circuit 502) is 90 ℃ and the temperature threshold is 80 ℃, the memory control circuit unit 404 (or the memory management circuit 502) will decrease the current execution speed by 50MB/sec for every 1 ℃ increase in the temperature of the memory control circuit unit 404 (or the memory management circuit 502), and therefore the memory control circuit unit 404 (or the memory management circuit 502) will determine that it needs to decrease the current execution speed by 500MB/sec (i.e., (90 ℃ -80 ℃) by 50 MB/sec). In a state where the current execution speed of the memory control circuit unit 404 (or the memory management circuit 502) is the full-speed execution speed (i.e., 1400MB/sec), the memory control circuit unit 404 (or the memory management circuit 502) obtains a target access speed of 900MB/sec (i.e., 1400MB/sec-500 MB/sec). That is, the target access speed depends on the delay speed count value set according to the desired cooling effect, so that different cooling effects can be achieved more flexibly according to the requirement. Similarly, after the target access speed is obtained, the delay time for transmitting the data of the upper layer and the data of the lower layer can be respectively obtained according to the target access speed and the unit size of the data transmission of the upper layer and the lower layer, so as to effectively achieve the overall cooling.
Fig. 9 is a flowchart illustrating a data transmission method according to an exemplary embodiment of the invention.
Referring to fig. 9, in step S901, the memory control circuit unit 404 (or the memory management circuit 502) detects the temperature of the memory storage device 10.
In step S903, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the temperature of the memory storage device 10 is greater than a temperature threshold.
In step S905, if the temperature of the memory storage device is greater than the temperature threshold, the memory control circuit unit 404 (or the memory management circuit 502) writes the first data into the rewritable non-volatile memory module within the first delay time according to the delay rate counter value corresponding to a unit temperature.
However, the steps in fig. 9 have been described in detail above, and are not described again here. It is to be noted that the steps in fig. 9 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 9 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, in the data transmission method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention, when the temperature of the memory storage device reaches the temperature threshold, the transmission speed and the access speed of the data stream to be written into the rewritable non-volatile memory module from the host system are controlled and processed at the upper layer and the lower layer of the memory storage device, so as to reduce the bus bandwidth for processing the foreground data, and further avoid the system overheating phenomenon caused by fast and mass data writing during the operation of the memory storage device. In addition, the data transmission method of the exemplary embodiment can further control the access speed of the data stream generated by executing background work such as garbage collection programs and the like at the bottom layer of the memory storage device, so that the heat generation and the heat dissipation of the memory storage device can be ensured to really reach a stable state under the condition of considering the transmission speed and the access speed of foreground data and background data, and the data transmission rate and the data access efficiency are further improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (27)

1. A data transmission method is used for a memory storage device with a rewritable non-volatile memory module, and comprises the following steps:
detecting a temperature of the memory storage device;
determining whether the temperature of the memory storage device is greater than a temperature threshold;
if the temperature is larger than the temperature threshold, writing first data into the rewritable non-volatile memory module within a first delay time according to the delay velocity counter value corresponding to the unit temperature.
2. The data transmission method according to claim 1, further comprising:
setting the maximum allowable temperature value and the full-speed execution speed of the memory storage device; and
and calculating the delay speed count value according to the full-speed execution speed, the highest allowable temperature value and the temperature threshold value.
3. The data transmission method according to claim 2, wherein the step of calculating the delay speed count value according to the full-speed execution speed, the maximum allowable temperature value and the temperature threshold value comprises:
dividing the full speed execution speed into a plurality of delay speed halves according to a first temperature difference value between the highest allowable temperature value and the temperature threshold value, wherein a value of each delay speed half is equal to the delay speed count value.
4. The method of claim 1, wherein the rewritable non-volatile memory module comprises a plurality of physically erased cells, and the physically erased cells comprise at least idle physically erased cells,
wherein the step of writing the first data into the rewritable non-volatile memory module within the first delay time according to the value of the delay velocity meter corresponding to the unit temperature comprises:
according to a first unit size of data transmitted or accessed by the memory storage device, respectively forming a plurality of parts of first data into a plurality of first data groups, wherein the size of one first data group is equal to the first unit size; and
and according to the delay speed counting value, sequentially writing each first data group into the first idle physical erasing units extracted from the at least one idle physical erasing unit within a second delay time corresponding to each first data group.
5. The method according to claim 4, wherein the step of sequentially writing each first data group to the first idle physical erase units extracted from the at least one idle physical erase unit within the second delay time corresponding to each first data group according to the delay speed count value comprises:
obtaining a target access speed based on a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
calculating the second delay time corresponding to each first data set according to the target access speed and the size of each first data set, wherein the first unit size is equal to the size of one physical programming unit.
6. The method according to claim 1, wherein the step of writing the first data to the rewritable nonvolatile memory module within the first delay time further comprises:
the first data is received from the host system within a third delay time based on the delayed speed meter value.
7. The data transmission method according to claim 6, wherein the step of receiving the first data from the host system within the third delay time according to the delay speed count value comprises:
obtaining a target access speed based on a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value;
calculating a fourth delay time of the first data corresponding to each part according to the target access speed and the size of each first data; and
sequentially receiving the first data of each portion within the fourth delay time corresponding to the first data of each portion, wherein the size of the first data of one portion is smaller than the second unit size of one physical program cell.
8. The data transmission method according to claim 4, further comprising:
selecting a first physical erasing unit from the physical erasing units, wherein the first physical erasing unit does not comprise the first idle physical erasing unit and stores a plurality of data;
forming at least one valid datum in the data into a plurality of second data groups according to the first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one second data group is equal to the first unit size;
sequentially writing each second data group into a second idle physical erasing unit extracted from the at least one idle physical erasing unit within the second delay time corresponding to each second data group according to the delay speed counting value, wherein the second idle physical erasing unit is different from the first idle physical erasing unit; and
and erasing the first physical erasing unit.
9. The method according to claim 8, wherein the step of writing each second data set to the second idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each second data set in sequence according to the delay speed count value comprises:
obtaining a target access speed based on a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
calculating the second delay time corresponding to each second data set according to the target access speed and the size of each second data set, wherein the first unit size is equal to the size of one physical programming unit.
10. A memory control circuit unit for controlling a memory storage device having a rewritable non-volatile memory module, the memory control circuit unit comprising:
a host interface for coupling to a host system;
a memory interface for coupling to the rewritable non-volatile memory module; and
a memory management circuit coupled to the host interface and the memory interface and configured to detect a temperature of the memory storage device,
wherein the memory management circuitry is further to determine whether the temperature of the memory storage device is greater than a temperature threshold,
if the temperature is greater than the temperature threshold, the memory management circuit is further configured to issue a first write command sequence to instruct to write first data into the rewritable non-volatile memory module according to the delay speed counter value corresponding to the unit temperature within a first delay time.
11. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to set a maximum allowable temperature value and a full speed execution speed of the memory storage device,
the memory management circuit is further configured to calculate the delay speed count value according to the full-speed execution speed, the maximum allowable temperature value, and the temperature threshold.
12. The memory control circuit unit of claim 11, wherein, in the operation of calculating the delay speed count value according to the full-speed execution speed, the highest allowable temperature value, and the temperature threshold value,
the memory management circuit is further configured to divide the full speed execution speed into a plurality of delay speed halves according to a first temperature difference between the highest allowable temperature value and the temperature threshold, wherein a value of each delay speed half equals to the delay speed count value.
13. The memory control circuit unit of claim 10, wherein the rewritable non-volatile memory module comprises a plurality of physical erase units, and the physical erase units comprise at least one idle physical erase unit,
wherein the memory management circuit is further configured to respectively combine a plurality of portions of the first data into a plurality of first data groups according to a first unit size of the data transmitted or accessed by the memory storage device, wherein a size of one first data group is equal to the first unit size,
the memory management circuit is further configured to issue the first write command sequence to instruct each of the first data groups to be written into the first idle physical erase unit extracted from the at least one idle physical erase unit within a second delay time corresponding to each of the first data groups in sequence according to the delay speed count value.
14. The memory control circuit unit of claim 13, wherein the first write command sequence is issued to instruct each first data set to be written into the first idle physical erase unit extracted from the at least one idle physical erase unit during the second delay time corresponding to each first data set in sequence according to the delay speed count value,
the memory management circuit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
calculating the second delay time corresponding to each first data set according to the target access speed and the size of each first data set, wherein the first unit size is equal to the size of one physical programming unit.
15. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to receive the first data from the host system within a third delay time according to the latency counter value before issuing the first write command sequence to instruct writing of the first data to the rewritable non-volatile memory module within the first delay time.
16. The memory control circuit unit according to claim 15, wherein in an operation of receiving the first data from the host system within the third delay time according to the delay speed count value,
the memory management circuit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value;
the memory management circuit is further configured to calculate a fourth delay time corresponding to each portion of the first data according to the target access speed and the size of each first data; and
the memory management circuit is further configured to sequentially receive the first data of each portion within the fourth delay time corresponding to the first data of each portion, wherein a size of the first data of one portion is smaller than a second unit size of one physical program cell.
17. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to select a first physically erased cell from the physically erased cells, wherein the first physically erased cell does not include the first idle physically erased cell and stores a plurality of data,
wherein the memory management circuit is further configured to group at least one valid data of the data into a plurality of second data groups according to the first unit size of the data transferred or accessed by the memory storage device, wherein the size of one second data group is equal to the first unit size,
wherein the memory management circuit is further configured to issue a second write command sequence to instruct each second data set to be written into a second idle physical erase unit extracted from the at least one idle physical erase unit according to the delay speed count value sequentially within the second delay time corresponding to each second data set, wherein the second idle physical erase unit is different from the first idle physical erase unit,
the memory management circuit is further used for erasing the first physical erasing unit.
18. The memory control circuit unit of claim 17, wherein the second write command sequence is issued to instruct each second data set to be written into the second idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each second data set in sequence according to the delay speed count value,
the memory management circuit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
the memory management circuit is further configured to calculate the second delay time corresponding to each second data set according to the target access speed and the size of each second data set, wherein the first unit size is equal to the size of one physical program unit.
19. A memory storage device, comprising:
a connection interface unit for coupling to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used for detecting the temperature of the memory storage device,
wherein the memory control circuit unit is further configured to determine whether the temperature of the memory storage device is greater than a temperature threshold,
if the temperature is greater than the temperature threshold, the memory control circuit unit is further configured to issue a first write command sequence to instruct to write first data into the rewritable non-volatile memory module according to the delay speed counter value corresponding to the unit temperature within a first delay time.
20. The memory storage device of claim 19, wherein the memory control circuit unit is further configured to set a maximum allowable temperature value and a full speed execution speed of the memory storage device,
the memory control circuit unit is further configured to calculate the delay speed count value according to the full-speed execution speed, the maximum allowable temperature value, and the temperature threshold.
21. The memory storage device of claim 20, wherein in the operation of calculating the delay speed count value based on the full speed execution speed, the maximum allowable temperature value, and the temperature threshold value,
the memory control circuit unit is further configured to divide the full speed execution speed into a plurality of delay speed halves according to a first temperature difference between the highest allowable temperature value and the temperature threshold, wherein a value of each delay speed half equals to the delay speed count value.
22. The memory storage device of claim 19, wherein the rewritable non-volatile memory module comprises a plurality of physically erased cells, and the physically erased cells comprise at least one idle physically erased cell,
wherein the memory control circuit unit is further configured to respectively combine a plurality of portions of the first data into a plurality of first data sets according to a first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one first data set is equal to the first unit size,
the memory control circuit unit is further configured to issue the first write command sequence to instruct each of the first data groups to be written into the first idle physical erase unit extracted from the at least one idle physical erase unit within a second delay time corresponding to each of the first data groups in sequence according to the delay speed count value.
23. The memory storage device of claim 22, wherein the first write command sequence is issued to instruct writing of each first data set into the first idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each first data set in sequence according to the delay speed count value,
the memory control circuit unit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
the memory control circuit unit is further configured to calculate the second delay time corresponding to each first data set according to the target access speed and a size of each first data set, wherein the first unit size is equal to a size of a physical programming unit.
24. The memory storage device of claim 19, wherein during the operation of issuing the first write command sequence to indicate the first data is written to the rewritable non-volatile memory module before the first delay time, the memory control circuit unit is further configured to receive the first data from the host system within a third delay time according to the latency counter value.
25. The memory storage device according to claim 24, wherein in an operation of receiving the first data from the host system within the third delay time according to the delay speed count value,
the memory control circuit unit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value;
the memory control circuit unit is further configured to calculate a fourth delay time corresponding to each portion of the first data according to the target access speed and the size of each first data; and
the memory control circuit unit is further configured to sequentially receive the first data of each portion within the fourth delay time corresponding to the first data of each portion, wherein a size of the first data of one portion is smaller than a second unit size of one physical programming unit.
26. The memory storage device of claim 22, wherein the memory control circuit unit is further configured to select a first physically erased cell from the physically erased cells, wherein the first physically erased cell does not include the first idle physically erased cell and stores a plurality of data,
wherein the memory control circuit unit is further configured to group at least one valid data of the data into a plurality of second data groups according to the first unit size of the data transmitted or accessed by the memory storage device, wherein the size of one second data group is equal to the first unit size,
wherein the memory control circuit unit is further configured to issue a second write command sequence to instruct each second data set to be written into a second idle physical erase unit extracted from the at least one idle physical erase unit according to the delay speed count value sequentially within the second delay time corresponding to each second data set, wherein the second idle physical erase unit is different from the first idle physical erase unit,
the memory control circuit unit is further used for erasing the first physical erasing unit.
27. The memory storage device of claim 26, wherein the second write command sequence is issued to instruct each second data set to be written into the second idle physical erase unit extracted from the at least one idle physical erase unit within the second delay time corresponding to each second data set in sequence according to the delay speed count value,
the memory control circuit unit is further configured to obtain a target access speed according to a second temperature difference between the temperature of the memory storage device and the temperature threshold and the delay speed count value; and
the memory control circuit unit is further configured to calculate the second delay time corresponding to each second data set according to the target access speed and the size of each second data set, wherein the first unit size is equal to the size of one physical programming unit.
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