CN107204205B

CN107204205B - Memory management method, memory control circuit unit and memory storage device

Info

Publication number: CN107204205B
Application number: CN201610149646.5A
Authority: CN
Inventors: 陈国荣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-03-16
Filing date: 2016-03-16
Publication date: 2020-05-26
Anticipated expiration: 2036-03-16
Also published as: CN107204205A

Abstract

The invention provides a memory management method, a memory control circuit unit and a memory storage device. The method comprises the following steps: setting a read interference threshold value for each entity erasing unit; adjusting a reading interference threshold value of the first entity erasing unit according to the state information of the rewritable non-volatile memory module; and executing read interference prevention operation according to the read interference threshold value of the first entity erasing unit. Based on the above, the present invention provides a method for dynamically adjusting the read disturb threshold according to the erase count of the physical erase unit, so as to effectively reduce the probability of wear of the physical erase unit or the probability of occurrence of read disturb.

Description

Memory management method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a memory management method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, fast reading and writing speed, etc., it is most suitable for portable electronic products, such as notebook computers. A solid state disk is a memory storage device that uses a flash memory module as a storage medium. Therefore, the flash memory industry has become a relatively popular part of the electronics industry in recent years.

Generally, a rewritable nonvolatile memory module usually includes a plurality of physically erased cells, and each of the physically erased cells includes a plurality of physically programmed pages. In particular, the erase count of the physically erased cells in the rewritable non-volatile memory module is limited, for example, a physically erased cell will wear out after ten thousand erase operations. When a physically erased cell is worn out, it may cause erroneous bits when data is programmed (also called written) to the physically erased cell, and even worse, may cause adverse effects such as data loss or data failure.

In addition, when the data stored in one of the physical program cells in one of the physical erase cells is read for a plurality of times (for example, for hundreds of thousands to millions of times), the data stored in the physical program cell may also be subjected to erroneous bits or loss due to the applied read voltage, and even may cause erroneous bits or loss of data stored in other physical program cells in the same physical erase cell, which is commonly known as read-disturb by those skilled in the art.

The rewritable non-volatile memory module has the phenomenon that the entity erasing unit is abraded and read interference is caused along with the use of the rewritable non-volatile memory module, and the phenomena do not drive various manufacturers to develop various memory management methods, so that the abrasion probability of the entity erasing unit is effectively reduced or the occurrence probability of the read interference is inhibited.

Disclosure of Invention

The invention provides a memory management method, a memory control circuit unit and a memory storage device, which can effectively reduce the probability of abrasion of a solid erasing unit or inhibit the probability of occurrence of reading interference, thereby improving the life cycle and the reliability of a rewritable non-volatile memory module.

The invention provides a memory management method, which is used for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is provided with a plurality of entity erasing units, each entity erasing unit is provided with a plurality of entity programming units, and the memory management method comprises the following steps: setting a read interference threshold value for each entity erasing unit; adjusting a reading interference threshold value of the first entity erasing unit according to the state information of the rewritable non-volatile memory module; and executing read interference prevention operation according to the read interference threshold value of the first entity erasing unit.

In an exemplary embodiment of the invention, the step of adjusting the read disturb threshold of the first entity erasing unit according to the state information of the rewritable non-volatile memory module includes: recording the erase count of each physical erase unit; and adjusting the read interference threshold of the first physical erase unit from the first threshold to a second threshold when the erase count of the first physical erase unit is increased from the first count to a second count, wherein the second count is greater than the first count, and the second threshold is less than the first threshold.

In an exemplary embodiment of the present invention, the step of performing the read disturb prevention operation according to the read disturb threshold of the first physically erased cell includes: judging whether the reading times of a first entity programming unit corresponding to the first entity erasing unit is larger than a reading interference threshold value of the first entity erasing unit or not; and copying the data stored in the first physically erased cell to a second physically erased cell among the physically erased cells if the number of times of reading corresponding to the first physically programmed cell is greater than the read interference threshold of the first physically erased cell.

In an exemplary embodiment of the invention, the step of adjusting the read disturb threshold of the first entity erasing unit according to the state information of the rewritable non-volatile memory module includes: recording the erase count of each entity erasing unit, and adjusting the reading interference threshold value of the first entity erasing unit from a third threshold value to a fourth threshold value when the erase count of the first entity erasing unit is increased from the first count value to a second count value, wherein the second count value is larger than the first count value, and the fourth threshold value is larger than the third threshold value.

In an exemplary embodiment of the present invention, the step of performing the read disturb prevention operation according to the read disturb threshold of the first physically erased cell includes: reading a read data from a first physical programming unit of the first physical erasing unit; determining whether the number of error bits of read data read from the first physical programming unit is greater than a read disturb threshold of the first physical erase unit; if the number of error bits of the read data read from the first physically programmed cells is greater than the read disturb threshold of the first physically erased cells, the data stored in the first physically erased cells is copied to a second physically erased cell among the physically erased cells.

In an exemplary embodiment of the invention, the step of adjusting the read disturb threshold of the first entity erasing unit according to the state information of the rewritable non-volatile memory module includes: checking the temperature of the rewritable non-volatile memory module; and adjusting the reading interference threshold value of the first entity erasing unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the invention, the step of adjusting the read disturb threshold of the first physical erase unit according to the temperature of the rewritable non-volatile memory module comprises: when the temperature of the rewritable non-volatile memory module is increased from a first temperature value to a second temperature value, the read interference threshold value of the first entity erasing unit is adjusted from a fifth threshold value to a sixth threshold value, wherein the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for electrically connecting to a host system; the memory interface is electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and a memory management circuit electrically connected to the host interface and the memory interface. The memory management circuit is used for setting a reading interference threshold value for each entity erasing unit, adjusting the reading interference threshold value of the first entity erasing unit according to the state information of the rewritable non-volatile memory module, and executing reading interference prevention operation according to the reading interference threshold value of the first entity erasing unit.

In an exemplary embodiment of the invention, in the operation of adjusting the read disturb threshold of the first erase unit according to the status information of the rewritable non-volatile memory module, the memory management circuit is further configured to record an erase count of each erase unit, and when the erase count of the first erase unit is increased from the first count value to the second count value, the memory management circuit is further configured to adjust the read disturb threshold of the first erase unit from the first threshold value to the second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold of the first erase unit, the memory management circuit is further configured to determine whether the number of times of reading the first program cell corresponding to the first erase unit is greater than the read disturb threshold of the first erase unit, and if the number of times of reading the first program cell corresponding to the first erase unit is greater than the read disturb threshold of the first erase unit, the memory management circuit is further configured to copy the data stored in the first erase unit to a second erase unit among the erase units.

In an exemplary embodiment of the invention, in the operation of adjusting the read disturb threshold of the first erase unit according to the status information of the rewritable non-volatile memory module, the memory management circuit is further configured to record an erase count of each erase unit, and when the erase count of the first erase unit is increased from the first count value to the second count value, the memory management circuit is further configured to adjust the read disturb threshold of the first erase unit from the third threshold value to the fourth threshold value, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

In an exemplary embodiment of the invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold of the first physical erase cell, the memory management circuit is further configured to read a read datum from the first physical program cell of the first physical erase cell, the memory management circuit is further configured to determine whether the number of error bits of the read datum read from the first physical program cell is greater than the read disturb threshold of the first physical erase cell, and if the number of error bits of the read datum read from the first physical program cell is greater than the read disturb threshold of the first physical erase cell, the memory management circuit is further configured to copy the data stored in the first physical erase cell to a second physical erase cell among the physical erase cells.

In an exemplary embodiment of the invention, in the operation of adjusting the read disturb threshold of the first physical erase unit according to the status information of the rewritable non-volatile memory module, the memory management circuit is further configured to check a temperature of the rewritable non-volatile memory module, and the memory management circuit is further configured to adjust the read disturb threshold of the first physical erase unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the invention, in the operation of adjusting the read interference threshold of the first entity erasing unit according to the temperature of the rewritable non-volatile memory module, when the temperature of the rewritable non-volatile memory module is increased from the first temperature value to the second temperature value, the memory management circuit is further configured to adjust the read interference threshold of the first entity erasing unit from the fifth threshold value to the sixth threshold value, wherein the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

An exemplary embodiment of the present invention provides a memory storage device. It includes: the memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory comprises a plurality of entity erasing units, and each entity erasing unit in the entity erasing units comprises a plurality of entity programming units. The memory control circuit unit is used for setting a reading interference threshold value for each entity erasing unit, adjusting the reading interference threshold value of the first entity erasing unit according to state information of the rewritable non-volatile memory module, and executing reading interference prevention operation according to the reading interference threshold value of the first entity erasing unit.

In an exemplary embodiment of the invention, in the operation of adjusting the read disturb threshold of the first entity erasing unit according to the status information of the rewritable non-volatile memory module, the memory control circuit unit is further configured to record the erase count of each entity erasing unit, and when the erase count of the first entity erasing unit is increased from the first count value to the second count value, the memory control circuit unit is further configured to adjust the read disturb threshold of the first entity erasing unit from the first threshold value to the second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold of the first erase unit, the memory control circuit unit is further configured to determine whether the number of times of reading the first program cell corresponding to the first erase unit is greater than the read disturb threshold of the first erase unit, and if the number of times of reading the first program cell corresponding to the first erase unit is greater than the read disturb threshold of the first erase unit, the memory control circuit unit is further configured to copy the data stored in the first erase unit to a second erase unit among the erase units.

In an exemplary embodiment of the invention, in the operation of adjusting the read disturb threshold of the first physical erase unit according to the status information of the rewritable non-volatile memory module, the memory control circuit unit is further configured to record an erase count of each physical erase unit, and when the erase count of the first physical erase unit is increased from the first count value to the second count value, the memory control circuit unit is further configured to adjust the read disturb threshold of the first physical erase unit from the third threshold value to the fourth threshold value, wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

In an exemplary embodiment of the invention, in the operation of performing the read disturb prevention operation according to the read disturb threshold of the first physical erase unit, the memory control circuit unit is further configured to read a read datum from the first physical program unit of the first physical erase unit, the memory control circuit unit is further configured to determine whether the number of error bits of the read datum read from the first physical program unit is greater than the read disturb threshold of the first physical erase unit, and if the number of error bits of the read datum read from the first physical program unit is greater than the read disturb threshold of the first physical erase unit, the memory control circuit unit is further configured to copy the data stored in the first physical erase unit to a second physical erase unit among the physical erase units.

In an exemplary embodiment of the invention, in the operation of adjusting the read interference threshold of the first entity erasing unit according to the state information of the rewritable non-volatile memory module, the memory control circuit unit is further configured to check a temperature of the rewritable non-volatile memory module, and the memory control circuit unit is further configured to adjust the read interference threshold of the first entity erasing unit according to the temperature of the rewritable non-volatile memory module.

In an exemplary embodiment of the invention, in the operation of adjusting the read interference threshold of the first entity erasing unit according to the temperature of the rewritable non-volatile memory module, when the temperature of the rewritable non-volatile memory module is increased from the first temperature value to the second temperature value, the memory control circuit unit is further configured to adjust the read interference threshold of the first entity erasing unit from a fifth threshold to a sixth threshold, wherein the second temperature value is greater than the first temperature value, and the sixth threshold is greater than the fifth threshold.

Based on the above, the present invention provides a method for dynamically adjusting the read disturb threshold according to the erase count of the physical erase unit, so as to effectively reduce the probability of wear of the physical erase unit or the probability of occurrence of read disturb.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an example embodiment.

FIGS. 6 and 7 illustrate exemplary diagrams of managing physical erase units according to one exemplary embodiment;

FIG. 8 is a flow chart illustrating a memory management method according to an example embodiment;

FIG. 9 is a diagram illustrating adjustment of read disturb threshold based on erase count according to a first exemplary embodiment;

FIG. 10 is a flowchart illustrating adjusting read disturb threshold based on erase counts according to a first exemplary embodiment;

FIG. 11 is a flowchart illustrating performing a read disturb prevention operation according to a first exemplary embodiment;

FIG. 12 is a diagram illustrating adjustment of read disturb threshold based on erase count according to a second exemplary embodiment;

FIG. 13 is a flowchart illustrating adjusting read disturb threshold based on erase counts according to a second exemplary embodiment;

FIG. 14 is a flowchart illustrating performing a read disturb prevention operation according to a second exemplary embodiment;

15A, 15B, and 15C are schematic diagrams illustrating adjusting a read disturb threshold based on a temperature of a rewritable non-volatile memory module according to a third exemplary embodiment;

FIG. 16 is a flowchart illustrating adjusting a read disturb threshold based on temperature according to a third exemplary embodiment.

Description of reference numerals:

10: a memory storage device;

11: a host system;

12: input/output (I/O) devices;

110: a system bus;

111: a processor;

112: random Access Memory (RAM);

113: read Only Memory (ROM);

114: a data transmission interface;

20: a main board;

204: a wireless memory storage device;

205: a global positioning system module;

206: a network interface card;

207: a wireless transmission device;

208: a keyboard;

209: a screen;

210: a horn;

30: a memory storage device;

31: a host system;

32: an SD card;

33: a CF card;

34: an embedded storage device;

341: an embedded multimedia card;

342: an embedded multi-chip package storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

410(0) to 410 (N): a physical erase unit;

502: a memory management circuit;

504: a host interface;

506: a memory interface;

508: a buffer memory;

510: a power management circuit;

512: an error checking and correcting circuit;

514: a temperature sensing circuit;

602: a data area;

604: an idle area;

606: a system area;

608: a substitution region;

LBA (0) to LBA (h): a logical address;

LZ (0) to LZ (M): a logical area;

s801: setting a reading interference threshold value for each entity erasing unit;

s803: adjusting a reading interference threshold value of the first entity erasing unit according to the state information of the rewritable non-volatile memory module;

s805: executing a step of preventing read disturb operation according to the read disturb threshold of the first entity erasing unit;

s1001: performing an erase operation on the first physically erased cell;

s1003: updating the erase count of the first physical erase unit;

s1005: adjusting the reading interference threshold value of the first entity erasing unit from the first threshold value to a second threshold value when the erasing count of the first entity erasing unit is increased from the first count value to a second count value, wherein the second count value is larger than the first count value, and the second threshold value is smaller than the first threshold value;

s1101: reading a first entity programming unit of the first entity erasing unit;

s1103: updating the read times corresponding to the first physical programming unit;

s1105: judging whether the reading times of the first entity programming unit corresponding to the first entity erasing unit is larger than the reading interference threshold value of the first entity erasing unit;

s1107: copying the data stored in the first physically erased cell to a second physically erased cell among the physically erased cells;

s1301: performing an erase operation on the first physically erased cell;

s1303: updating an erase count corresponding to the first physically erased cell;

s1305: adjusting the reading interference threshold value of the first entity erasing unit from a third threshold value to a fourth threshold value when the erasing count of the first entity erasing unit is increased from the first counting value to a second counting value, wherein the second counting value is larger than the first counting value, and the fourth threshold value is larger than the third threshold value;

s1401: reading a read data from a first physical programming cell of the first physical erase cell;

s1403: judging whether the number of error bits of read data read from the physical programming unit is larger than a read interference threshold value of the first physical erasing unit;

s1405: copying the data stored in the first physically erased cell to a second physically erased cell among the physically erased cells;

s1601: checking the temperature of the rewritable non-volatile memory module;

s1603: and adjusting the reading interference threshold value of the first entity erasing unit from a fifth threshold value to a sixth threshold value when the temperature of the rewritable non-volatile memory module is increased from the first temperature value to the second temperature value, wherein the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

Fig. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 over system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be electrically connected to the memory storage device 10 through the data transmission interface 114 by wire or wirelessly. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless fidelity (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a low power Bluetooth (low energy) memory Storage device (e.g., iBeacon) memory Storage device based on various wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded Multi media cards (eMMC) 341 and/or embedded Multi Chip Package memory devices (eMCP) 342, which electrically connect the memory module directly to the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compatible with Serial Advanced Technology Attachment (SATA) standards. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Embedded, Multimedia Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-chip package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or software, and performing operations such as writing, reading and erasing data in the rewritable non-volatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 has physically erasable units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each of the plurality of physical erase units has a plurality of physical program units, wherein the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell generally includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program cell includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable non-volatile memory module 406 is a multi-Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 data bits in one memory Cell). However, the invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e. a flash memory module capable of storing 2 data bits in one memory Cell) or other memory modules with the same characteristics.

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer 508, a power management circuit 510, an error checking and correcting circuit 512, and a temperature sensing circuit 514.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in software. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIGS. 6 and 7 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment.

It should be understood that, when describing the operation of the physically erasable units of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erasable units by the terms "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable non-volatile memory module are not changed, but the physical erase units of the rewritable non-volatile memory module are logically operated.

Referring to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the physical erase units in the data area 602 are regarded as physical erase units with stored data, and the physical erase units in the idle area 604 are used to replace the physical erase units in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 writes the data by extracting the physical erase unit from the idle region 604 to replace the physical erase unit in the data region 602.

The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable non-volatile memory module, the number of erase units of the rewritable non-volatile memory module, the number of programmed units of each erase unit, and so on.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of memory storage device 10, the grouping of physically erased cells associated with data area 602, idle area 604, system area 606, and replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.

Referring to fig. 7, the memory control circuit unit 404 (or the memory management circuit 502) allocates logical addresses LBA (0) -LBA (h) to map the physically erased units in the data area 602, where each logical address has a plurality of logical units to map the physically programmed units of the corresponding physically erased units. Moreover, when the host system 11 intends to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase unit from the idle area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. Moreover, when the physical erase unit as the active physical erase unit is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract the empty physical erase unit from the idle area 504 as the active physical erase unit to continue writing the update data corresponding to the write command from the host system 1000. In addition, when the number of the available physical erase units in the idle area 604 is smaller than the predetermined value, the memory control circuit unit 404 (or the memory management circuit 502) performs a valid data merging procedure (also called a garbage collection procedure) to arrange the valid data in the data area 602, so as to re-associate the physical erase units in the data area 602 that do not store valid data with the idle area 604.

In order to identify the physical erase cell in which the data of each logical address is stored, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the mapping between the logical address and the physical erase cell. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical address-physical address mapping table in the rewritable non-volatile memory module 406 to record the physically erased cells mapped by each logical address. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table into the buffer memory 508 for maintenance, and writes or reads data according to the logical address-physical address mapping table.

It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical address, the mapping table of logical address-physical address corresponding to the logical area to which the logical address belongs is loaded into the buffer memory 508 for updating.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in the form of program codes in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment of the present invention, the control instruction of the memory management circuit 502 can also be implemented in a hardware manner. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable non-volatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable non-volatile memory module 406 so as to write data into the rewritable non-volatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable non-volatile memory module 406 so as to read data from the rewritable non-volatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable non-volatile memory module 406 so as to erase data from the rewritable non-volatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406.

Referring to fig. 5 again, the host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing the commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transfer standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable non-volatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. For example, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the corresponding error checking and correcting code is simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting procedure on the read data according to the error checking and correcting code.

The temperature sensing circuit 514 is electrically connected to the memory management circuit 502 and is used for checking the temperature of the rewritable non-volatile memory module 406.

It should be noted that, assuming that when the data stored in the first physical programming unit (also referred to as the physical programming unit 410(0) -1) of the physical erasing units 410(0) is read by the memory control circuit unit 404 (or the memory management circuit 502) for multiple times (for example, hundreds of thousands of times of reading), since the memory control circuit unit 404 (or the memory management circuit 502) applies the read voltage to the memory cells in the physical programming units 410(0) -1 during each reading operation, the data stored in the physical programming units 410(0) -1 is likely to generate error bits or loss due to the repeated application of the read voltage to the memory cells, and even cause error bits or loss of the data stored in other physical programming units in the physical erasing units 410(0), this creates a problem of "read disturb".

Generally, it is able to avoid data errors or data loss caused by read disturb by determining whether the "read count" is greater than a read disturb value. Specifically, in the example where the memory control circuit unit 404 (or the memory management circuit 502) repeatedly reads the physical programming unit 410(0) -1, since the physical programming unit 410(0) -1 may generate error bits or data loss in the physical erasing unit 410(0) after being read for multiple times, the memory control circuit unit 404 (or the memory management circuit 502) may determine whether the number of times (i.e., the number of times of reading) that the data stored in the physical programming unit 410(0) -1 is read is greater than the read disturb threshold value, so as to determine whether to move the data stored in the physical erasing unit 410 (0). If the number of times of reading the data stored in the physical programming unit 410(0) -1 is greater than the read disturb threshold, the memory control circuit unit 404 (or the memory management circuit 502) moves the data in the physical programming unit 410(0) -1 to, for example, other idle physical programming units, so as to prevent the data stored in the physical programming unit 410(0) -1 from being repeatedly read and causing excessive error bits or data loss.

In addition, data errors or loss caused by read interference can be avoided by judging whether the 'error bit number' of the read data is larger than a read interference value or not. Specifically, when the memory control circuit unit 404 (or the memory management circuit 502) reads a read data from the physical programming unit 410(0) -1 of the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) simultaneously reads the error checking and correcting code corresponding to the read data, and performs the error checking and correcting procedure on the read data according to the error checking and correcting code by the error checking and correcting circuit 512, thereby calculating the number of error bits for the physical programming unit 410(0) -1 according to the number of error bits of the data stored by the physical programming unit 410(0) -1. Thereafter, the memory control circuit unit 404 (or the memory management circuit 502) can determine whether the number of error bits of the read data read from (0) -1 of the physical programming unit 410 is greater than the read disturb threshold. If the number of error bits of the read data read from the physical programming unit 410(0) -1 is greater than the read disturb threshold, the memory control circuit unit 404 (or the memory management circuit 502) moves the data in the physical programming unit 410(0) -1 to, for example, other idle physical programming units, so as to prevent the data stored in the physical programming unit 410(0) -1 from being repeatedly read and causing more error bits or data loss.

However, it should be noted that in the methods of the prior art that use "read times" or "number of error bits" to avoid read disturb, "read disturb threshold" is not dynamically changed, and none of these methods takes into account the wear of the physically erased cells. It is assumed that when the physical erase unit 410(0) is worn out, the memory control circuit unit 404 (or the memory management circuit 502) will generate too many error bits when programming data to the physical program unit 410(0) -1 in the physical erase unit 410(0), and even worse, data will be lost or data cannot be stored.

Therefore, the present invention provides a memory management method, which dynamically adjusts the "read disturb threshold" corresponding to the physical erase unit according to the status information of the rewritable non-volatile memory module 406, so as to effectively reduce the probability of wear of the physical erase unit or suppress the occurrence of read disturb.

FIG. 8 is a flowchart illustrating a memory management method according to an example embodiment.

Referring to FIG. 8, in step S801, the memory control circuit unit 404 (or the memory management circuit 502) sets a read disturb threshold for each of the physical erase units 410(0) -410 (N).

Taking the physical erase unit 410(0) as an example, in an exemplary embodiment of the invention, the read disturb threshold corresponding to the physical erase unit 410(0) may be used to determine whether the "read times" of the data stored in one of the physical program units in the physical erase unit 410(0) is greater than a specific value, so as to determine whether to move the data in the physical erase unit 410 (0).

In another exemplary embodiment of the present invention, the read disturb threshold corresponding to the physical erase unit 410(0) can be used to determine whether the "number of error bits" of the read data read from one of the physical program cells in the physical erase unit 410(0) is greater than a certain value, so as to determine whether to move the data in the physical erase unit 410 (0).

Next, in step S803, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the first erase unit according to the status information of the rewritable nonvolatile memory module 406. In step S805, the memory control circuit unit 404 (or the memory management circuit 502) performs a read disturb prevention operation according to the read disturb threshold of the first physically erased cell.

In an exemplary embodiment, the status information of the rewritable nonvolatile memory module 406 can be the erase count of each of the physically erased cells 410(0) -410 (N) in the rewritable nonvolatile memory module 406. For example, the memory control circuit unit 404 (or the memory management circuit 502) records the erase count of each of the physical erase units 410(0) -410 (N). Specifically, in the exemplary embodiment, memory control circuitry 404 (or memory management circuitry 502) stores an erase count table in rewritable non-volatile memory module 406 to record erase counts of each of the physically erased cells 410(0) -410 (N), and memory control circuitry 404 (or memory management circuitry 502) loads the erase count table into buffer 508 for maintenance. The memory control circuit unit 404 (or the memory management circuit 502) may record (or update) the erase count of the physically erased unit to which the erase operation is performed in the erase count table each time the erase operation is performed on one of the physically erased units 410(0) to 410 (N). Taking the physical erase unit 410(0) as an example, assuming that the memory control circuit unit 404 (or the memory management circuit 502) performs one erase operation on the physical erase unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) may add one to the erase count value corresponding to the physical erase unit 410(0) in the erase count table.

Then, the memory control circuit unit 404 (or the memory management circuit 502) dynamically adjusts the read disturb threshold corresponding to the physical erase unit 410(0) according to the erase count corresponding to the physical erase unit 410(0) in the erase count table, so as to change the timing for moving the data in the physical erase unit 410 (0). The operation of preventing read disturb can be to move the data in the erase block 410(0), i.e. to copy the data in the erase block 410(0) to other erase blocks in the erase blocks 410(0) -410 (N).

In addition, in another exemplary embodiment, the state information of the rewritable nonvolatile memory module 406 may be a temperature of the rewritable nonvolatile memory module 406. For example, the memory controller 404 (or the memory management circuit 502) checks the temperature of the rewritable nonvolatile memory module 406 through the temperature sensing circuit 514, and adjusts the read disturb threshold of the erase units 410(0) -410 (N) according to the temperature of the rewritable nonvolatile memory module 406. Thereby changing the timing of moving the data in the physical erase unit 410 (0). The operation of preventing read disturb can be to move the data in the erase block 410(0), i.e. to copy the data in the erase block 410(0) to other erase blocks in the erase blocks 410(0) -410 (N).

By the above method, the probability of wear of the physical erase units 410(0) -410 (N) can be reduced or the probability of read disturb can be suppressed. Several exemplary embodiments are provided below for a more detailed description.

First exemplary embodiment

In the first exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) records the erase counts of each of the physical erase units 410(0) -410 (N) in the erase count table, and dynamically adjusts the read disturb threshold corresponding to the physical erase unit 410(0) according to the erase counts corresponding to the physical erase units 410(0) in the erase count table. In particular, in the first exemplary embodiment of the invention, the memory control circuit unit 404 (or the memory management circuit 502) determines whether to perform the read disturb prevention operation by determining whether the "read times" of the data of the physical programming unit 410(0) -1 of the physical erase unit 410(0) is greater than the read disturb threshold. Based on the fact that the wear of the physically erased cells due to the excessive number of erasures, it is assumed that when the physically erased cell 410(0) is worn out, it may cause an error bit to be generated when the data is programmed to the physically programmed cell 410(0) -1. At this time, if only the fixed read disturb threshold is used to avoid the read disturb of the physical erase unit 410(0), in this case, when the memory control circuit unit 404 (or the memory management circuit 502) repeatedly reads the data of the physical program unit 410(0) -1 in the worn physical erase unit 410(0), the physical program unit 410(0) -1 is likely to generate too many error bits due to the wear of the physical erase unit 410(0) and the repeated read by the memory control circuit unit 404 (or the memory management circuit 502) under the condition that the read times of the physical program unit 410(0) -1 are not greater than the read disturb threshold. That is, in the case that the number of times of reading the physical programming unit 410(0) -1 is not greater than the read disturb threshold, the physical programming unit 410(0) -1 may generate error bits due to wear of the physical erase unit 410(0), and the additional error bits are repeatedly read by the physical programming unit 410(0) -1, resulting in excessive error bits in the data stored in the physical programming unit 410(0) -1.

Therefore, in the first exemplary embodiment of the invention, it is assumed that when the number of times the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically lowers the threshold of the read disturb number corresponding to the physical erase unit 410(0), so as to prevent the data in the physical program unit 410(0) -1 from generating too many error bits.

Specifically, it is assumed that when the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the physically erased cell 410(0) (hereinafter, referred to as a first physically erased cell), the memory control circuit unit 404 (or the memory management circuit 502) correspondingly increments the erase count of the first physically erased cell by one. Then, when the erase count of the physical erase unit 410(0) is increased from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the physical erase unit 410(0) from the first threshold value to the second threshold value, wherein the second count value is greater than the first count value, and the second threshold value is smaller than the first threshold value.

For example, FIG. 9 is a diagram illustrating adjusting a read disturb threshold based on erase counts according to a first exemplary embodiment. Referring to FIG. 9, in one state, it is assumed that the erase count corresponding to the entity-erased cell 410(0) is recorded as 7000 (i.e., the first count value), and the read disturb threshold corresponding to the entity-erased cell 410(0) is set as 90000 (i.e., the first threshold value). Assuming that after a period of time, when the erase count of memory control circuit unit 404 (or memory management circuit 502) corresponding to physical erase unit 410(0) is increased to 8000 (i.e., the second count) due to 1000 erase operations performed on physical erase unit 410, memory control circuit unit 404 (or memory management circuit 502) adjusts the read disturb threshold corresponding to physical erase unit 410(0) from 7000 to 9000 (i.e., the second threshold) at the same time when the erase count of physical erase unit 410(0) is increased to 8000, so that when the number of times physical erase unit 410(0) is erased is increased, memory control circuit unit 404 (or memory management circuit 502) dynamically decreases the read disturb threshold corresponding to physical erase unit 410 (0). It should be noted, however, that the present invention is not limited to the values of the erase counts and the read disturb thresholds, and the optimal correspondence between the erase counts and the read disturb thresholds can be determined by repeated experiments for different types of memory storage devices.

In addition, the memory control circuit unit 404 (or the memory management circuit 502) records a read count for each physical program unit according to the number of times each physical program unit in the physical erase units 410(0) to 410(N) is read.

For example, the memory control circuit unit 404 (or the memory management circuit 502) may record the read count corresponding to the physical programming unit 410(0) -1 in the physical erase unit 410(0) in the read count table according to the number of times the physical programming unit 410(0) -1 (i.e., the first physical programming unit) is read. In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a read count table in the rewritable non-volatile memory module 406 to record the read count of each of the physically erased cells, and the memory control circuit unit 404 (or the memory management circuit 502) loads the read count table into the buffer memory 508 for maintenance.

Then, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the read times of the physical programming unit 410(0) -1 corresponding to the physical erasing unit 410(0) are greater than the read disturb threshold of the physical erasing unit 410 (0). If the number of reads corresponding to the entity programming unit 410(0) -1 is greater than the read disturb threshold of the entity erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) copies the data stored in the entity erasing unit 410(0) to one entity erasing unit among the entity erasing units 410(0) -410 (N).

In detail, since the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read/erase count corresponding to the physical erase unit 410(0) to 8000, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold corresponding to the physical erase unit 410(0) to 9000, assuming that the memory control circuit unit 404 (or the memory management circuit 502) continuously performs the read operation on the physical programming unit 410(0) -1 of the physical erase unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) may copy the data stored in the physical erase unit 410(0) to the physical erase unit 410(F) in the idle region 604 after performing the 9001 th read operation on the physical programming unit 410(0) -1, the erase operation is performed on the physical erase unit 410(0), and then the physical erase unit 410(0) is associated with the idle region 604 and the physical erase unit 410(F) is associated with the data region 602. It should be noted, however, that the present invention is not limited to the manner of transferring the data in the first physically erased cells. In an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) may copy the data stored in the physical programming unit 410(0) -1 to, for example, the buffer memory 508 after the 9001 th read operation is performed on the physical programming unit 410(0) -1, and write the data originally stored in the physical programming unit 410(0) -1 back to the physical erasing unit 410(0) from the buffer memory 508 after the erase operation is performed on the physical erasing unit 410 (0).

In this way, when the number of times the erase operation is performed on the physical erase unit 410(0) is increased, the memory control circuit unit 404 (or the memory management circuit 502) dynamically lowers the read disturb threshold corresponding to the erase operation 410(0) to prevent the physical program unit 410(0) -1 from generating too many error bits due to the wear-out of the physical erase unit 410(0) and the additional error bits read by the physical program unit 410(0) -1 repeatedly when the read count of the physical program unit 410(0) -1 is not greater than the read disturb threshold.

FIG. 10 is a flowchart illustrating adjusting read disturb threshold based on erase counts according to a first exemplary embodiment.

Referring to fig. 10, in step S1001, the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the first physically erased cell. Thereafter, in step S1003, the memory control circuit unit 404 (or the memory management circuit 502) updates the erase count of the first physically erased cell. Finally, in step S1005, when the erase count of the first physical erase unit is increased from the first count value to a second count value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the first physical erase unit from the first threshold to a second threshold, wherein the second count value is greater than the first count value, and the second threshold is smaller than the first threshold.

FIG. 11 is a flowchart illustrating a read disturb preventive operation performed according to the first exemplary embodiment.

Referring to fig. 11, in step S1101, the memory control circuit unit 404 (or the memory management circuit 502) performs a read operation on the first physically programmed cell of the first physically erased cell. Next, in step S1103, the memory control circuit unit 404 (or the memory management circuit 502) updates the read times corresponding to the first physical program unit. Then, in step S1105, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the number of times of reading the first physical program cell corresponding to the first physical erase cell is greater than the read disturb threshold of the first physical erase cell. If the number of times of reading the first physical program cell corresponding to the first physical erase cell is not greater than the read disturb threshold of the first physical erase cell, step S1101 is executed. If the number of times of reading the first physical program cell corresponding to the first physical erase cell is greater than the read disturb threshold of the first physical erase cell, in step S1107, the memory control circuit unit 404 (or the memory management circuit 502) copies the data stored in the first physical erase cell to the second physical erase cell among the physical erase cells.

Therefore, in the first exemplary embodiment of the present invention, when the number of times a physically erased cell is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically adjusts the read disturb threshold corresponding to the physically erased cell to be low, so as to avoid excessive error bits or data loss in the case that the read count of one of the physically erased cells is not greater than the read disturb threshold.

Second exemplary embodiment

In the second exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) records the erase counts of each of the physical erase units 410(0) -410 (N) in the erase count table, and dynamically adjusts the read disturb threshold corresponding to the physical erase unit 410(0) according to the erase counts in the erase count table. In particular, in the second exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) determines whether to perform the read disturb prevention operation by determining whether the "number of error bits" of the read data read in the physical programming unit 410(0) -1 of the physical erase unit 410(0) is greater than the read disturb threshold. Based on the fact that the wear of the physically erased cells due to the excessive number of erasures, it is assumed that when the physically erased cell 410(0) is worn out, it may cause an error bit to be generated when the data is programmed to the physically programmed cell 410(0) -1. If only a fixed read disturb threshold is used to avoid the read disturb of the physical erase cell 410(0), more error bits than the number of error bits may be generated when writing data into the physical program cell 410(0) -1 due to the wear of the physical erase cell 410 (0). At this time, the memory control circuit unit 404 (or the memory management circuit 502) moves the data in the physical erase unit 410(0) and performs an erase operation on the physical program unit 410 (0). In this case, if the memory control circuit unit 404 (or the memory management circuit 502) repeatedly writes one of the worn-out physical erase units 410(0), the physical program unit 410(0) may be repeatedly erased due to the number of error bits of the written data being greater than the error bit count threshold value, thereby increasing the wear of the physical program unit 410 (0).

Therefore, in the second exemplary embodiment of the present invention, it is assumed that when the number of times the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physical erase unit 410(0), so as to avoid the physical erase unit 410(0) from being subjected to excessive erase operations and causing more serious wear.

Specifically, it is assumed that when the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the physically erased cell 410(0) (hereinafter, referred to as a first physically erased cell), the memory control circuit unit 404 (or the memory management circuit 502) correspondingly increments the erase count of the first physically erased cell by one. Then, when the erase count of the physical erase unit 410(0) is increased from the first count value to the second count value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the physical erase unit 410(0) from the third threshold to a fourth threshold, wherein the second count value is greater than the first count value, and the fourth threshold is greater than the third threshold.

For example, FIG. 12 is a diagram illustrating adjusting read disturb threshold values based on erase counts according to a second exemplary embodiment. Referring to FIG. 12, in one state, it is assumed that the erase count corresponding to the physical erase unit 410(0) is recorded as 7000 (i.e., the first count value), and the read disturb threshold corresponding to the physical erase unit 410(0) is set to 90 (i.e., the third threshold value). Assuming that after a period of time, when the erase count of the memory control circuit unit 404 (or the memory management circuit 502) corresponding to the physical erase unit 410(0) is increased to 8000 (i.e., the second count) due to the erase operation performed on the physical erase unit 410 for 1000 times, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold corresponding to the physical erase unit 410(0) from 90 to 100 (i.e., the fourth threshold), for example, so that when the number of times the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physical erase unit 410 (0). It should be noted, however, that the present invention is not limited to the values of the erase counts and the read disturb thresholds, and the optimal correspondence between the erase counts and the read disturb thresholds can be determined by repeated experiments for different types of memory storage devices.

In addition, the memory control circuit unit 404 (or the memory management circuit 502) calculates an error bit count for the first physically programmed cell according to the number of error bits of the read data read by the first physically programmed cell of the first physically erased cells.

For example, when the memory control circuit unit 404 (or the memory management circuit 502) reads data from the physical programming unit 410(0) -1 (i.e., the first physical programming unit) of the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) simultaneously reads the error checking and correcting code corresponding to the data, and performs the error checking and correcting procedure on the read data according to the error checking and correcting code by the error checking and correcting circuit 512, thereby calculating the error bit count for the physical programming unit 410(0) -1 according to the error bit number of the data stored by the physical programming unit 410(0) -1. However, the invention is not limited to the timing of calculating the error bit count, in an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) may also perform the error checking and correcting process by the error checking and correcting circuit 512 after writing the data into the physical programming unit 410(0) -1, and further calculate the error bit count for the physical programming unit 410(0) -1 according to the number of error bits of the data stored in the physical programming unit 410(0) -1.

Thereafter, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the number of error bits of the read data read from the physical programming unit 410(0) -1 is greater than the read disturb threshold of the physical erasing unit 410 (0). If the number of error bits of the read data read from the physical programming unit 410(0) is greater than the read disturb threshold of the physical erasing unit 410(0), the memory control circuit unit 404 (or the memory management circuit 502) copies the data stored in the physical erasing unit 410(0) to one of the physical erasing units 410(0) -410 (N).

In detail, since the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read/erase count corresponding to the physical erase unit 410(0) to 8000, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold corresponding to the physical erase unit 410(0) to 100, assuming that when the memory control circuit unit 404 (or the memory management circuit 502) reads data from the physical program unit 410(0) -1, the memory control circuit unit 404 (or the memory management circuit 502) will simultaneously read the corresponding error checking and correcting codes, and the error checking and correcting circuit 512 will perform the error checking and correcting procedure on the read data according to the error checking and correcting codes, and further according to the number of error bits of the data stored in the physical program unit 410(0) -1, the error bit count is calculated for the physical programming unit 410(0) -1. Assuming that the value of the error bit count of the physical programming unit 410(0) -1 is 101, the memory control circuit unit 404 (or the memory management circuit 502) may copy the data stored in the physical erasing unit 410(0) to the physical erasing unit 410(F) in the idle region 604 and erase the physical erasing unit 410(0) after performing the read operation on the physical programming unit 410(0) -1, and then associate the physical erasing unit 410(0) to the idle region 604 and associate the physical erasing unit 410(F) to the data region 602. It should be noted, however, that the present invention is not limited to the manner of transferring the data in the first physically erased cells. In an exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) may copy the data stored in the physical programming unit 410(0) -1 to, for example, the buffer memory 508 after performing the 101 st read operation on the physical programming unit 410(0) -1, and write the data originally stored in the physical programming unit 410(0) -1 back to the physical erasing unit 410(0) from the buffer memory 508 after performing the erase operation on the physical erasing unit 410 (0).

In this way, when the number of times the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physical erase unit 410(0), so as to avoid the problem that the physical erase unit 410(0) is frequently erased due to the wear of the physical erase unit 410(0) causing the number of error bits greater than the read disturb threshold during data writing. Based on the second exemplary embodiment of the present invention, the wear of the physically erased cell 410(0) can be effectively reduced.

FIG. 13 is a flowchart illustrating adjusting read disturb threshold based on erase counts according to a second exemplary embodiment.

Referring to fig. 13, in step S1301, the memory control circuit unit 404 (or the memory management circuit 502) performs an erase operation on the first physically erased cell. Thereafter, in step S1303, the memory control circuit unit 404 (or the memory management circuit 502) updates the erase count corresponding to the first physically erased cell. Finally, in step S1305, when the erase count of the first physically erased cell is increased from the first count value to a second count value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the first physically erased cell from a third threshold value to a fourth threshold value, where the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

FIG. 14 is a flowchart illustrating performing a read disturb prevention operation according to a second exemplary embodiment.

Referring to fig. 14, in step S1401, the memory control circuit unit 404 (or the memory management circuit 502) reads a read datum from the first physical programming unit of the first physical erasing unit. Next, in step S1403, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the number of error bits of the read data read from the physically programmed cell is greater than the read disturb threshold of the first physically erased cell. If the number of error bits of the read data read from the physically programmed cell is not greater than the read disturb threshold of the first physically erased cell, step S1401 is executed. If the number of error bits of the read data read from the physically programmed cells is greater than the read disturb threshold of the first physically erased cells, in step S1405, the memory control circuit unit 404 (or the memory management circuit 502) copies the data stored in the first physically erased cells to the second physically erased cells among the physically erased cells.

Therefore, in the second exemplary embodiment of the present invention, it is assumed that when the number of times a physically erased cell is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physically erased cell, so as to avoid the more serious wear caused by the excessively performed erase operation of the physically erased cell.

Third exemplary embodiment

In the third exemplary embodiment of the invention, the memory control circuit unit 404 (or the memory management circuit 502) checks the temperature of the rewritable non-volatile memory module 406 by the temperature sensing circuit 514, and adjusts the read disturb threshold of the physical erase units 410(0) -410 (N) according to the temperature of the rewritable non-volatile memory module 406.

For example, the third embodiment of the present invention adjusts the read disturb threshold by determining the "number of error bits" and the temperature of the rewritable nonvolatile memory module 406. Taking the physical erase unit 410(0) and the physical program unit 410(0) -1 as examples, the memory control circuit unit 404 (or the memory management circuit 502) can determine whether to perform the read disturb prevention operation by determining whether the "number of error bits" of the read data read in the physical program unit 410(0) -1 of the physical erase unit 410(0) is greater than the read disturb threshold. It is assumed that when the number of times that the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physical erase unit 410(0) to avoid more serious wear caused by excessive erase operations performed on the physical erase unit 410 (0). However, it should be noted that when the temperature of the rewritable nonvolatile memory module 406 increases, the memory control circuit unit 404 (or the memory management circuit 502) is more likely to generate an error bit when writing data into the physical programming unit of the rewritable nonvolatile memory module 406. Therefore, if the memory control circuit unit 404 (or the memory management circuit 502) writes the physical programming unit 410(0) -1 in the high temperature physical erasing unit 410(0) again, the memory control circuit unit 404 (or the memory management circuit 502) may check that the physical programming unit 410(0) -1 has generated excessive error bits, and the memory control circuit unit 404 (or the memory management circuit 502) moves the data in the physical erasing unit 410(0) and performs the erasing operation on the physical programming unit 410 (0). In this case, if the memory control circuit unit 404 (or the memory management circuit 502) repeatedly writes one of the physically erased units 410(0) which is at a high temperature and is worn out, the physically erased units 410(0) may be repeatedly erased due to the number of error bits of the written data being greater than the error bit count threshold value, thereby increasing the wear of the physically erased units 410 (0).

Therefore, in the third exemplary embodiment of the invention, the memory control circuit unit 404 (or the memory management circuit 502) checks the temperature of the rewritable nonvolatile memory module 406 through the temperature sensing circuit 514, and adjusts the read disturb threshold of the first physically erased cell according to the temperature of the rewritable nonvolatile memory module 406. In particular, when the temperature of the rewritable non-volatile memory module 406 increases from the first temperature value to the second temperature value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the first erase unit from a fifth threshold to a sixth threshold, wherein the second temperature value is greater than the first temperature value, and the sixth threshold is greater than the fifth threshold.

In detail, fig. 15A, 15B and 15C are schematic diagrams illustrating adjusting the read disturb threshold according to the temperature of the rewritable non-volatile memory module according to the third exemplary embodiment.

Referring to fig. 15A, 15B and 15C, it is assumed that in the state of fig. 15A, the temperature of the current rewritable non-volatile memory module 406 is 60 ℃, the erase count corresponding to the physical erase unit 410(0) is recorded as 7000 (i.e., the first count), and the read disturb threshold corresponding to the physical erase unit 410(0) is set as 90 (i.e., the third threshold). Assuming that after a period of time, when the erase count of the memory control circuit unit 404 (or the memory management circuit 502) corresponding to the physical erase unit 410(0) is increased to 8000 (i.e., the second count) due to the erase operation performed on the physical erase unit 410 for 1000 times, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold corresponding to the physical erase unit 410(0) from 90 to 100 (i.e., the fourth threshold), for example, so that when the number of times the physical erase unit 410(0) is erased increases, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the physical erase unit 410 (0).

Assuming that the temperature of the rewritable nonvolatile memory module 406 rises from 60 ℃ to 80 ℃ at this time, as shown in fig. 15B, the memory control circuit unit 404 (or the memory management circuit 502) may adjust the read disturb threshold from 100 to 105 (i.e., the fifth threshold), for example.

Then, assuming that the temperature of the rewritable nonvolatile memory module 406 rises from 80 ℃ (i.e., the first temperature value) to 100 ℃ (i.e., the second temperature value), as shown in fig. 15C, the memory control circuit unit 404 (or the memory management circuit 502) can adjust the read disturb threshold from 105 to 110 (i.e., the sixth threshold), for example.

Assuming that the memory control circuit unit 404 (or the memory management circuit 502) reads the data from the physical programming unit 410(0) -1 at this time, the memory control circuit unit 404 (or the memory management circuit 502) simultaneously reads the error checking and correcting code corresponding to the data, and the error checking and correcting circuit 512 performs the error checking and correcting procedure on the read data according to the error checking and correcting code, thereby calculating the error bit count for the physical programming unit 410(0) -1 according to the number of error bits of the data stored in the physical programming unit 410(0) -1. Assuming that the value of the error bit count of the entity programming unit 410(0) -1 is 111, the memory control circuit unit 404 (or the memory management circuit 502) may copy the data stored in the entity erasing unit 410(0) to, for example, the buffer memory 508 after the read operation is performed on the entity programming unit 410(0) -1, perform the erasing operation on the entity erasing unit 410(0), and write the data originally stored in the entity programming unit 410(0) -1 back to the entity erasing unit 410(0) from the buffer memory 508 after the temperature of the rewritable non-volatile memory module 406 is reduced to a certain temperature value.

It should be noted, however, that the present invention is not limited to the above-mentioned manner of moving the data in the first entity erasing unit, and the present invention is not limited to the above-mentioned erase count, the temperature of the rewritable non-volatile memory module 406 and the reading disturbance threshold value, and the optimal corresponding relationship among the erase count, the temperature of the rewritable non-volatile memory module 406 and the reading disturbance threshold value can be obtained by repeated experiments according to different types of memory storage devices.

By the above method, the problem of more serious wear caused by excessive erase operations performed on the entity erasing unit 410(0) when the temperature of the rewritable non-volatile memory module 406 is increased can be effectively avoided.

In step S1601, the memory control circuit unit 404 (or the memory management circuit 502) checks the temperature of the rewritable nonvolatile memory module 406 to adjust the read disturb threshold of the first erase unit according to the temperature of the rewritable nonvolatile memory module.

Next, in step S1603, when the temperature of the rewritable non-volatile memory module 406 is increased from the first temperature value to a second temperature value, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the read disturb threshold of the first physical erase unit from a fifth threshold to a sixth threshold, wherein the second temperature value is greater than the first temperature value, and the sixth threshold is greater than the fifth threshold.

Therefore, in the third exemplary embodiment of the present invention, it is assumed that when the temperature of the rewritable non-volatile memory module 406 rises, the memory control circuit unit 404 (or the memory management circuit 502) dynamically increases the read disturb threshold corresponding to the entity-erased cell 410(0), so as to avoid the entity-erased cell 410(0) from being subjected to excessive erase operations and causing more serious wear.

It should be noted that, in the third exemplary embodiment, the read disturb threshold corresponding to each entity erasing unit is dynamically adjusted according to the temperature of the rewritable non-volatile memory module 406, but the invention is not limited thereto. In another exemplary embodiment, the memory controller 404 (or the memory management circuit 502) may further set the read disturb threshold value in consideration of the temperature of the rewritable non-volatile memory module 406 and the erase count of each physically erased cell. That is, the memory control circuit unit 404 (or the memory management circuit 502) in the first and second exemplary embodiments can dynamically adjust the read disturb threshold corresponding to each entity erasing unit according to the temperature of the rewritable non-volatile memory module 406 as described in the third exemplary embodiment.

In summary, since the rewritable non-volatile memory module has the phenomena of wear of the physical erase unit and read disturb, the present invention provides a method for dynamically adjusting the read disturb threshold according to the erase count of the physical erase unit, so as to effectively reduce the probability of wear of the physical erase unit or the probability of occurrence of read disturb.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method is used for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the memory management method comprises the following steps:

setting a reading interference threshold value for each entity erasing unit;

adjusting a reading interference threshold value of a first entity erasing unit according to state information of the rewritable non-volatile memory module; and

performing a read disturb prevention operation based on the read disturb threshold of the first physically erased cell, wherein the step of performing the read disturb prevention operation based on the read disturb threshold of the first physically erased cell comprises:

reading a read data from a first physical programming cell of the first physical erase cell;

determining whether the number of error bits of the read data read from the first physical programming cell is greater than the read disturb threshold of the first physical erase cell;

if the number of error bits of the read data read from the first physically programmed cell is greater than the read disturb threshold of the first physically erased cell, copying the data stored in the first physically erased cell to a second physically erased cell among the physically erased cells.

2. The method of claim 1, wherein the step of adjusting the read disturb threshold of the first physically erased cell according to the status information of the rewritable nonvolatile memory module comprises:

recording an erase count of each of the plurality of physically erased cells; and

when the erase count of the first physical erase unit is increased from a first count value to a second count value, the read disturb threshold of the first physical erase unit is adjusted from a third threshold to a fourth threshold,

wherein the second count value is greater than the first count value, and the fourth threshold value is greater than the third threshold value.

3. A memory management method is used for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the memory management method comprises the following steps:

setting a reading interference threshold value for each entity erasing unit;

adjusting a reading interference threshold value of a first entity erasing unit according to a temperature of the rewritable non-volatile memory module; and

performing a read disturb prevention operation based on the read disturb threshold of the first physically erased cell,

wherein the step of adjusting the read disturb threshold of the first physical erase unit based on the temperature of the rewritable non-volatile memory module comprises:

when the temperature of the rewritable non-volatile memory module increases from a first temperature value to a second temperature value, the read disturb threshold of the first physical erase unit is adjusted from a fifth threshold to a sixth threshold,

the second temperature value is greater than the first temperature value, and the sixth threshold value is greater than the fifth threshold value.

4. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

the rewritable non-volatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is used for setting a reading interference threshold value for each of the physically erased cells,

the memory control circuit unit is further used for adjusting a read interference threshold value of a first entity erasing unit according to a state information of the rewritable non-volatile memory module,

the memory control circuit unit is further configured to perform a read disturb prevention operation according to the read disturb threshold of the first physical erase cell, wherein in the operation of performing the read disturb prevention operation according to the read disturb threshold of the first physical erase cell,

the memory control circuit unit is further used for reading a read data from a first physical programming unit of the first physical erasing unit,

the memory control circuit unit is further configured to determine whether the number of erroneous bits of the read data read from the first physical programming unit is greater than the read disturb threshold of the first physical erase unit,

the memory control circuit unit is further configured to copy the data stored in the first physically erased cell to a second physically erased cell among the physically erased cells if the number of erroneous bits of the read data read from the first physically programmed cell is greater than the read disturb threshold of the first physically erased cell.

5. The memory storage device of claim 4, wherein in the adjusting the read disturb threshold of the first physically erased cell operation based on the status information of the rewritable non-volatile memory module,

the memory control circuit unit is further used for recording an erase count of each of the physically erased units,

when the erase count of the first physical erase unit is increased from a first count value to a second count value, the memory control circuit unit is further configured to adjust the read disturb threshold of the first physical erase unit from a third threshold value to a fourth threshold value,

6. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

the memory control circuit unit is further used for adjusting a read interference threshold value of a first entity erasing unit according to a temperature of the rewritable non-volatile memory module,

the memory control circuit unit is further configured to perform a read disturb prevention operation according to the read disturb threshold of the first physically erased cell,

wherein, during the operation of adjusting the read disturb threshold of the first physical erase unit according to the temperature of the rewritable non-volatile memory module,

when the temperature of the rewritable non-volatile memory module increases from a first temperature value to a second temperature value, the memory control circuit unit is further configured to adjust the read disturb threshold of the first physical erase unit from a fifth threshold to a sixth threshold,