CN103811070A - High-reliability NAND Flash reading method and system - Google Patents
High-reliability NAND Flash reading method and system Download PDFInfo
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- CN103811070A CN103811070A CN201210460392.0A CN201210460392A CN103811070A CN 103811070 A CN103811070 A CN 103811070A CN 201210460392 A CN201210460392 A CN 201210460392A CN 103811070 A CN103811070 A CN 103811070A
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Abstract
The invention relates to the technical field of data storage, and discloses a high-reliability NAND Flash reading method and system. The method comprises the following steps: storing N turnover point comparison voltages in a peripheral circuit, wherein the N turnover point comparison voltages are arranged to form N+1 voltage intervals by size, the number of statistic times of the voltage intervals are respectively stored in the peripheral circuit of the NAND Flash, and N is an odd number which is greater than 1; when receiving a reading command, acquiring N reading results by respectively using the storage states of the storage units in the N turnover point comparison voltage reading page; and sequentially determining the storage states and voltage intervals of the storage units, determining the reading result of the page, and adjusting the N turnover point comparison voltages. By adopting the multiple-reading mode, temporarily storing and comparing the reading results each time and combining ECC (error correction code) verification, the method and system can effectively reduce the probability of error reading in large-scale reading and enhance the accuracy of the reading operation.
Description
Technical field
The present invention relates to technical field of data storage, relate in particular to read method and the system thereof of a kind of high reliability NAND Flash.
Background technology
Flash memory (Flash Memory, flash memory are called for short flash memory) is the novel storage medium of one of being born in late 1980s.Non-volatile owing to having, at a high speed, the good characteristic such as high antidetonation, low-power consumption, small volume and less weight, flash memory is widely used in the embedded system and portable set in the field such as mobile communication, data acquisition in recent years, as mobile phone, portable electronic device, digital camera, Digital Video, sensor, also for fields such as Aero-Space, as aerospace vehicle etc.
NAND Flash a kind ofly can carry out the erasable Nonvolatile semiconductor flash memory of electricity online, has the advantages such as erasable speed is fast, low-power consumption, large capacity, low cost, applies very extensive.In recent years, along with music player, the market such as mobile phone and storage card flourish, the shipment amount of NAND Flash climbs up and up, semiconductor manufacturer is by reduction process size and adopt many-valued technology (MLC/TLC), the capacity of NAND Flash is risen to several Gbit from hundreds of Mbit, but the tolerance limit (being the scope between the minimum voltage of programmed state and the maximum voltage of erase state) that simultaneously makes threshold voltage reduces and cause the reliability of chip to reduce, therefore, under existing technique, the threshold voltage of accurately adjusting NAND Flash just seems particularly important.
Take the NAND Flash of monodrome type as example, traditional monodrome type NAND Flash reads mechanism as above shown in Fig. 1, its principle is: select a suitable overturn point comparative voltage (being between the minimum voltage of programmed state and the maximum voltage of erase state) between programmed state and the threshold voltage of erase state, once read, storage unit (cell) unification that is greater than this overturn point comparative voltage is defined as programmed state, is less than the unified erase state that is defined as of storage unit (cell) of this overturn point comparative voltage.
There is certain defect in a this traditional read method.As everyone knows, itself there is uncertainty in the threshold value distribution of storage unit, after repeatedly program erase operates, the distribution range of threshold value can further depart from ideal, for example, in the NAND Flash of employing floating grid, there is the shift phenomenon of the threshold voltage being caused by the disturbing effect of element that affects threshold voltage, may there is the problem of programmed state and the skew of erase state threshold window, for example storer voltage distributes and occurs the distribution situation shown in Fig. 2 (a) or Fig. 2 (b), even there is programmed state and the overlapping problem of erase state threshold window, for example storer voltage distributes and occurs the distribution situation shown in Fig. 2 (c).Now, if adopt a traditional reading manner, after the operation of program erase repeatedly, there will be the figure place that mistake reads to increase gradually, carrying out large-scale page while reading, directly obtain final correct data by being difficult to, cause read error.
Summary of the invention
The object of the invention is to propose read method and the system thereof of a kind of high reliability NAND Flash, can effectively reduce error bit probability, improve the accuracy of read operation, thereby improve the reliability of NAND Flash.
For reaching this object, the present invention proposes the read method of a kind of high reliability NAND Flash, in the peripheral circuit of described NAND Flash, store N overturn point comparative voltage, described N overturn point comparative voltage arranged by size and formed N+1 voltage range, in the peripheral circuit of described NAND Flash, store respectively the statistics number of each voltage range, described N is greater than 1 odd number;
In the time that described NAND Flash receives reading order:
S1, use described N overturn point comparative voltage respectively
read in NAND Flash pagethe store status of each storage unit
,obtain N part reading result, wherein said store status is erase state or programmed state
, wherein said useoverturn point comparative voltage
the operation of reading NAND Flash page comprises:
Apply described overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this overturn point comparative voltage of use;
s2,according to described N part reading result, determine successively store status and the residing voltage range of each storage unit, in the time that certain storage unit is positioned at certain voltage range, the statistics number of this voltage range is added to one, and,
The store status of S3, the described each storage unit of foundation is determined the reading result of this NAND Flash page;
S4, the statistics number of a described N+1 voltage range is analyzed, in the time meeting default regularization condition, the statistics number of described N overturn point comparative voltage or a described N+1 voltage range is adjusted.
Further, if this Nand Flash is ECC flash memory, the store status of the described each storage unit of described foundation is determined after the reading result of this NAND Flash page and is also comprised the reading result of this NAND Flash page is carried out to ECC verification.
Further, the described N part of described foundation reading result, the store status of determining successively each storage unit specifically comprises: in described N part reading result, successively the store status of each storage unit is added up, in the time that in certain storage unit, programmed state number of times is greater than erase state number of times, this memory cell content is defined as to erase state, otherwise this memory cell content is defined as to programmed state.
Further, described determine successively each storage unit electric discharge default discharge time after residing voltage range specifically comprise: from described N part reading result, obtain successively the store status of each storage unit, in the time that the state of certain storage unit in N part reading result is programmed state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being greater than to the interval of maximum overturn point comparative voltage, in the time that the state of certain storage unit in N part reading result is erase state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being less than to the interval of minimum overturn point comparative voltage, when the store status difference of certain storage unit in the reading result of the adjacent overturn point comparative voltage of certain size, after this storage unit electric discharge is preset to discharge time, residing voltage range is defined as the interval that these adjacent two voltages form.
Further, described N is 3.
According to same design of the present invention, the present invention also provides the reading system of a kind of high reliability NAND Flash, in the peripheral circuit of described NAND Flash, store N overturn point comparative voltage, and described N the statistics number that overturn point comparative voltage is arranged N+1 voltage range of formation by size, described N is greater than 1 odd number;
Comprise:
Preliminary read module, in the time that described NAND Flash receives reading order, uses respectively described N overturn point comparative voltage
read in NAND Flash pagethe store status of each storage unit
,obtain N part reading result, wherein said store status is erase state or programmed state
, wherein said useoverturn point comparative voltage
the operation of reading NAND Flash page comprises:
Apply described overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this overturn point comparative voltage of use;
Element analysis and data acquisition module, for in the time that described NAND Flash receives reading order, the N part reading result obtaining according to described preliminary read module, determine successively store status and the residing voltage range of each storage unit, in the time that certain storage unit is positioned at certain voltage range, the statistics number of this voltage range is added to one, and
Determine the reading result of this NAND Flash page according to the store status of described each storage unit;
Data adjusting module, for in the time that described NAND Flash receives reading order, according to the statistics number of N+1 voltage range in described element analysis and data acquisition module, statistics number to a described N+1 voltage range is analyzed, in the time meeting default regularization condition, the statistics number of described N overturn point comparative voltage or a described N+1 voltage range is adjusted.
Further, also comprise ECC correction verification module, in the time that this Nand Flash is ECC flash memory, the reading result of the page that element analysis and data acquisition module are read carries out ECC verification.
Further, the store status of determining successively each storage unit in described element analysis and data acquisition module specifically comprises: in described N part reading result, successively the store status of each storage unit is added up, in the time that in certain storage unit, programmed state number of times is greater than erase state number of times, this memory cell content is defined as to erase state, otherwise this memory cell content is defined as to programmed state.
Further, after in described element analysis and data acquisition module, discharge time is preset in definite each storage unit electric discharge successively, residing voltage range specifically comprises: from described N part reading result, obtain successively the store status of each storage unit, in the time that the state of certain storage unit in N part reading result is programmed state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being greater than to the interval of maximum overturn point comparative voltage, in the time that the state of certain storage unit in N part reading result is erase state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being less than to the interval of minimum overturn point comparative voltage, when the store status difference of certain storage unit in the reading result of two adjacent overturn point comparative voltages of certain size, after this storage unit electric discharge is preset to discharge time, residing voltage range is defined as the interval that these adjacent two voltages form.
Further, described N is 3.
The present invention proposes a kind of read method of alleviating the overlapping impact of memory threshold, read at large-scale page the mode that middle employing is repeatedly read, the temporary result at every turn reading compares, coordinate ECC verification, can effectively reduce and read on a large scale the probability that middle mistake reads, improve the accuracy of read operation.
Accompanying drawing explanation
Fig. 1 is that in prior art, storer reads schematic diagram of mechanism;
Fig. 2 is the schematic diagram of three kinds of situations of storer voltage distribution in prior art;
Fig. 3 is the read method process flow diagram of highly reliable NAND Flash described in the embodiment of the present invention one;
Fig. 4 is the reading system block diagram of highly reliable NAND Flash described in the embodiment of the present invention two.
Embodiment
The present invention stores N overturn point comparative voltage in the peripheral circuit of described NAND Flash, described N overturn point comparative voltage arranged by size and formed N+1 voltage range, the statistics number of storing respectively each voltage range in the peripheral circuit of described NAND Flash.
Wherein N is greater than 1 odd number, and for example, N can be 3,5 or 7 etc.For the object of odd number is in the time that the result that uses different overturn point comparative voltages to read same storage unit cell is different, be convenient to the number of times of programmed state and the number of times of erase state in these reading results by adding up this unit, get the final store status of much more relatively store statuss of number of times as this unit.
Take N as 3 as example, for example, in peripheral circuit, store 3 overturn point comparative voltages, be respectively 5V, 4V, 6V, 4 voltage ranges that these three voltages form after arranging by order are from small to large followed successively by from small to large: U<4V, 4V<U<5V, 5V<U<6V, U>6V, the statistics number of storing respectively each voltage range in peripheral circuit.When each reading out data, continue the statistics number of each voltage range to add up, preset regularization condition, according to described statistics, described 3 overturn point comparative voltages are carried out to accommodation, prepare against while reading next time and use.
Illustrate in the time that NAND Flash receives reading order below in conjunction with accompanying drawing and by embodiment, read the method and system of the operation of NAND Flash page.
Embodiment mono-
Fig. 3 is the read method process flow diagram of highly reliable NAND Flash described in the present embodiment, as shown in Figure 3, in the time that described NAND Flash receives reading order, use respectively described N overturn point comparative voltage to read the store status of each storage unit in NAND Flash page, obtain N part reading result, wherein said store status is erase state or programmed state.Take N=3 as example, concrete read method comprises:
S301, read page with the first overturn point comparative voltage, preserve reading result;
Nand Flash has various structures, and take the NAND Flash of SLC type as example, data are to be kept at storage unit cell in the mode of bit.In the NAND Flash of SLC type, in a cell, can only store a bit, these cell are combination take 8 or 16 as unit, forms so-called byte or word, the bit wide of Here it is NAND Device, and these byte/word can recomposition Page.The K9F1208U0M of for example Samsung, every page of 528Byte, every 32 page pages form a Block piece, and a block piece is 16kByte.Disc as hard disk is divided into magnetic track, and each magnetic track is divided into again some sectors, and a Nand flash is also divided into some, and each is divided into some pages.Generally speaking, the relation between piece, page is different along with the difference of chip.
Nand flash reads and writes data take page as unit, and take piece as unit obliterated data.
In the time that described NAND Flash receives reading order, the operation that first overturn point comparative voltage of wherein said use reads NAND Flash page comprises:
Apply described the first overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this first overturn point comparative voltage of use, the storage unit (cell) that is greater than the first overturn point comparative voltage after electric discharge is defined as to programmed state, be designated as " 0 ", the storage unit (cell) that is less than the first overturn point comparative voltage after electric discharge is defined as to erase state, be designated as " 1 ".The reading result of this page is saved.
S302, read page with the second overturn point comparative voltage, preserve reading result;
This step with drill do identical, read for the second time by the second overturn point comparative voltage, apply described the second overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this second overturn point comparative voltage of use, the storage unit (cell) that is greater than the second overturn point comparative voltage after electric discharge is defined as to programmed state, be designated as " 0 ", the storage unit (cell) that is less than the second overturn point comparative voltage after electric discharge is defined as to erase state, be designated as " 1 ".The reading result of this page is saved.
S303, read page with the 3rd overturn point comparative voltage, preserve reading result;
This step is all identical with upper two step operations, read for the third time by the 3rd overturn point comparative voltage, the storage unit (cell) that is greater than the 3rd overturn point comparative voltage after electric discharge is defined as to programmed state, be designated as " 0 ", the storage unit (cell) that is less than the 3rd overturn point comparative voltage after electric discharge is defined as to erase state, is designated as " 1 ".The reading result of this page is saved.
S304, compare by unit, determine store status, determine voltage range, revise the statistics number of this voltage range;
Obtain successively the store status of each storage unit, when the state of certain storage unit in N part reading result is programmed state, the voltage range of this storage unit is positioned at the interval that is greater than maximum overturn point comparative voltage, when the state of certain storage unit in N part reading result is erase state, the voltage range of this storage unit is positioned at the interval that is less than minimum overturn point comparative voltage, when the state of certain storage unit in N part reading result has redirect in the reading result of certain two adjacent overturn point comparative voltage, the voltage range of this storage unit is between the interval of these adjacent two overturn point comparative voltages.
Take eight storage unit in this NAND Flash page as example, for example, while reading with overturn point comparative voltage 4V for the first time, result is 10101101, while reading with overturn point comparative voltage 5V for the second time, result is 11101101, while reading with overturn point comparative voltage 6V for the third time, result is 11101111, determines that storage content and definite voltage range result are as follows:
First: read for three times and be 1, finally determine that store status is 1, the voltage range U<4V of this storage unit, adds one by the statistics number of U<4V;
Second: read for three times and be followed successively by 0,1,1, state is that 1 number of times is 2 times, state is that 0 number of times is 1 time, final definite store status is 1, this storage unit jumps to 1 by 0 in the reading result of certain two adjacent overturn point comparative voltage 4V and 5V, the voltage range of this storage unit is between the interval of these adjacent two voltages, the voltage range of this storage unit is 4V<U<5V, and the statistics number of 4V<U<5V is added to one;
The 3rd: identical with first analysis, the voltage range of this storage unit is U<4V, and the statistics number of U<4V is added to one;
The 4th: read for three times and be 0, finally determine that store status is 0, the voltage range U>6V of this storage unit, adds one by the statistics number of U>6V;
The 5th, the 6th: identical with first analysis, the voltage range of their storage unit is U<4V, respectively the statistics number of U<4V is added to one;
The 7th: read for three times and be followed successively by 0,0,1, state is that 0 number of times is 2 times, state is that 1 number of times is 1 time, final definite store status is 0, this storage unit jumps to 1 by 0 in the reading result of certain two adjacent overturn point comparative voltage 5V and 6V, the voltage range of this storage unit is between the interval of these adjacent two voltages, the voltage range of this storage unit is 5V<U<6V, and the statistics number of 5V<U<6V is added to one;
The 8th: identical with first analysis, the voltage range of this storage unit is U<4V, and the statistics number of U<4V is added to one.
S305, definite storage content is carried out to ECC verification;
According to upper step, the definite event memory of these eight storage unit is 11101101, determines the event memory of this page of whole storage unit according to said method.
If this Nand Flash is ECC flash memory, above-mentioned event memory is carried out to ECC and test, obtain the final event memory of this page.
S306, judge whether to meet default regularization condition, if perform step S307, otherwise finish;
After obtaining final event memory, the statistics number of a described N+1 voltage range is analyzed, judged whether to meet default regularization condition, if perform step S307, otherwise finish.
Described default regularization condition is for presetting condition, and object reads self-adaptation in this Nand Flash use procedure, realizes the robotization adjustment of overturn point comparative voltage.
Be specially according to the statistics number of N overturn point comparative voltage and N+1 voltage range and set, can set in conjunction with the characteristic of Nand Flash simultaneously.
S307, N overturn point comparative voltage or statistics number are adjusted, finished.
For example, N is 3 o'clock, three overturn point comparative voltages are followed successively by U1, U2, U3 from small to large, voltage range is: U<U1, U1<U<U2, U2<U<U3, U>U3, can set: when the number of times of U1<U<U2 is during than the number of times of U2<U<U3 large 30, U2+0.1V; When the number of times of U2<U<U3 is during than the number of times of U1<U<U2 large 30, U2-0.1V; In the time that the number of times of U<U1 is greater than 500 divided by the number of times of U1<U<U2, U1-0.2V; In the time that the number of times of U>U3 is greater than 500 divided by the number of times of U2<U<U3, U3+0.2V.
In the time that N is 5, be with the difference of aforesaid operations, after step S303, also comprise and read page and preserve reading result and read page and preserve reading result with the 5th overturn point comparative voltage with the 4th overturn point comparative voltage, in step S304, compare by unit, determine store status, determine voltage range, while revising the statistics number of this voltage range according to the reading result of the above-mentioned NAND Flash page that reads and preserve by 5 overturn point comparative voltages respectively.
The rest may be inferred, and in the time that N is the odd number such as 7,9, method is similar, and therefore not to repeat here.
Embodiment bis-
According to same design of the present invention, the present invention also provides the reading system of a kind of highly reliable NAND Flash, in described system, in the peripheral circuit of described NAND Flash, store N overturn point comparative voltage, and described N the statistics number that overturn point comparative voltage is arranged N+1 voltage range of formation by size, use respectively described N overturn point comparative voltage to read the store status of each storage unit in NAND Flash page, obtain N part reading result.Fig. 4 is the reading system block diagram of highly reliable NAND Flash described in the present embodiment, and as shown in Figure 4, the reading system of the highly reliable NAND Flash described in the present embodiment comprises:
Preliminary read module, for in the time that described NAND Flash receives reading order, use respectively N overturn point comparative voltage to read the store status of each storage unit in NAND Flash page, obtain N part reading result, wherein said store status is erase state or programmed state.
Nand Flash has various structures, and take the NAND Flash of SLC type as example, data are to be kept at storage unit cell in the mode of bit.In the NAND Flash of SLC type, in a cell, can only store a bit, these cell are combination take 8 or 16 as unit, forms so-called byte or word, the bit wide of Here it is NAND Device, and these byte/word can recomposition Page.The K9F1208U0M of for example Samsung, every page of 528Byte, every 32 page pages form a Block piece, and a block piece is 16kByte.Disc as hard disk is divided into magnetic track, and each magnetic track is divided into again some sectors, and a Nand flash is also divided into some, and each is divided into some pages.Generally speaking, the relation between piece, page is different along with the difference of chip.
Nand flash reads and writes data take page as unit, and take piece as unit obliterated data.
The concrete read operation of this module is identical with traditional read operation, and take N=3 as example, this functions of modules is:
In the time that described NAND Flash receives reading order, the operation that first overturn point comparative voltage of wherein said use reads NAND Flash page comprises:
Apply described the first overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this first overturn point comparative voltage of use, the storage unit (cell) that is greater than the first overturn point comparative voltage after electric discharge is defined as to programmed state, be designated as " 0 ", the storage unit (cell) that is less than the first overturn point comparative voltage after electric discharge is defined as to erase state, be designated as " 1 ".The reading result of this page is saved.
Use again same procedure, read respectively this page of content by the second overturn point comparative voltage and the 3rd overturn point comparative voltage successively, respectively reading result is saved.
Element analysis and data acquisition module, for in the time that described NAND Flash receives reading order, the N part reading result obtaining according to described preliminary read module, determine successively store status and the residing voltage range of each storage unit, in the time that certain storage unit is positioned at certain voltage range, the statistics number of this voltage range is added to one, and
Determine the reading result of this NAND Flash page according to the store status of described each storage unit;
The store status of obtaining successively each storage unit specifically comprises: when the state of certain storage unit in N part reading result is programmed state, the voltage range of this storage unit is positioned at the interval that is greater than maximum overturn point comparative voltage, when the state of certain storage unit in N part reading result is erase state, the voltage range of this storage unit is positioned at the interval that is less than minimum overturn point comparative voltage, when the state of certain storage unit in N part reading result has redirect in the reading result of certain two adjacent overturn point comparative voltage, the voltage range of this storage unit is between the interval of these adjacent two voltages.
Take eight storage unit in this NAND Flash page as example, for example, while reading with overturn point comparative voltage 4V for the first time, result is 10101101, while reading with overturn point comparative voltage 5V for the second time, result is 11101101, while reading with overturn point comparative voltage 6V for the third time, result is 11101111, determines that storage content and definite voltage range result are as follows:
First: read for three times and be 1, finally determine that store status is 1, the voltage range U<4V of this storage unit, adds one by the statistics number of U<4V;
Second: read for three times and be followed successively by 0,1,1, state is that 1 number of times is 2 times, state is that 0 number of times is 1 time, final definite store status is 1, this storage unit jumps to 1 by 0 in the reading result of certain two adjacent overturn point comparative voltage 4V and 5V, the voltage range of this storage unit is between the interval of these adjacent two voltages, the voltage range of this storage unit is 4V<U<5V, and the statistics number of 4V<U<5V is added to one;
The 3rd: identical with first analysis, the voltage range of this storage unit is U<4V, and the statistics number of U<4V is added to one;
The 4th: read for three times and be 0, finally determine that store status is 0, the voltage range U>6V of this storage unit, adds one by the statistics number of U>6V;
The 5th, the 6th: identical with first analysis, the voltage range of their storage unit is U<4V, respectively the statistics number of U<4V is added to one;
The 7th: read for three times and be followed successively by 0,0,1, state is that 0 number of times is 2 times, state is that 1 number of times is 1 time, final definite store status is 0, this storage unit jumps to 1 by 0 in the reading result of certain two adjacent overturn point comparative voltage 5V and 6V, the voltage range of this storage unit is between the interval of these adjacent two voltages, the voltage range of this storage unit is 5V<U<6V, and the statistics number of 5V<U<6V is added to one;
The 8th: identical with first analysis, the voltage range of this storage unit is U<4V, and the statistics number of U<4V is added to one.
According to above-mentioned analysis, the definite event memory of these eight storage unit is 11101101, according to the above-mentioned event memory of determining this page of whole storage unit.
ECC correction verification module, in the time that this Nand Flash is ECC flash memory, the reading result of the page that element analysis and data acquisition module are read carries out ECC verification.
If this Nand Flash is ECC flash memory, above-mentioned event memory is carried out to ECC and test, obtain the final event memory of this page.
Data adjusting module, for in the time that described NAND Flash receives reading order, according to the statistics number of N+1 voltage range in described element analysis and data acquisition module, statistics number to a described N+1 voltage range is analyzed, in the time meeting default regularization condition, the statistics number of described N overturn point comparative voltage or a described N+1 voltage range is adjusted.
After this module is obtained final event memory for described element analysis and data acquisition module, statistics number to a described N+1 voltage range is analyzed, in the time that the statistics number of a described N+1 voltage range meets default regularization condition, this Nand Flash is read to self-adaptation, realize the robotization adjustment of overturn point comparative voltage.
Described default regularization condition is for presetting condition, and object reads self-adaptation in this Nand Flash use procedure, realizes the robotization adjustment of overturn point comparative voltage.
Be specially according to the statistics number of N overturn point comparative voltage and N+1 voltage range and set, can set in conjunction with the characteristic of Nand Flash simultaneously.
For example, N is 3 o'clock, three voltages are followed successively by U1, U2, U3 from small to large, voltage range is: U<U1, U1<U<U2, U2<U<U3, U>U3, can set: when the number of times of U1<U<U2 is during than the number of times of U2<U<U3 large 30, U2+0.1V; When the number of times of U2<U<U3 is during than the number of times of U1<U<U2 large 30, U2-0.1V; In the time that the number of times of U<U1 is greater than 500 divided by the number of times of U1<U<U2, U1-0.2V; In the time that the number of times of U>U3 is greater than 500 divided by the number of times of U2<U<U3, U3+0.2V.
In the time that N is 5, compared with N=3, just in preliminary read module, also comprise and read page and preserve reading result and read page and preserve reading result with the 5th overturn point comparative voltage with the 4th overturn point comparative voltage, in element analysis and data acquisition module, compare by unit, determine store status, determine voltage range, while revising the statistics number of this voltage range according to the reading result of the above-mentioned NAND Flash page that reads and preserve by 5 overturn point comparative voltages respectively.
The rest may be inferred, and in the time that N is the odd number such as 7,9, method is similar, and therefore not to repeat here.
The present invention is by reading at large-scale page the mode that middle employing is repeatedly read, and the temporary result at every turn reading compares, and coordinates ECC verification, can effectively reduce and read on a large scale the probability that middle mistake reads, and improves the accuracy of read operation.
All or part of content in the technical scheme that above embodiment provides can realize by software programming, and its software program is stored in the storage medium can read, storage medium for example: hard disk, CD or floppy disk in computing machine.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the read method of a high reliability NAND Flash, it is characterized in that, in the peripheral circuit of described NANDFlash, store N overturn point comparative voltage, described N overturn point comparative voltage arranged by size and formed N+1 voltage range, in the peripheral circuit of described NAND Flash, store respectively the statistics number of each voltage range, described N is greater than 1 odd number;
In the time that described NAND Flash receives reading order:
S1, use described N overturn point comparative voltage to read the store status of each storage unit in NAND Flash page respectively, obtain N part reading result, wherein said store status is erase state or programmed state, and the operation that wherein said use overturn point comparative voltage reads NAND Flash page comprises:
Apply described overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this overturn point comparative voltage of use;
S2, the described N part reading result of foundation, store status and the residing voltage range of definite each storage unit, in the time that certain storage unit is positioned at certain voltage range, add one by the statistics number of this voltage range successively, and,
The store status of S3, the described each storage unit of foundation is determined the reading result of this NAND Flash page;
S4, the statistics number of a described N+1 voltage range is analyzed, in the time meeting default regularization condition, the statistics number of described N overturn point comparative voltage or a described N+1 voltage range is adjusted.
2. the read method of high reliability NAND Flash as claimed in claim 1, it is characterized in that, if this Nand Flash is ECC flash memory, the store status of the described each storage unit of described foundation is determined after the reading result of this NAND Flash page and is also comprised the reading result of this NAND Flash page is carried out to ECC verification.
3. the read method of high reliability NAND Flash as claimed in claim 1 or 2, it is characterized in that, the described N part of described foundation reading result, the store status of determining successively each storage unit specifically comprises: in described N part reading result, successively the store status of each storage unit is added up, in the time that programmed state number of times is greater than erase state number of times in certain storage unit, this memory cell content is defined as to erase state, otherwise this memory cell content is defined as to programmed state.
4. the read method of high reliability NAND Flash as claimed in claim 3, it is characterized in that, described determine successively each storage unit electric discharge default discharge time after residing voltage range specifically comprise: from described N part reading result, obtain successively the store status of each storage unit, in the time that the state of certain storage unit in N part reading result is programmed state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being greater than to the interval of maximum overturn point comparative voltage, in the time that the state of certain storage unit in N part reading result is erase state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being less than to the interval of minimum overturn point comparative voltage, when the store status difference of certain storage unit in the reading result of two adjacent overturn point comparative voltages of certain size, after this storage unit electric discharge is preset to discharge time, residing voltage range is defined as the interval that these adjacent two voltages form.
5. the read method of high reliability NAND Flash as claimed in claim 3, is characterized in that, described N is 3.
6. the reading system of a high reliability NAND Flash, it is characterized in that, in the peripheral circuit of described NANDFlash, store N overturn point comparative voltage, and described N the statistics number that overturn point comparative voltage is arranged N+1 voltage range of formation by size, described N is greater than 1 odd number;
Comprise:
Preliminary read module, for in the time that described NAND Flash receives reading order, use respectively described N overturn point comparative voltage to read the store status of each storage unit in NAND Flash page, obtain N part reading result, wherein said store status is erase state or programmed state, and the operation that wherein said use overturn point comparative voltage reads NAND Flash page comprises:
Apply described overturn point comparative voltage to the comparer of sense amplifier, applying preset charged voltage to described NAND Flash page charges and timing to each storage unit, in the time that timing exceedes preset charged time threshold, when removing described preset charged voltage complete charge and carrying out discharge gage, reach default discharge time in the time of discharge gage time, the store status of each storage unit in this NAND Flash page while reading this overturn point comparative voltage of use;
Element analysis and data acquisition module, for in the time that described NAND Flash receives reading order, the N part reading result obtaining according to described preliminary read module, determine successively store status and the residing voltage range of each storage unit, in the time that certain storage unit is positioned at certain voltage range, the statistics number of this voltage range is added to one, and
Determine the reading result of this NAND Flash page according to the store status of described each storage unit;
Data adjusting module, for in the time that described NAND Flash receives reading order, according to the statistics number of N+1 voltage range in described element analysis and data acquisition module, statistics number to a described N+1 voltage range is analyzed, in the time meeting default regularization condition, the statistics number of described N overturn point comparative voltage or a described N+1 voltage range is adjusted.
7. the reading system of high reliability NAND Flash as claimed in claim 6, it is characterized in that, also comprise ECC correction verification module, in the time that this Nand Flash is ECC flash memory, the reading result of the page that element analysis and data acquisition module are read carries out ECC verification.
8. the reading system of the high reliability NAND Flash as described in claim 6 or 7, it is characterized in that, the store status of determining successively each storage unit in described element analysis and data acquisition module specifically comprises: in described N part reading result, successively the store status of each storage unit is added up, in the time that in certain storage unit, programmed state number of times is greater than erase state number of times, this memory cell content is defined as to erase state, otherwise this memory cell content is defined as to programmed state.
9. the read method of high reliability NAND Flash as claimed in claim 8, it is characterized in that, after in described element analysis and data acquisition module, discharge time is preset in definite each storage unit electric discharge successively, residing voltage range specifically comprises: from described N part reading result, obtain successively the store status of each storage unit, in the time that the state of certain storage unit in N part reading result is programmed state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being greater than to the interval of maximum overturn point comparative voltage, in the time that the state of certain storage unit in N part reading result is erase state, residing voltage range after default the electric discharge of this storage unit discharge time is defined as being less than to the interval of minimum overturn point comparative voltage, when the store status difference of certain storage unit in the reading result of two adjacent overturn point comparative voltages of certain size, after this storage unit electric discharge is preset to discharge time, residing voltage range is defined as the interval that these adjacent two voltages form.
10. the read method of high reliability NAND Flash as claimed in claim 8, is characterized in that, described N is 3.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978153A (en) * | 2015-07-10 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Method and apparatus for configruation nformation in data storage type flash memory |
| CN105206302A (en) * | 2015-09-14 | 2015-12-30 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN107204205A (en) * | 2016-03-16 | 2017-09-26 | 群联电子股份有限公司 | Storage management method, memorizer control circuit unit and memory storage apparatus |
| CN109119118A (en) * | 2017-06-22 | 2019-01-01 | 点序科技股份有限公司 | Flash memory device and data reading method thereof |
| CN111883198A (en) * | 2019-05-02 | 2020-11-03 | 爱思开海力士有限公司 | Memory controller and operating method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921015A (en) * | 2005-08-17 | 2007-02-28 | 赛芬半导体有限公司 | Method for reading non-volatile memory cells |
| US20070291546A1 (en) * | 2006-06-19 | 2007-12-20 | Teruhiko Kamei | Systems for Programming Differently Sized Margins and Sensing with Compensations at Select States for Improved Read Operations in Non-Volatile Memory |
| CN101681679A (en) * | 2007-05-02 | 2010-03-24 | 美光科技公司 | By non-volatile multilevel memory cell to the data read of reference unit |
| US20100103731A1 (en) * | 2008-10-27 | 2010-04-29 | Samsung Electronics Co., Ltd. | Method analyzing threshold voltage distribution in nonvolatile memory |
-
2012
- 2012-11-15 CN CN201210460392.0A patent/CN103811070B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921015A (en) * | 2005-08-17 | 2007-02-28 | 赛芬半导体有限公司 | Method for reading non-volatile memory cells |
| US20070291546A1 (en) * | 2006-06-19 | 2007-12-20 | Teruhiko Kamei | Systems for Programming Differently Sized Margins and Sensing with Compensations at Select States for Improved Read Operations in Non-Volatile Memory |
| CN101681679A (en) * | 2007-05-02 | 2010-03-24 | 美光科技公司 | By non-volatile multilevel memory cell to the data read of reference unit |
| US20100103731A1 (en) * | 2008-10-27 | 2010-04-29 | Samsung Electronics Co., Ltd. | Method analyzing threshold voltage distribution in nonvolatile memory |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978153A (en) * | 2015-07-10 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Method and apparatus for configruation nformation in data storage type flash memory |
| CN105206302A (en) * | 2015-09-14 | 2015-12-30 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN107204205A (en) * | 2016-03-16 | 2017-09-26 | 群联电子股份有限公司 | Storage management method, memorizer control circuit unit and memory storage apparatus |
| CN107204205B (en) * | 2016-03-16 | 2020-05-26 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
| CN109119118A (en) * | 2017-06-22 | 2019-01-01 | 点序科技股份有限公司 | Flash memory device and data reading method thereof |
| CN111883198A (en) * | 2019-05-02 | 2020-11-03 | 爱思开海力士有限公司 | Memory controller and operating method thereof |
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|---|---|
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