CN105575433B - Nand memory and its device for balancing the WL Voltage Establishment time - Google Patents
Nand memory and its device for balancing the WL Voltage Establishment time Download PDFInfo
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- CN105575433B CN105575433B CN201510918013.1A CN201510918013A CN105575433B CN 105575433 B CN105575433 B CN 105575433B CN 201510918013 A CN201510918013 A CN 201510918013A CN 105575433 B CN105575433 B CN 105575433B
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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Abstract
The embodiment of the invention provides a kind of nand memory and its devices of balance WL Voltage Establishment time, device includes: control signal receiving module, when in nand memory the first plane and the 2nd plane simultaneously operate when, it controls signal receiving module and receives first control signal, and when operating to the first plane or the 2nd plane, control signal receiving module receives second control signal；Clock control module, the input terminal of clock control module is connected with control signal receiving module, the output end of clock control module is connected with the charge pump of nand memory, clock control module exports the first clock signal according to first control signal, and exports second clock signal according to second control signal；Frequency of the frequency of second clock signal less than the first clock signal.The embodiment of the present invention enables to the WL Voltage Establishment time to be consistent in single plane operation and double plane operations.
Description
Technical field
The present invention relates to memory technology fields, more particularly to a kind of device and one kind for balancing the WL Voltage Establishment time
Nand memory.
Background technique
When NAND (computer flash memory device) memory to double plane (storage matrix) structure operates, sometimes
It is double plane operation modes, i.e., two plane is operated simultaneously, sometimes list plane operation mode, i.e., only to two
A plane in plane carries out individually operated.
Traditional nand memory is as shown in Figure 1, under above two operation mode, needed for the charge pump of nand memory
The capacitor to be driven is not identical.Such as in double plane operation modes, to PLN0 ' and PLN1 ' it operates simultaneously, charge pump
It needs to drive capacitor CCGA’, capacitor CCG0’, capacitor CCG1’, capacitor CWL0’With capacitor CWL1’, at this point, key signal in nand memory
Schematic diagram is as shown in Figure 2.PLN0 ' or PLN1 ' is individually operated in single plane operation mode, charge pump is corresponding only to be needed
Drive capacitor CCGA ', capacitor CCG0 ' and capacitor CWL0 ' or capacitor CCGA ', capacitor CCG1 ' and capacitor CWL1 ', wherein right
When PLN1 ' is individually operated, key signal schematic diagram is as shown in Figure 3 in nand memory.
Since under above two different operation mode, as shown in Figures 2 and 3, the driving capability of charge pump is the same, lead
Cause the recovery time t21' and t31' of the output signal PUMP ' of charge pump not identical, WL1 ' Voltage Establishment time t22' and t32'
Also not identical.
Summary of the invention
In view of the above problems, the embodiment of the present invention be designed to provide it is a kind of balance the WL Voltage Establishment time device and
A kind of corresponding nand memory, to solve traditional nand memory in different modes of operation, when establishing of WL voltage
Between different problem.
To solve the above-mentioned problems, the embodiment of the invention discloses a kind of devices for balancing the WL Voltage Establishment time, comprising:
Control signal receiving module, when in nand memory the first plane and the 2nd plane simultaneously operate when, the control
Signal receiving module processed receives first control signal, and works as and operate to 2nd plane of the first plane or described
When, the control signal receiving module receives second control signal；Clock control module, the input terminal of the clock control module
It is connected with the control signal receiving module, the output end of the clock control module is connected with the charge pump of nand memory,
The clock control module exports the first clock signal according to the first control signal, and according to the second control signal
Export second clock signal；The frequency of the second clock signal is less than the frequency of first clock signal.
Specifically, the control signal receiving module includes: the first signal receiving end and second signal receiving end, wherein
When the control signal receiving module receives the first control signal, first signal receiving end is high level, described
Second signal receiving end is low level；When the control signal receiving module receives the second control signal, described first
Signal receiving end is low level, and the second signal receiving end is high level.
Specifically, the clock control module includes: the first clock source, and first clock source generates first clock
Signal；Second clock source, the second clock source generate the second clock signal；First clock control cell, described first
The input terminal of clock control cell respectively with first signal receiving end, the second signal receiving end, first clock
Source is connected with the second clock source, and the output end of first clock control cell is connected with the charge pump, and described first
Clock control cell exports first clock signal according to the first control signal, and according to the second control signal
Export the second clock signal.
Specifically, the clock control module includes: tertiary clock source, and the tertiary clock source generates first clock
Signal；Second clock control unit, the input terminal of the second clock control unit respectively with first signal receiving end, institute
It states second signal receiving end to be connected with the tertiary clock source, the output end of the second clock control unit and the charge pump
It is connected, the second clock control unit exports first clock signal according to the first control signal, and according to institute
It states second control signal to handle first clock signal, and exports the second clock signal.
Specifically, first clock control cell includes: the first logical AND gate, and the first of first logical AND gate is defeated
Enter end and the second input terminal is connected with first signal receiving end and first clock source respectively；Second logical AND gate, institute
State the second logical AND gate first input end and the second input terminal respectively with the second signal receiving end and the second clock
Source is connected；First logic sum gate, the first input end and the second input terminal of first logic sum gate are patrolled with described first respectively
It collects and is connected with the output end of the output end of door and second logical AND gate, the output end and the electricity of first logic sum gate
Lotus pump is connected.
Specifically, the second clock control unit includes: third logical AND gate, and the first of the third logical AND gate is defeated
Enter end and the second input terminal is connected with first signal receiving end and the tertiary clock source respectively；Counter, the counting
The input terminal of device is connected with the tertiary clock source, and the counter is described second for handling first clock signal
Clock signal；4th logical AND gate, the first input end and the second input terminal of the 4th logical AND gate are respectively with described second
Signal receiving end is connected with the output end of the counter；Second logic sum gate, the first input end of second logic sum gate
It is connected respectively with the output end of the output end of the third logical AND gate and the 4th logical AND gate with the second input terminal, it is described
The output end of second logic sum gate is connected with the charge pump.
To solve the above-mentioned problems, the embodiment of the invention also discloses a kind of nand memories, comprising: the first plane,
The device of two plane, charge pump and the described balance WL Voltage Establishment time, the device of the balance WL Voltage Establishment time with
The charge pump is connected.
The nand memory of the embodiment of the present invention and its device for balancing the WL Voltage Establishment time include following advantages: when right
When the first plane and the 2nd plane in nand memory are operated simultaneously, first is received by control signal receiving module
Signal is controlled, and when operating to the first plane or the 2nd plane, receives second by control signal receiving module
Signal is controlled, and then the first clock signal is exported to charge pump, Yi Jigen according to first control signal by clock control module
Second clock signal is exported to charge pump according to second control signal, wherein the frequency of second clock signal is believed less than the first clock
Number frequency.To accordingly adjust the driving capability of charge pump according to operation mode, realize the WL Voltage Establishment time in single plane
It is consistent when operation and double plane operations, extends the service life of nand memory.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional nand memory；
Fig. 2 is key signal schematic diagram of traditional nand memory in double plane operation modes；
Fig. 3 is key signal schematic diagram of traditional nand memory when individually operating to PLN1 '；
Fig. 4 is a kind of structural block diagram of the Installation practice of balance WL Voltage Establishment time of the invention；
Fig. 5 is a kind of structural schematic diagram of the Installation practice of balance WL Voltage Establishment time of the invention；
Fig. 6 is the device that nand memory has the balance WL Voltage Establishment time shown in fig. 5, operates mould in double plane
Key signal schematic diagram when formula；
Fig. 7 is the device that nand memory has the balance WL Voltage Establishment time shown in fig. 5, operates mould in single plane1
Key signal schematic diagram when formula；
Fig. 8 is the structural schematic diagram of the Installation practice of another balance WL Voltage Establishment time of the invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Referring to Fig. 4, a kind of structural block diagram of 1 embodiment of device of balance WL Voltage Establishment time of the invention is shown,
It can specifically include following module: control signal receiving module 10 and clock control module 20.Wherein, in nand memory
The first plane PLN0 and the 2nd plane PLN1 simultaneously when being operated i.e. double plane operation modes, control signal receives
Module 10 receives first control signal, and i.e. single when being operated to the first plane PLN0 or the 2nd plane PLN1
When plane operation mode, control signal receiving module 10 receives second control signal；The input terminal of clock control module 20 and control
Signal receiving module 10 processed is connected, and the output end of clock control module 20 is connected with the charge pump 2 of nand memory, clock control
Module 20 exports the first clock signal clk 1 according to first control signal, and exports second clock letter according to second control signal
Number CLK2；Frequency of the frequency of second clock signal CLK2 less than the first clock signal clk 1.
To realize in double plane operation modes, the device 1 of balance WL Voltage Establishment time controls 2 basis of charge pump
First clock signal clk 1 drives each capacitor (parasitic capacitance C in nand memoryCGA, parasitic capacitance CCG0, parasitic capacitance CCG1, post
Raw capacitor CWL0With parasitic capacitance CWL1), the driving capability of charge pump 2 is stronger；In single plane operation mode, WL voltage is balanced
The device 1 of settling time controls charge pump 2 and drives each capacitor (parasitic capacitance in nand memory according to second clock signal CLK2
CCGA, parasitic capacitance CCG0With parasitic capacitance CWL0Or parasitic capacitance CCGA, parasitic capacitance CCG1With parasitic capacitance CWL1), due to second
The frequency of clock signal clk 2 less than the first clock signal clk 1 frequency, at this point, the driving capability of charge pump 2 dies down.Specifically
The frequency on ground, second clock signal CLK2 can be 2/3rds or other ratios of the frequency of the first clock signal clk 1.
When due to single plane operation mode, the capacitor that charge pump 2 needs to drive is reduced, such as list plane1 operation mode
When, charge pump 2 needs the capacitor driven to reduce CCG0And CWL0, the recovery time of PUMP when single plane operation mode and WL1
The Voltage Establishment time relatively double plane operation modes when PUMP recovery time and the WL1 Voltage Establishment time will not become
Change.Similarly, when single plane0 operation mode, charge pump 2 needs the capacitor driven to reduce CCG1And CWL1, single plane operation mould
The recovery time and WL0 Voltage Establishment time of PUMP when formula relatively double plane operation modes when PUMP recovery time and
The WL0 Voltage Establishment time will not change.I.e. the WL Voltage Establishment time keeps in single plane operation and double plane operations
Unanimously, so as to extending the service life of nand memory.
Specifically, in one embodiment of the invention, referring to Fig. 5 and Fig. 8, control signal receiving module 10 may include
First signal receiving end 11 and second signal receiving end 12.Wherein, when control signal receiving module 10 receives first control signal
When, the first signal receiving end 11 is high level, and second signal receiving end 12 is low level；When control signal receiving module 10 receives
When second control signal, the first signal receiving end 11 is low level, and second signal receiving end 12 is high level.
Specifically, in one embodiment of the invention, referring to Fig. 5, clock control module 20 may include: the first clock
Source 21, second clock source 22 and the first clock control cell 23.Wherein, the first clock source 21 generates the first clock signal clk 1；
Second clock source 22 generates second clock signal CLK2；The input terminal of first clock control cell 23 is received with the first signal respectively
End 11, second signal receiving end 12, the first clock source 21 are connected with second clock source 22, the output of the first clock control cell 23
End is connected with charge pump 2, and the first clock control cell 23 exports the first clock signal clk 1, Yi Jigen according to first control signal
Second clock signal CLK2 is exported according to second control signal.
Specifically, referring to Fig. 5 and Fig. 8, in a specific embodiment of the present invention, nand memory has the embodiment of the present invention
Balance the WL Voltage Establishment time device 1, nand memory remove include balance the WL Voltage Establishment time device 1, first
Plane PLN0, the 2nd plane PLN1, charge pump 2, parasitic capacitance CCGA, parasitic capacitance CCG0, parasitic capacitance CCG1, parasitic electricity
Hold CWL0With parasitic capacitance CWL1It outside, can also include overall situation WL decoder cgdec, the first global control switch g_sw0, the first row
Address decoder BLKDEC0, the first WL driving switch WL_drv0, the second global control switch g_sw1, the decoding of the second row address
Device BLKDEC1, the 2nd WL driving switch WL_drv1.Wherein, the first plane PLN0 and the 2nd plane PLN1 are identical, and first
The global control switch g_sw1 of global control switch g_sw0 and second is identical, the first row address decoder BLKDEC0 and the second row
Address decoder BLKDEC1 is identical, and the first WL driving switch WL_drv0 and the 2nd WL driving switch WL_drv1 are identical.Fig. 5 and
In Fig. 8, RA0 is the input row address of the first row address decoder BLKDEC0, and RA1 is the second row address decoder BLKDEC1's
Input row address.
Wherein, when nand memory shown in fig. 5 is in double plane operation modes, key signal shows in nand memory
It is intended to as shown in fig. 6, when nand memory shown in fig. 5 is in single plane1 operation mode, key signal in nand memory
Schematic diagram is as shown in Figure 7.Wherein, PLNSEL0 is the operation signal of the first plane PLN0, and PLNSEL1 is the 2nd plane
The operation signal of PLN1, MPL are the level of the first signal receiving end 11, and SPL is the level of second signal receiving end 12, and CLK is
The output signal of first clock control cell 23, CGSEL are the control signal of overall situation WL decoder cgdec, and PUMP is charge pump 2
The driving signal of output, CGA are the output signal of overall situation WL decoder cgdec, and CG0 is the first global control switch g_sw0
Output signal, CG1 are the output signal of the second global control switch g_sw1, and WL0 is the defeated of the first WL driving switch WL_drv0
Voltage signal out, WL1 are the output voltage signal of the 2nd WL driving switch WL_drv1.
From Fig. 6 and Fig. 7 it can be found that nand memory shown in fig. 5, the recovery time of PUMP in double plane operation
Recovery time t71 and WL1 Voltage Establishment the time t72 of PUMP when t61 and WL1 Voltage Establishment time t62 and list plane1 is operated
Substantially it is consistent.
Specifically, in one embodiment of the invention, the first clock control cell 23 may include: the first logical AND
Door, the second logical AND gate and the first logic sum gate.Wherein, the first input end of the first logical AND gate and the second input terminal respectively with
First signal receiving end 11 is connected with the first clock source 21；The first input end of second logical AND gate and the second input terminal respectively with
Second signal receiving end 12 is connected with second clock source 22；The first input end of first logic sum gate and the second input terminal respectively with
The output end of the output end of first logical AND gate and the second logical AND gate is connected, the output end and charge pump 2 of the first logic sum gate
It is connected.
Specifically, in another embodiment of the present invention, referring to Fig. 8, when clock control module 20 may include: third
Clock source 24 and second clock control unit 25.Wherein, tertiary clock source 24 generates the first clock signal clk 1；Second clock control
The input terminal of unit 25 is connected with the first signal receiving end 11, second signal receiving end 12 and tertiary clock source 24 respectively, and second
The output end of clock control cell 25 is connected with charge pump 2, and second clock control unit 25 is according to first control signal output the
One clock signal CLK1, and the first clock signal clk 1 is handled according to second control signal, and export second clock
Signal CLK2.
Wherein, nand memory shown in Fig. 8 in double plane operation modes, build by the recovery time of PUMP and WL1 voltage
As shown in fig. 6, nand memory shown in Fig. 8 is in single plane1 operation mode between immediately, the recovery time of PUMP and WL1 electricity
Press settling time as shown in Figure 7.
Specifically, second clock control unit 25 may include: third logical AND gate, counter, the 4th logical AND gate and
Second logic sum gate.Wherein, the first input end of third logical AND gate and the second input terminal respectively with the first signal receiving end 11
It is connected with tertiary clock source 24；The input terminal of counter is connected with tertiary clock source 24, and counter is used for the first clock signal
CLK1 processing is second clock signal CLK2；The first input end and the second input terminal of 4th logical AND gate respectively with second signal
Receiving end 12 is connected with the output end of counter；The first input end of second logic sum gate and the second input terminal are patrolled with third respectively
It collects and is connected with the output end of the output end of door and the 4th logical AND gate, the output end of the second logic sum gate is connected with charge pump 2.
The device of the balance WL Voltage Establishment time of the embodiment of the present invention includes following advantages: in nand memory
When first plane and the 2nd plane is operated simultaneously, first control signal is received by control signal receiving module, and
When operating to the first plane or the 2nd plane, second control signal is received by control signal receiving module, in turn
By clock control module according to first control signal the first clock signal of output to charge pump, and according to second control signal
Second clock signal is exported to charge pump, wherein frequency of the frequency of second clock signal less than the first clock signal.To root
The driving capability of charge pump is accordingly adjusted according to operation mode, realizes the WL Voltage Establishment time in single plane operation and double plane behaviour
As when be consistent, extend the service life of nand memory.
The embodiment of the present invention also proposed a kind of nand memory, comprising: the first plane PLN0, the 2nd plane
The device 1 of PLN1, charge pump 2 and above-mentioned balance WL Voltage Establishment time, balance the device 1 and charge of WL Voltage Establishment time
Pump 2 is connected.
The nand memory of the embodiment of the present invention includes following advantages: the device by increasing the balance WL Voltage Establishment time
It accordingly adjusts the driving capability of charge pump according to operation mode, realizes the WL Voltage Establishment time in single plane operation and double
Plane is consistent when operating, and the service life is longer for nand memory.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases
This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
Above to a kind of device and a kind of nand memory for balancing the WL Voltage Establishment time provided by the present invention, carry out
It is discussed in detail, used herein a specific example illustrates the principle and implementation of the invention, above embodiments
Explanation be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art,
According to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion in this specification
Appearance should not be construed as limiting the invention.
Claims (7)
1. a kind of device for balancing the WL Voltage Establishment time characterized by comprising
Control signal receiving module, when in nand memory the first plane and the 2nd plane simultaneously operate when, institute
It states control signal receiving module and receives first control signal, and work as and 2nd plane of the first plane or described is grasped
When making, the control signal receiving module receives second control signal；
Clock control module, the input terminal of the clock control module are connected with the control signal receiving module, the clock
The output end of control module is connected with the charge pump of nand memory, and the clock control module is according to the first control signal
The first clock signal is exported, and second clock signal is exported according to the second control signal；The second clock signal
Frequency is less than the frequency of first clock signal.
2. the apparatus according to claim 1, which is characterized in that the control signal receiving module includes: that the first signal connects
Receiving end and second signal receiving end, wherein
When the control signal receiving module receives the first control signal, first signal receiving end is high level,
The second signal receiving end is low level；
When the control signal receiving module receives the second control signal, first signal receiving end is low level,
The second signal receiving end is high level.
3. the apparatus of claim 2, which is characterized in that the clock control module includes:
First clock source, first clock source generate first clock signal；
Second clock source, the second clock source generate the second clock signal；
First clock control cell, the input terminal of first clock control cell respectively with first signal receiving end, institute
State second signal receiving end, first clock source is connected with the second clock source, first clock control cell it is defeated
Outlet is connected with the charge pump, and first clock control cell exports first clock according to the first control signal
Signal, and the second clock signal is exported according to the second control signal.
4. the apparatus of claim 2, which is characterized in that the clock control module includes:
Tertiary clock source, the tertiary clock source generate first clock signal；
Second clock control unit, the input terminal of the second clock control unit respectively with first signal receiving end, institute
It states second signal receiving end to be connected with the tertiary clock source, the output end of the second clock control unit and the charge pump
It is connected, the second clock control unit exports first clock signal according to the first control signal, and according to institute
It states second control signal to handle first clock signal, and exports the second clock signal.
5. device according to claim 3, which is characterized in that first clock control cell includes:
First logical AND gate, the first input end and the second input terminal of first logical AND gate connect with first signal respectively
Receiving end is connected with first clock source；
Second logical AND gate, the first input end and the second input terminal of second logical AND gate connect with the second signal respectively
Receiving end is connected with the second clock source；
First logic sum gate, the first input end and the second input terminal of first logic sum gate respectively with first logical AND
The output end of door is connected with the output end of second logical AND gate, the output end of first logic sum gate and the charge pump
It is connected.
6. device according to claim 4, which is characterized in that the second clock control unit includes:
Third logical AND gate, the first input end and the second input terminal of the third logical AND gate connect with first signal respectively
Receiving end is connected with the tertiary clock source；
Counter, the input terminal of the counter are connected with the tertiary clock source, when the counter is used for described first
Clock signal processing is the second clock signal；
4th logical AND gate, the first input end and the second input terminal of the 4th logical AND gate connect with the second signal respectively
Receiving end is connected with the output end of the counter；
Second logic sum gate, the first input end and the second input terminal of second logic sum gate respectively with the third logical AND
The output end of door is connected with the output end of the 4th logical AND gate, the output end of second logic sum gate and the charge pump
It is connected.
7. a kind of nand memory characterized by comprising the first plane, the 2nd plane, charge pump and according to claim
Described in any one of 1-6 balance the WL Voltage Establishment time device, it is described balance the WL Voltage Establishment time device with it is described
Charge pump is connected.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890688A (en) * | 2011-07-28 | 2014-06-25 | 奈特力斯公司 | Flash-dram hybrid memory module |
| CN105097026A (en) * | 2014-05-14 | 2015-11-25 | 爱思开海力士有限公司 | Semiconductor memory device |
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| JP2002304886A (en) * | 2001-04-06 | 2002-10-18 | Nec Corp | Semiconductor memory |
| KR101012887B1 (en) * | 2009-06-30 | 2011-02-08 | 주식회사 하이닉스반도체 | Operating method of nonvolatile memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890688A (en) * | 2011-07-28 | 2014-06-25 | 奈特力斯公司 | Flash-dram hybrid memory module |
| CN105097026A (en) * | 2014-05-14 | 2015-11-25 | 爱思开海力士有限公司 | Semiconductor memory device |
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