CN105529826B - A kind of portable simulation intelligent cell based on PXI buses - Google Patents
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Abstract
The present invention provides a kind of portable simulation intelligent cell based on PXI buses, the intelligent cell includes PXI cabinets, network interface board, time service unit plate, analog acquisition plate, On-off signal plate and operation circuit plate, and PXI cabinets, network interface board and time service unit plate are connect with analog acquisition plate, On-off signal plate and operation circuit plate by PXI buses.Portable simulation intelligent cell provided by the invention integrates combining unit, intelligent terminal, time service unit three zones, and configuration method is easier, and the test for protection, measure and control device provides simple and efficient test environment.
Description
Technical field
The present invention relates to a kind of simulation intelligent cell, in particular to a kind of portable simulation intelligence based on PXI buses
Unit.
Background technology
In intelligent substation, the debugging test of bay device, which generally requires the cooperations of more complete equipments, to be completed.Such as intelligence
The secondary devices such as protection, the observing and controlling of energy substation need access to meet the mould of IEC61850 standards when carrying out single device debugging
Analog quantity sampling value signal SMV, open into signal (including switch and disconnecting link position signal, pressing plate signal etc.), output signal (switch and
The divide-shut brake signal of disconnecting link) and clock synchronization signal (generally using B codes) etc..
SMV samples value signal and is generally provided by digital protective relay tester at present, but digital protecting is surveyed
It is expensive to try instrument, operation is relative complex;On the other hand, protection, measure and control device test when need intelligent terminal offer open into, open
Go out cooperation, according to test event, selective short circuit, simulation intake position are carried out to the intake of intelligent terminal.This operation
Mode needs frequently to change the configuration and wiring of intelligent terminal, and test job amount is big and error-prone.In addition, also needing to configure specially
Clock synchronization equipment provides clock synchronization signal for equipment under test etc..
Test needs more set test equipments that the debugging calibration tape to equipment such as intelligent substation protection, observing and controlling is coordinated to come not
Just, it needs to build relative complex test environment, testing efficiency is low, to the more demanding of tester.
Invention content
To solve above-mentioned deficiency of the prior art, the object of the present invention is to provide a kind of based on the portable of PXI buses
Intelligent cell is simulated, which integrates combining unit, intelligent terminal, time service unit three zones,
Configuration method is easier, and the test for protection, measure and control device provides simple and efficient test environment.
The purpose of the present invention is what is realized using following technical proposals:
A kind of portable simulation intelligent cell based on PXI buses, the intelligent cell include PXI cabinets, network interface
Plate, time service unit plate, analog acquisition plate, On-off signal plate and operation circuit plate, it is improved in that the PXI machines
Case, network interface board and time service unit plate by PXI buses with analog acquisition plate, On-off signal plate and operation circuit plate
Connection.
Wherein, the PXI cabinets include the system controller being connected with each other and PXI platforms, and the system controller is just
The master controller for taking formula simulation intelligent cell completes logic judgment, operation circuit plate is driven, to going out for receiving GOOSE message
Mouth relay is controlled, the status information of read switch amount tablet, and controls the association of network interface board and time service unit plate
With work.
Wherein, the network interface board is the network interface board based on FPGA, including following function:1. passing through PXI buses
Receive the sampled value sent of analog acquisition plate, the SMV modules of network interface board are according to IEC61850-9-2 formats by sampled value
After data are packaged, exported to protection supervisory equipment in the form of optical Ethernet;2. receiving externally input GOOSE message, parse
System controller is transmitted to by PXI buses afterwards, and defeated in the form of Ethernet after the GOOSE message of system controller is packaged
Go out;
The network interface board includes bus control unit, the first FPGA module, Ethernet PHY chip, crystal oscillator, Double Data Rate
Synchronous DRAM DDR and front plate interface;The front plate interface is connect with protection supervisory equipment;The front panel
Interface, Ethernet PHY chip and the first FPGA module are sequentially connected;The bus control unit respectively with the first FPGA module and
PXI buses connect;First FPGA module is connect with PXI buses;The crystal oscillator and the storage of Double Data Rate synchronous dynamic random
Device DDR is connect with the first FPGA module;
First FPGA module includes the MAC Address module, GOOSE modules, SMV moulds controlled by the first fpga chip
Block, DDR controller and expansion bus driving;The MAC Address module is connect with GOOSE modules and SMV modules respectively.
Wherein, the time service unit plate include the 2nd FGPA modules, the 2nd FGPA modules respectively with satellite antenna and
Constant-temperature crystal oscillator connects;
The 2nd FGPA modules include GPS module, coding module and the punctual module controlled by the second fpga chip;Institute
It states GPS module and punctual module is connect with coding module;The GPS module receives satellite-signal, output by satellite antenna
Pps pulse per second signal and temporal information, coding module generate B code data flows according to the format of regulation, are exported by interface driving circuit
The B codes of light B codes and RS485 formats;The sampling pulse that pulse per second (PPS) frequency dividing is 4000Hz is issued analog quantity and adopted by the coding module
Collect plate, first pulse and the pulse per second (PPS) stringent synchronization of the sampling pulse;If not connecing satellite antenna, the GPS module will not
Pulse per second (PPS) is exported, the second of external constant-temperature crystal oscillator is rushed after signal frequency split and used as standard pulse per second (PPS) by the punctual module.
Wherein, after the analog acquisition plate is used to the signal of conventional voltage/current mutual inductor carrying out isolation conditioning
Digital signal is converted to, and network interface board is sent to by PXI buses;
The analog acquisition plate includes sequentially connected front plate interface, mutual inductor, A/D chips and the 3rd FPGA moulds
Block;
The third FPGA module include the first switch amount scan module controlled by third fpga chip, computing module,
First event journal module and first disappears and trembles module;
The first switch amount scan module is used to scan the variation of each switching value, stamps timestamp;Described first disappears
It trembles module and trembles processing for doing to disappear to the shake of intake, invalid place is done less than the switching value variation for trembling the time that disappears for shaking
Reason;The first event journal module (SOE) to form SOE records for changing to each effective switching value, every note
Record includes the number of switching value, the time (being accurate to ms) of variation beginning and the level state after variation;
The voltage and current signals introduced from the external terminal of the third FPGA module are converted by the isolation of mutual inductor,
After filtering and amplification, it is sent to A/D chips;The 4000Hz synchronized samplings for coming from time service unit plate are received by fpga chip
Pulse controls the sampling instant of A/D chips according to sampling pulse, after computing module receives the sampled value of A/D, by calculating and beating
Network interface board is issued after packet, the network interface board issues protection supervisory equipment with the format of IEC61850-9-2.
Wherein, the On-off signal plate is by sequentially connected signal conditioning circuit, isolation circuit and the 4th FPGA module
Composition;
4th FPGA module includes the second switch amount scan module controlled by the 4th fpga chip, second disappears and tremble mould
Block and second event journal module;
The remote signals inputted from terminal after filtering and shaping, are sent to after current-limiting circuit and Phototube Coupling
The scan module of FPGA, the state of FPGA scanning switch amounts are done after disappearing and trembling processing, then generate SOE events letter after stamping timestamp
Breath, system controller is issued by PXI buses.
Wherein, the operation circuit plate is made of operation circuit, isolation circuit and the 5th FPGA module;The isolation circuit
It is connect respectively with operation circuit and the 5th FPGA module;5th FPGA module includes the DO moulds controlled by the 5th fpga chip
Block, third, which disappear, trembles module and third sequence of events recording module;
The DO modules receive the control information that system controller is sent by PXI buses and pass through driving after decoding
The corresponding relay of circuit control, to realize the control of breaker, disconnecting link equipment;And by isolation circuit, scan electric system
The state of primary equipment is disappeared by third and is trembled after module does and disappear and tremble processing, issued third sequence of events recording module and generate SOE things
Part information issues system controller finally by PXI buses.
The excellent effect that technical solution provided by the invention has is:
The present invention provides the integrated simulation intelligent cells for integrating combining unit, intelligent terminal and time service unit
Design method, which uses the standard PC case based on PXI, and each board uses standard inter-board interface, versatile,
Upgrading is convenient.Without daemon software, it is only necessary to web browser can complete twin installation configuration, control and text
The work such as part upload.Using the equipment, when being protected to intelligent substation, measure and control device being tested, it is only necessary to it is traditional
Analog protection tester cooperation, so that it may to complete the detection of secondary device.Intelligent substation secondary is simplified using the device
The test environment of equipment is real using traditional relay protection tester without relying on digital protecting tester, time service equipment etc.
The test of the various kinds of equipment of existing intelligent substation is provided convenience condition, convenient for Field Force's application and management service.
Description of the drawings
Fig. 1 is portable simulation intelligent cell board schematic diagram provided by the invention;
Fig. 2 is time service unit plate structure schematic diagram provided by the invention;
Fig. 3 is analog input plate structure schematic diagram provided by the invention;
Fig. 4 is On-off signal plate structure schematic diagram provided by the invention;
Fig. 5 is operation circuit plate structure schematic diagram provided by the invention;
Fig. 6 is network interface plate structure schematic diagram provided by the invention;
Fig. 7 is general function structural schematic diagram provided by the invention;
Fig. 8 is Web configuration features structural schematic diagram provided by the invention.
Specific implementation mode
The specific implementation mode of the present invention is described in further detail below in conjunction with the accompanying drawings.
The following description and drawings fully show specific embodiments of the present invention, to enable those skilled in the art to
Put into practice them.Other embodiments may include structure, logic, it is electrical, process and other change.Embodiment
Only represent possible variation.Unless explicitly requested, otherwise individual component and function are optional, and the sequence operated can be with
Variation.The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.This hair
The range of bright embodiment includes equivalent obtained by the entire scope of claims and all of claims
Object.Herein, these embodiments of the invention can individually or generally be indicated that this is only with term " invention "
For convenience, it and if in fact disclosing the invention more than one, is not meant to automatically limit ranging from appointing for the application
What single invention or inventive concept.
Portable simulation intelligent cell based on PXI buses, including PXI cabinets and 5 blocks of peripheral plug-in units are (based on FPGA's
Network interface board, time service unit plate, analog acquisition plate, operation circuit plate, On-off signal plate), as shown in Figure 1.The PXI
Cabinet, network interface board and time service unit plate by PXI buses with analog acquisition plate, On-off signal plate and operation circuit
Plate connects.
PXI cabinets include PXI platforms and system controller.The PXI cabinets that PXI cabinets select NI companies ready-made are a whole set of
The main control part of device, the device of control containing system and power supply.Remaining board is autonomous Design.PXI(PCI extensions for
Instrumentation, the PCI extensions towards instrument system) it is a kind of measurement based on PC issued by NI companies and automatic
Change platform, there is high performance backsheet and secured and reliable mechanical encapsulation.
System controller:For receiving GOOSE message, logic judgment is completed, operation circuit plate is driven, to exit relay
It is controlled, reads the status information opened into plate, and control the collaborative work of network interface board, time service unit plate.
Time service unit plate is as shown in Fig. 2, its effect is to provide the benchmark of time for package unit, while external outputting standard
Clock synchronization signal, including B codes, pulse per second (PPS), SNTP, to meet requirement of each test system to time precision.Time service unit plate
The temporal information of generation is sent to each slot by the Trigger Bus of PXI, and interval is 1ms, while it is 4000Hz's to generate frequency
Lock-out pulse is sent to analog acquisition plate as sampling pulse.The B code signals externally exported can be that the devices such as protection, observing and controlling carry
For clock synchronization signal, interface type is optical fiber ST interfaces and power port 485, facilitates field connection.
Time service unit plate includes the 2nd FGPA modules, and the 2nd FGPA modules connect with satellite antenna and constant-temperature crystal oscillator respectively
It connects;2nd FGPA modules include GPS module, coding module and punctual module;The GPS module and punctual module with coding mould
Block connects.
GPS module receives satellite-signal by antenna, exports pps pulse per second signal and temporal information, the coding module in FPGA
The data flow that B codes are generated according to the format of regulation, passes through the B codes of driving circuit output light B codes and RS485 formats.Meanwhile it encoding
The sampling pulse that pulse per second (PPS) frequency dividing is 4000Hz is issued analog acquisition plate by module, first pulse of the sampling pulse be with
Pulse per second (PPS) stringent synchronization.If not connecing satellite antenna, GPS module will not export pulse per second (PPS), in this case, keeping in FPGA
When module the second of external constant-temperature crystal oscillator can be rushed to signal frequency split after used as standard pulse per second (PPS).
The function of analog acquisition plate is converted to after the signal of conventional voltage/current mutual inductor is carried out isolation conditioning
Digital signal, and network interface board is sent to by PXI local bus.As shown in figure 3, analog acquisition plate is used for routine
The signal of voltage/current mutual inductor is converted to digital signal after carrying out isolation conditioning, and is sent to network interface by PXI buses
Plate;The analog acquisition plate includes sequentially connected front plate interface, mutual inductor, A/D chips and third FPGA module;It is described
Third FPGA module includes first switch amount scan module, computing module, the first event sequence controlled by third fpga chip
Logging modle and first disappears and trembles the operation of module;The first switch amount scan module is used to scan the variation of each switching value,
Stamp timestamp;Described first, which disappears, trembles module and trembles processing for doing to disappear to the shake of intake, and the time is trembled less than disappearing for shake
Switching value variation do invalidation;The first event journal module (SOE) is used for each effective switch quantitative change
Change forms SOE records, and every record includes the number of switching value, the time (being accurate to ms) of variation beginning and the level after variation
State;
Voltage, the current signal introduced from the external terminal of third FPGA module, after the isolation conversion of mutual inductor, then
After filtered, amplification, it is sent to A/D chips.Time service unit plate is come from by the fpga chip reception in third FPGA module
4000Hz Synchronous Sampling Pulses, according to the sampling instant of Pulse Width Control A/D chips, computing module receives the sampling of A/D chips
After value, network board is issued after calculating, being packaged, protection, measuring and controlling equipment are issued with the format of IEC61850-9-2.
On-off signal plate is made of sequentially connected signal conditioning circuit, isolation circuit and the 4th FPGA module;It is described
4th FPGA module includes the second switch amount scan module controlled by the 4th fpga chip, second disappears and tremble module and second event
Journal module;As shown in figure 4, from the remote signals that terminal inputs, after current-limiting circuit and Phototube Coupling, using filter
After wave and shaping, it is sent to the scan module of FPGA, the state of FPGA scanning switch amounts is done after disappearing and trembling processing, then stamps timestamp
SOE event informations are generated afterwards, and system controller is issued by PXI buses.
Operation circuit plate is made of operation circuit, isolation circuit and FPGA.As shown in figure 5, operation circuit plate is by operating back
Road, isolation circuit and the 5th FPGA module composition;The isolation circuit is connect with operation circuit and the 4th FPGA module respectively;Institute
It includes that the DO modules controlled by the 5th fpga chip, third disappear and tremble module and third sequence of events recording mould to state the 5th FPGA module
Block;
The DO modules receive the control information that system controller is sent by PXI buses and pass through driving after decoding
Circuit controls corresponding relay, to realize the control of the equipment such as breaker, disconnecting link.Meanwhile passing through isolation circuit, scanning one
The state of secondary device is done after disappearing and trembling processing, generates SOE event informations, system controller is issued by PXI buses.
Network board is as shown in fig. 6, function is as follows:On the one hand the sampling that analog input is sent is received by PXI buses
Value after sample values are packaged by SMV modules according to IEC61850-9-2 formats, are exported in the form of optical Ethernet and is surveyed to protection
Control device;On the other hand it is to receive externally input GOOSE message, system controller is transmitted to by PXI buses after parsing, together
When, it will be exported in the form of Ethernet after the GOOSE information packages of system controller.
Network interface board includes bus control unit, the first FPGA module, Ethernet PHY chip, crystal oscillator, Double Data Rate synchronization
Dynamic RAM DDR and front plate interface;The front plate interface is connect with protection supervisory equipment;The front panel connects
Mouth, Ethernet PHY chip and the first FPGA module are sequentially connected;The bus control unit respectively with the first FPGA module and PXI
Bus connects;First FPGA module is connect with PXI buses;The crystal oscillator and Double Data Rate synchronous DRAM
DDR is connect with the first FPGA module;First FPGA module include the first fpga chip, MAC Address module, GOOSE modules,
SMV modules, DDR controller and expansion bus driving;The first fpga chip control MAC Address module, GOOSE modules, SMV
Module, DDR controller and expansion bus driving;The MAC Address module is connect with GOOSE modules and SMV modules respectively.
Portable simulation intelligent cell provided by the invention based on PXI buses, uses matching based on Web Service
Method is set, as shown in figure 8, daemon software is not needed, as long as user completes the control to the present apparatus by web browser
System realizes the functions such as parameter configuration, configuration file are downloaded, file uploads.This configuration method is total by Apache+MySQL+
Enjoy what the mode of memory was realized, wherein Apache is HTTP Server, and the mode of it and the swapping data of application program has
Two kinds, it is based on MySQL database mode and shared drive mode.
The above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, although with reference to above-described embodiment pair
The present invention is described in detail, those of ordinary skill in the art still can to the present invention specific implementation mode into
Row modification either equivalent replacement these without departing from any modification of spirit and scope of the invention or equivalent replacement, applying
Within the claims of the pending present invention.
Claims (6)
1. a kind of portable simulation intelligent cell based on PXI buses, the intelligent cell include PXI cabinets, network interface board,
Time service unit plate, analog acquisition plate, On-off signal plate and operation circuit plate, which is characterized in that the PXI cabinets, network
Interface board and time service unit plate are connect with analog acquisition plate, On-off signal plate and operation circuit plate by PXI buses;
The network interface board is the network interface board based on FPGA, including following function:1. receiving analog quantity by PXI buses
The sampled value that collection plate is sent, after sample values are packaged by the SMV modules of network interface board according to IEC61850-9-2 formats,
It is exported to protection supervisory equipment in the form of optical Ethernet;2. externally input GOOSE message is received, it is total by PXI after parsing
Line is transmitted to system controller, and is exported in the form of Ethernet after the GOOSE message of system controller is packaged;
The network interface board includes bus control unit, the first FPGA module, Ethernet PHY chip, crystal oscillator, Double Data Rate synchronization
Dynamic RAM DDR and front plate interface;The front plate interface is connect with protection supervisory equipment;The front panel connects
Mouth, Ethernet PHY chip and the first FPGA module are sequentially connected;The bus control unit respectively with the first FPGA module and PXI
Bus connects;First FPGA module is connect with PXI buses;The crystal oscillator and Double Data Rate synchronous DRAM
DDR is connect with the first FPGA module;
First FPGA module includes the MAC Address module controlled by the first fpga chip, GOOSE modules, SMV modules, DDR
Controller and expansion bus driving;The MAC Address module is connect with GOOSE modules and SMV modules respectively.
2. portable simulation intelligent cell as described in claim 1, which is characterized in that the PXI cabinets include being connected with each other
System controller and PXI platforms, the system controller be portable simulation intelligent cell master controller, for receiving
GOOSE message completes logic judgment, drives operation circuit plate, controls exit relay, read switch amount tablet
Status information, and control the collaborative work of network interface board and time service unit plate.
3. portable simulation intelligent cell as described in claim 1, which is characterized in that the time service unit plate includes second
FGPA modules, the 2nd FGPA modules are connect with satellite antenna and constant-temperature crystal oscillator respectively;
The 2nd FGPA modules include GPS module, coding module and the punctual module controlled by the second fpga chip;It is described
GPS module and punctual module are connect with coding module;The GPS module receives satellite-signal by satellite antenna, exports the second
Pulse signal and temporal information, coding module generate B code data flows according to the format of regulation, pass through interface driving circuit output light
The B codes of B codes and RS485 formats;The sampling pulse that pulse per second (PPS) frequency dividing is 4000Hz is issued analog acquisition by the coding module
Plate, first pulse and the pulse per second (PPS) stringent synchronization of the sampling pulse;If not connecing satellite antenna, the GPS module will not be defeated
Go out pulse per second (PPS), the second of external constant-temperature crystal oscillator is rushed after signal frequency split and used as standard pulse per second (PPS) by the punctual module.
4. portable simulation intelligent cell as described in claim 1, which is characterized in that the analog acquisition plate is used for will be normal
The signal of the voltage/current mutual inductor of rule is converted to digital signal after carrying out isolation conditioning, and is sent to network by PXI buses
Interface board;
The analog acquisition plate includes sequentially connected front plate interface, mutual inductor, A/D chips and third FPGA module;
The third FPGA module includes the first switch amount scan module controlled by third fpga chip, computing module, first
Sequence of events recording module and first disappears and trembles module;
The first switch amount scan module is used to scan the variation of each switching value, stamps timestamp;Described first, which disappears, trembles mould
Block trembles processing for doing to disappear to the shake of intake, and invalidation is done less than the switching value variation for trembling the time that disappears for shaking;Institute
It states first event journal module to form SOE records for changing each effective switching value, every record includes switch
The number of amount, the time of variation beginning and the level state after variation;
The voltage and current signals introduced from the external terminal of the third FPGA module are converted by the isolation of mutual inductor, then are passed through
After crossing filtering and amplification, it is sent to A/D chips;The 4000Hz synchronized sampling arteries and veins for coming from time service unit plate is received by fpga chip
Punching controls the sampling instant of A/D chips according to sampling pulse, after computing module receives the sampled value of A/D, by calculating and being packaged
After issue network interface board, the network interface board issues protection supervisory equipment with the format of IEC61850-9-2.
5. portable simulation intelligent cell as described in claim 1, which is characterized in that the On-off signal plate by connecting successively
Signal conditioning circuit, isolation circuit and the 4th FPGA module composition connect;
4th FPGA module include the second switch amount scan module controlled by the 4th fpga chip, second disappear tremble module and
Second event journal module;
The remote signals inputted from terminal after filtering and shaping, are sent to second after current-limiting circuit and Phototube Coupling
Switching value scan module, the state of the 4th fpga chip scanning switch amount are done after disappearing and trembling processing, then are generated after stamping timestamp
SOE event informations issue system controller by PXI buses.
6. portable simulation intelligent cell as described in claim 1, which is characterized in that the operation circuit plate is by operating back
Road, isolation circuit and the 5th FPGA module composition;The isolation circuit is connect with operation circuit and the 5th FPGA module respectively;Institute
It includes that the DO modules controlled by the 5th fpga chip, third disappear and tremble module and third sequence of events recording mould to state the 5th FPGA module
Block;
The DO modules receive the control information that system controller is sent by PXI buses and pass through driving circuit after decoding
Corresponding relay is controlled, to realize the control of breaker, disconnecting link equipment;And by isolation circuit, scanning electric system is primary
The state of equipment is disappeared by third and is trembled after module does and disappear and tremble processing, issued third sequence of events recording module and generate SOE events letter
Breath, system controller is issued finally by PXI buses.
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CN109656175A (en) * | 2018-12-26 | 2019-04-19 | 大唐巴彦淖尔风力发电有限责任公司 | Wind-powered electricity generation investigating method based on PXI bussing technique |
CN110737559A (en) * | 2019-10-22 | 2020-01-31 | 浙江中控技术股份有限公司 | SOE function automatic test system and method |
CN111722031A (en) * | 2020-05-13 | 2020-09-29 | 广州市扬新技术研究有限责任公司 | Direct current traction protection tester device based on FPGA |
CN114189352A (en) * | 2021-10-28 | 2022-03-15 | 河北汉光重工有限责任公司 | SNTP protocol-based data link interface device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201886122U (en) * | 2010-11-19 | 2011-06-29 | 中国电子科技集团公司第十四研究所 | PXI (PCI extension for instrumentation) bus-based digital testing module |
CN202904367U (en) * | 2012-06-12 | 2013-04-24 | 湖北三江航天红峰控制有限公司 | A testing system based on a PXI bus |
-
2015
- 2015-06-30 CN CN201510373841.1A patent/CN105529826B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201886122U (en) * | 2010-11-19 | 2011-06-29 | 中国电子科技集团公司第十四研究所 | PXI (PCI extension for instrumentation) bus-based digital testing module |
CN202904367U (en) * | 2012-06-12 | 2013-04-24 | 湖北三江航天红峰控制有限公司 | A testing system based on a PXI bus |
Non-Patent Citations (1)
Title |
---|
《基于PXI总线技术的综合测试仪研制与实现》;郭庆;《CNKI优秀硕士学位论文全文库》;20121231;第8-10页 * |
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CN105529826A (en) | 2016-04-27 |
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