CN105512071B - High speed interface host-side controller - Google Patents
High speed interface host-side controller Download PDFInfo
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- CN105512071B CN105512071B CN201510894510.2A CN201510894510A CN105512071B CN 105512071 B CN105512071 B CN 105512071B CN 201510894510 A CN201510894510 A CN 201510894510A CN 105512071 B CN105512071 B CN 105512071B
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- logical network
- physical layer
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- clock signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3802—Harddisk connected to a computer port
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The host-side controller of low data dithering, low speed data is provided with logical network layer, transfers to electronic physical layer to be converted to high speed data delivery to external device (ED) via across time domain data transport module.The clock signal of the electronic physical layer operation is also transferred to the logical network layer, the logical network layer is provided first low speed data according to this.It is the low speed data that the external device (ED) provides that across the time domain data transport module reads in the logical network layer according to logical network layer end clock, and exports first low speed data to the electronic physical layer according to electronic physical layer end clock.
Description
Technical field
The present invention relates to high speed interface host-side controller, more particularly to make the high speed of high-speed transfer with external device (ED)
Data-interface host-side controller.
Background technology
High speed interface, such as：Serial Advanced Technology Attachment (SATA), peripheral interconnection standard (PCIE), safe number
Word input/output cards (SDIO), USB (USB) etc., it is easy to because clock signal is delayed, and data dithering occurs；
Significantly affect high speed data transfer.
The content of the invention
The present invention provides a kind of host-side controller of low data dithering (host controller), can also chipset
South bridge realize.
A kind of high speed interface host-side controller realized according to one embodiment of the present invention, including logical physical
Layer, electronic physical layer and across time domain data transport module.The logical network layer provides the first low speed data, then by the electronics
Physical layer conversion is the first high-speed data, and is transferred to the first external device (ED).The clock signal of the electronic physical layer operation is also
The logical network layer is transferred to, the logical network layer is provided first low speed data according to this.Should across time domain data transmission mould
Block is coupled between the logical network layer and the electronic physical layer, and the logical physical is read according to logical network layer end clock
First low speed data that layer provides for first external device (ED), and it is low according to electronic physical layer end clock output described first
Fast data are to the electronic physical layer.
Across the time domain data transport module of the present invention effectively solves operating clock in electronic physical layer end and logical network layer
The asynchronous problem at end.
Special embodiment below, and coordinate appended diagram, describe present invention in detail.
Brief description of the drawings
Fig. 1 is block diagram, describes the high speed interface host-side controller realized according to one embodiment of the present invention
100；
Fig. 2A, Fig. 2 B illustrate across time domain data transport module TXCDC according to one embodiment of the present invention；
Fig. 3 illustrates caching R_A1 operations with oscillogram, wherein the buffer of caching R_A1 numberings 0~7 is respectively designated as R_
A1_0~R_A1_7；And
Fig. 4 is block diagram, describes the host-side controller 400 realized according to one embodiment of the present invention, is with single
At least one external device of electronic physical layer EPHY connections.
Embodiment
The various embodiments described below for enumerating the present invention.The basic conception described below for introducing the present invention, and not anticipate
Figure limitation present invention.Actual invention scope should define according to claims.
Fig. 1 is block diagram, describes the high speed interface host-side controller realized according to one embodiment of the present invention
100.High speed interface host-side controller 100 (numbers same logical network layer (logical including logical network layer LPHY
Physical layer) abbreviation LPHY), multiple electronic physical layers (electrical physical layer, abridge EPHY)
EPHYA and EPHYB, multiplexer ECLKMUX and across time domain data transport module TXCDC.Two electronics are only shown in Fig. 1
Physical layer, but the present invention is not limited thereto.
Electronic physical layer EPHYA and EPHYB connection external device (ED)；Electronic physical layer EPHYA connection hard disk HDA1 with
HDA2, and electronic physical layer EPHYB connection hard disks HDB1 and HDB2.Electronic physical layer EPHYA and EPHYB believes according to clock respectively
Number MPLLCLK_A and MPLLCLK_B is operated；Clock signal MPLLCLK_A can be produced by electronic physical layer EPHYA inside, and when
Clock signal MPLLCLK_B can be by producing inside electronic physical layer EPHYB.It is worth noting that, the electronic physical layer in Fig. 1
EPHYA and EPHYB only connects two hard disks, but the present invention is not intended to limit the outside that each electronic physical layer is connected herein
The type and quantity of device.
Multiplexer ECLKMUX receive clock signal MPLLCLK_A corresponding to electronic physical layer EPHYA and EPHYB with
MPLLCLK_B, and export common clock signal MPLLCLK_COM.Common clock signal MPLLCLK_COM is introduced into the logic thing
Manage layer LPHY and be somebody's turn to do across time domain data transport module TXCDC.
For hard disk HDA1, HDA2, HDB1 and HDB2, in logical network layer LPHY respectively with circuit module PHYA1,
PHYA2, PHYB1 and PHYB2 be based on common clock signal MPLLCLK_COM provide low speed data DA1_COM, DA2_COM,
DB1_COM, DB2_COM are transferred to across the time domain data transport module TXCDC.
Across time domain data transport module TXCDC be coupled to logical network layer LPHY and electronic physical layer EPHYA and EPHYB it
Between, it is based on across Time-Domain Technique (clock domain crossing) operation.Across time domain data transport module TXCDC according to
Common clock signal MPLLCLK_COM reads in above-mentioned low speed data DA1_COM, DA2_ of logical network layer LPHY offers
COM、DB1_COM、DB2_COM.In one embodiment, across time domain data transport module TXCDC be the external device (ED) HDA1,
HDA2, HDB1 each provide a caching (being plotted in Fig. 2A, Fig. 2 B) from HDB2 to cache the low speed data of corresponding different external device (ED)s.
Across time domain data transport module TXCDC is always according to clock signal (electronics corresponding to corresponding electronic physical layer EPHYA and EPHYB
Physical layer EPHYA corresponds to clock signal MPLLCLK_A, electronic physical layer EPHYB corresponds to clock signal MPLLCLK_B) respectively will
The low speed data of above-mentioned caching takes out.Referenced in schematic, the low speed data DA1_A according to clock signal MPLLCLK_A taking-ups is by electricity
Muon physics layer EPHYA is sent to hard disk HDA1 after being converted to high-speed data, the low speed number taken out according to clock signal MPLLCLK_A
Sent after being converted to high-speed data by electronic physical layer EPHYA according to DA2_A to hard disk HDA2, according to clock signal MPLLCLK_B
The data DB1_B of taking-up is sent to hard disk HDB1 after being converted to high-speed data by electronic physical layer EPHYB, according to clock signal
The data DB2_B that MPLLCLK_B takes out is sent to hard disk HDB2 after being converted to high-speed data by electronic physical layer EPHYB.Especially
It is that each caching has multilayer caching depth so that low speed data reads in caching and data read-out caching is able to across time domain realization.
As shown in figure 1, reduction is set according to the common clock signal MPLLCLK_COM logical network layer LPHY operated merely
Count threshold.The difference of the different electronic physical layer (such as EPHYA and EPHYB) of the logical network layer LPHY of conventional art correspondence
Circuit module (such as PHYA1, PHYA2 and PHYB1, PHYA2) according to the clock signals of different electronic physical layers (such as
MPLLCLK_A and MPLLCLK_B) operation, due to clock signal (such as the MPLLCLK_A and MPLLCLK_ of each electronic physical layer
B it is) asynchronous clock signal, Clock Tree (Clock Tree) will be caused complicated, and the present invention is merely according to common clock signal
The logical network layer LPHY of MPLLCLK_COM operations will greatly simplify Clock Tree.In addition, it is arranged at logical network layer LPHY and electricity
Across time domain data transport module TXCDC between muon physics layer EPHYA and EPHYB will effectively suppress cabling latency issue.Compare
Logical network layer directly couples to the long cabling of electronic physical layer in conventional art, across time domain data transport module TXCDC is by number
Half is cut according to cabling, corrects cabling delay in time.
In one embodiment, clock signal MPLLCLK_A and MPLLCLK_B cable run distances will be used for judging electronics thing
Reason layer EPHYA and EPHYB which near logical network layer LPHY.Fig. 1 is that electronic physical layer EPHYA is nearest electronics thing
Manage layer.Multiplexer ECLKMUX is used as the common clock signal using nearest electronic physical layer EPHYA clock signal MPLLCLK_A
MPLLCLK_COM, make the clock signal MPLLCLK_A of less cabling delay used in logical network layer LPHY.It is noticeable
It is that in one embodiment, cable run distance here refers in application specific integrated circuit (Application Specific
Integrated Circuits, ASIC) in clock signal MPLLCLK_A and MPLLCLK_B from electronic physical layer EPHYA and
EPHYB to multiplexer ECLKMUX cable run distance.In the foregoing embodiment, selected altogether according to the cable run distance of clock signal
It based on clock signal MPLLCLK_A and MPLLCLK_B is frequency identical asynchronous clock to be with clock signal MPLLCLK_COM
Under the premise of, if clock signal MPLLCLK_A and MPLLCLK_B frequencies itself are difference, can otherwise select common
Clock signal MPLLCLK_COM, refer to aftermentioned.
In a kind of embodiment, across time domain data transport module TXCDC to logical network layer LPHY cabling (transmission DA1_
COM, DA2_COM, DB1_COM, DB2_COM) distance is designed as being shorter than nearest electronic physical layer EPHYA to logical network layer LPHY
Distance, or even should across time domain data transport module TXCDC to nearest electronic physical layer EPHYA cable run distance (transmission DA1_
A, DA2_A, DB1_B, DB2_B) it is also configured as the distance that is shorter than the nearest electronic physical layer EPHYA to logical network layer LPHY.
It is so designed that gist will make it that the amendment that across time domain data transport module TXCDC is delayed to data cabling is more accurate.
In a kind of embodiment, logical network layer LPHY provide in a parallel fashion low speed data DA1_COM, DA2_COM,
DB1_COM, DB2_COM extremely across time domain data transport module TXCDC, across time domain data transport module TXCDC are sent out in a parallel fashion
Low speed data DA1_A, DA2_A, DB1_B, DB2_B are sent to electronic physical layer EPHYA and EPHYB, and electronic physical layer EPHYA
And EPHYB includes data DA1_A, DA2_A, DB1_B, DB2_B being converted to serial high speed (example from parallel low speed data
Such as differential signal) after just transmit to hard disk HDA1, HDA2, HDB1 and HDB2.It is designed so that the logical network layer of low speed
LPHY is combined with the electronic physical layer EPHYA and EPHYB of high speed, beneficial to high speed interface is realized, such as：Serial advanced technology
Annex (SATA), peripheral interconnection standard (PCIE), secure digital input/output cards (SDIO), USB (USB)
Deng.
In a kind of embodiment, clock signal MPLLCLK_A and MPLLCLK_B and common clock signal MPLLCLK_
COM frequency is identical, is 300MHz.Logical network layer LPHY and across time domain data transport module TXCDC is 20 parallel-by-bits
Transmission, then electronic physical layer EPHYA can realize 6Gbps high speed serial transmission.
Fig. 1 embodiments be not intended limit electronic physical layer quantity, electronic physical layer connection external device quantity,
And the relative placement of electronic physical layer and logical network layer.Even, the clock signal of multiple electronic physical layers allows to be different
Frequency.Assuming that electronic physical layer EPHYA clock signal MPLLCLK_A frequencies are 300MHz, electronic physical layer EPHYB clock
Signal MPLLCLK_B frequencies are 150MHz.Herein in embodiment, multiplexer ECLKMUX will not consider clock signal
MPLLCLK_A and MPLLCLK_B cable run distance, but the common clock is used as using the clock signal MPLLCLK_A of most high frequency
Signal MPLLCLK_COM.Logical network layer LPHY includes frequency divider frequency dividing 300Mz common clock signal MPLLCLK_COM
To obtain multiple frequency dividing common clock signals (not illustrating), such as also obtain 150Mz clock signal.In logical network layer LPHY
Circuit module PHYA1 and PHYA2 (such as provided low according to 300MHz common clock signal MPLLCLK_COM operations
Fast data DA1_COM and DA2_COM), and the clock letter for the 150MHz that circuit module PHYB1 and PHYB2 obtains according to frequency dividing
Number operation (such as provide low speed data DB1_COM and DB2_COM).Each circuit module foundation in wherein logical network layer LPHY
Which frequency dividing common clock signal operation connects regarding external device (ED) corresponding to each circuit module (HDA1 and HDA2, HDB1 and HDB2)
The clock frequency of clock signal (MPLLCLK_A and MPLLCLK_B) corresponding to the electronic physical layer (EPHYA and EPHYB) connect and
Calmly, i.e., the clock frequency external device (ED) corresponding with each circuit module of the frequency dividing common clock signal of each circuit module is connected
The clock frequency of clock signal corresponding to electronic physical layer is identical.In another embodiment, across time domain data transport module TXCDC
Also include frequency divider frequency dividing 300MHz common clock signal MPLLCLK_COM to obtain multiple frequency dividing common clock signals
(not illustrating), such as also obtain 150MHz clock signal；Across time domain data transport module TXCDC according to corresponding hard disk HDA1 with
The clock signal MPLLCLK_A for the electronic physical layer EPHYA that HDA2 is connected clock frequency 300MHz frequency dividing common clock
Signal (frequency 300MHz) reads in data DA1_COM, DA2_COM, and be connected according to corresponding hard disk HDB1 with HDB2
(frequency is electronic physical layer EPHYB clock signal MPLLCLK_B clock frequency 150MHz frequency dividing common clock signal
Data DB1_COM, DB2_COM 150MHz) are read in into corresponding cache.It is worth noting that, across time domain data transport module
TXCDC data DA1_A, DA2_A are read be according to the corresponding hard disk HDA1 electronic physical layer EPHYA being connected with HDA2 when
Clock signal MPLLCLK_A, and it is the electronics thing being connected according to corresponding hard disk HDB1 with HDB2 that data DB1_B, DB2_B, which are read,
Manage layer EPHYB clock signal MPLLCLK_B.
Fig. 2A, Fig. 2 B illustrate across time domain data transport module TXCDC according to one embodiment of the present invention.Across time domain data
Transport module TXCDC corresponds to hard disk HDA1, HDA2, HDB1 and HDB2 and provides caching R_A1, R_A2, R_B1 and R_B2 respectively, respectively
From the buffer (each buffer size is with parallel low speed data size) for example including 8 numberings 0~7, that is, caching depth includes 0
~7.Low speed data DA1_COM, DA2_COM, DB1_COM, DB2_COM that logical network layer LPHY is provided believe according to common clock
Number MPLLCLK_COM first reads in buffer W_Buf, then writes marker generator WPTR++ according to common clock signal
MPLLCLK_COM operation write-in distributor W_DMUX, by corresponding low speed data DA1_COM, DA2_COM, DB1_COM,
DB2_COM is pushed into the buffer in caching R_A1, R_A2, R_B1 and R_B2 again.Buffer in R_A1, R_A2, R_B1 and R_B2
The content of the inside can also be grasped reading marker generator RPTR++ clock signal MPLLCLK_A and MPLLCLK_B corresponding to
Make to read selector R_MUX, corresponding low speed data is read into buffer R_Buf, then via buffer R_Buf according to right
The clock signal MPLLCLK_A/MPLLCLK_B outputs answered are data DA1_A, DA2_A, DB1_B, DB2_B.
Fig. 3 illustrates caching R_A1 operations with oscillogram, wherein the buffer of caching R_A1 numberings 0~7 is respectively designated as R_
A1_0~R_A1_7.The buffer R_A1_ of the different caching depth of caching R_A1 is pushed into according to common clock signal MPLLCLK_COM
0~R_A1_7 parallel data D0~D7 smoothly will take out via clock signal MPLLCLK_A, be reflected on data DA1_A.According to
Caching R_A1 data D8~D15 is pushed into according to common clock signal MPLLCLK_COM will update buffer R_A1_0~R_ one by one
A1_7.Buffer R_A1_0~R_A1_7 of difference caching depth data D8~D15 also will be smoothly via clock signal
MPLLCLK_A takes out, and is reflected on data DA1_A.
Fig. 4 is block diagram, describes the high speed interface host-side controller realized according to one embodiment of the present invention
400, it is with least one external device of single electronic physical layer EPHY connections, legend includes hard disk HD1 and HD2, corresponding,
Across time domain data transport module TXCDC includes two groups of caching designs.Logical network layer LPHY and across time domain data transport module
TXCDC can transmit data in a parallel fashion.Electronic physical layer EPHY may include parallel to serial conversion.
High speed interface host-side controller 100 compared to Fig. 1 is also devised with multiplexer ECLKMUX, Fig. 4 host side
Single electronic physical layer EPHY clock signal can be transmitted to patrolling merely with clock signal cabling CLK_trace on controller 400
Physical layer LPHY is collected, operates reference for circuit module PHY_1 and PHY_2 to export the first and second low speed datas respectively.Fig. 4
In, across time domain data transport module TXCDC is from the logical network layer end node on clock signal cabling CLK_trace
MPLLCLK_L receives logical network layer end clock (following to be equally referred to as MPLLCLK_L), and from clock signal cabling CLK_
Trace electronic physical layer end node MPLLCLK_E receives electronic physical layer end clock (following to be equally referred to as MPLLCLK_E).
Logical network layer end node MPLLCLK_L is on clock signal cabling CLK_trace and logical network layer LPHY homonymies
To across time domain data transport module TXCDC node, electronic physical layer end node MPLLCLK_E is the clock signal cabling for input
The upper inputs with electronic physical layer EPHY homonymies of CLK_trace extremely across time domain data transport module TXCDC node.Logic thing
Reason layer end node MPLLCLK_L leans on compared with the electronic physical layer end node MPLLCLK_E on clock signal cabling CLK_trace
Nearly logical network layer LPHY.Fig. 4 across time domain data transport module TXCDC still can effectively solve the delay of clock signal cabling
Problem.In one embodiment, across time domain data transport module TXCDC to logical network layer LPHY cable run distance design
To be shorter than clock signal cabling CLK_trace, and across time domain data transport module TXCDC is somebody's turn to do to electronic physical layer EPHY's
Cable run distance is shorter than clock signal cabling CLK_trace.Logical network layer is directly coupled to electronics thing compared to conventional art
The long cabling of layer is managed, data cabling is cut half by across time domain data transport module TXCDC, corrects cabling delay in time.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any to be familiar with this
Those skilled in the art, without departing from the spirit and scope of the present invention, when a little change and retouching, therefore protection scope of the present invention can be done
When that is defined depending on claims is defined.
Claims (9)
- A kind of 1. high speed interface host-side controller, it is characterised in that including：Logical network layer and electronic physical layer, wherein, the logical network layer provides the first low speed data, then by the electronics physics Layer is converted to the first high-speed data, and is transferred to the first external device (ED), and the clock signal of the electronic physical layer operation also passes The logical network layer is handed to, the logical network layer is provided first low speed data according to this；AndAcross time domain data transport module, it is coupled between the logical network layer and the electronic physical layer, according to logical physical It is first low speed data that first external device (ED) provides that layer end clock, which reads in the logical network layer, and according to electronics physics Layer end clock exports first low speed data to the electronic physical layer.
- 2. high speed interface host-side controller according to claim 1, it is characterised in that：It is somebody's turn to do across time domain data transport module and also provides the first caching for first external device (ED), caches according to the logical physical First low speed data that layer end clock is read in.
- 3. high speed interface host-side controller according to claim 1, it is characterised in that also include：Clock signal cabling, the clock signal is transferred to the logical network layer from the electronic physical layer,Wherein, across time domain data transport module is somebody's turn to do from the logic thing of the logical network layer end node reception on the clock signal cabling Manage layer end clock, and from the electronic physical layer end node reception of the clock signal cabling electronic physical layer end clock.
- 4. high speed interface host-side controller according to claim 3, it is characterised in that the logical network layer end segment Point close logical network layer on the clock signal cabling compared with the electronic physical layer end node.
- 5. high speed interface host-side controller according to claim 3, it is characterised in that：The cable run distance of across time domain data transport module to the logical network layer is shorter than the clock signal cabling；AndAcross the time domain data transport module to the cable run distance of the electronic physical layer is shorter than the clock signal cabling.
- 6. high speed interface host-side controller according to claim 1, it is characterised in that：The logical network layer provides first low speed data in a parallel fashion extremely should across time domain data transport module；It is somebody's turn to do across time domain data transport module and sends first low speed data in a parallel fashion to the electronic physical layer；AndThe electronic physical layer just transmitted after first low speed data is converted into serial high speed from parallel low speed data to First external device (ED).
- 7. high speed interface host-side controller according to claim 1, it is characterised in that：The logical network layer also provides the second low speed data and is converted to the second high-speed data by the electronic physical layer, and is transferred to Two external device (ED)s；Should across time domain data transport module always according to the logical network layer end clock read in the logical network layer for this outside second Second low speed data that device provides, and second low speed data is exported to the electricity according to the electronic physical layer end clock Muon physics layer.
- 8. high speed interface host-side controller according to claim 7, it is characterised in that：It is somebody's turn to do across time domain data transport module and also provides the second caching for the electronic physical layer, caches according to the logical network layer Second low speed data for holding clock to read in.
- 9. high speed interface host-side controller according to claim 1, it is characterised in that：The clock signal, the logical network layer end clock and the electronic physical layer end clock are same clock source.
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| EP2800004A1 (en) * | 2009-05-20 | 2014-11-05 | Chronologic Pty Limited | Synchronous network of superspeed and non-superspeed USB devices |
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| CN101689209A (en) * | 2007-05-15 | 2010-03-31 | 克罗诺洛吉克有限公司 | Method and system for reducing triggering latency in universal serial bus data acquisition |
| CN101561794A (en) * | 2009-06-05 | 2009-10-21 | 威盛电子股份有限公司 | Universal serial bus device |
| CN102023945A (en) * | 2009-09-22 | 2011-04-20 | 鸿富锦精密工业（深圳）有限公司 | Serial peripheral interface bus-based equipment and data transmission method thereof |
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Address after: Room 301, 2537 Jinke Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: Shanghai Zhaoxin Semiconductor Co.,Ltd. Address before: Room 301, 2537 Jinke Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd. |
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