CN105490692A - Bandwidth-adjustable zero-intermediate-frequency narrow-band receiving processing method - Google Patents
Bandwidth-adjustable zero-intermediate-frequency narrow-band receiving processing method Download PDFInfo
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- CN105490692A CN105490692A CN201410480984.8A CN201410480984A CN105490692A CN 105490692 A CN105490692 A CN 105490692A CN 201410480984 A CN201410480984 A CN 201410480984A CN 105490692 A CN105490692 A CN 105490692A
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Abstract
The invention discloses a bandwidth-adjustable zero-intermediate-frequency narrow-band receiving processing method. The method comprises the following steps: amplifying an input signal through an amplifier; performing frequency conversion on the amplified signal through a frequency mixer; converting an analog signal into a digital signal through an analog-to-digital converter; partitioning the digital signal into an I-path signal and a Q-path signal; performing secondary frequency conversion on the two paths of digital signals respectively through the frequency mixer; filtering the two paths of the digital signals being subjected to the secondary frequency conversion respectively through a filter; and outputting the filtered I-path signal and Q-path signal. Through adoption of the method, the problems of low-frequency noise interference, direct-current offset, signal aliasing and signal filtering in a zero-intermediate-frequency narrow-band receiver are solved; bandwidth adjustability can be realized; the implementation difficulty of the receiver is lowered; the circuit scale is reduced; and the power consumption and the cost are lowered.
Description
Technical field
The present invention relates to a kind of zero intermediate frequency receiving handling method, particularly relate to the zero intermediate frequency narrow-band reception processing method that a kind of bandwidth is adjustable.
Background technology
Along with the fast development of the microelectric techniques such as SiGe and cmos semiconductor technique, and the appearance of some novel circuit technology and new algorithm, zero-if architecture obtains comprehensive research and analysis at wireless communication field.Zero-if architecture is very potential developing direction in radio-frequency structure, has very large commercial value.
Zero intermediate frequency reciver has that volume is little, cost is low, power consumption is little, structure is simple, be easy to single-chip integration etc. advantage, be subject to extensive concern in the field of wireless communication, also should see simultaneously, zero intermediate frequency receives structure and also there are some problems, as higher in the DC maladjustment problem of zero intermediate frequency, the design difficulty of the low-frequency noise of zero intermediate frequency on the impact of narrow band signal, arrowband/bandwidth tunable filter, be difficult to realize for the frequency overlapped-resistable filter of high resolution A/D sampling, these problems also need to do more deep analysis and research.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, there is provided a kind of multiple technical bottlenecks that can solve in zero intermediate frequency narrow-band receiver, the zero intermediate frequency narrow-band reception processing method that a kind of bandwidth as low frequency noises, DC maladjustment, signal aliasing, signal filtering problem is adjustable.
The object of the invention is to be achieved through the following technical solutions:
The zero intermediate frequency narrow-band reception processing method that bandwidth is adjustable, it comprises the following steps:
S1: input signal carries out amplification process by the amplifier in analog domain;
S2: the signal after amplification carries out frequency conversion by the frequency mixer in analog domain to signal;
S3: in the output signal of frequency mixer analog to digital converter in the digital domain, analog signal is converted to digital signal, and eliminates the signal aliasing problem of ADC sampling;
S4: digital signal is divided into I road and Q road two paths of signals;
S5: two ways of digital signals carries out second time frequency conversion respectively by frequency mixer, solves the low frequency noises in zero-if architecture and DC maladjustment problem;
S6: the two paths of signals after second time frequency conversion carries out filtering process respectively by filter, the exponent number solving the filter that analog domain filtering faces is high, circuit scale large and be not easy stable problem;
S7: export the filtered zero intermediate frequency signals of I, Q two-way.
Analog to digital converter in described step S3 will adopt the continuous mode segma-deltaADC carrying anti-aliasing function, to solve the signal aliasing problem of ADC sampling.
Frequency mixer in described step S2, S3, S5 and the local oscillation signal of analog to digital converter and sampling clock produce by same frequency synthesizer, are provided by frequency division.
The invention has the beneficial effects as follows: the present invention adopts and realizes double conversion at analog domain and numeric field, finally produce the mode that zero intermediate frequency exports, solve the problem of the low frequency noises in zero intermediate frequency narrow-band receiver, DC maladjustment, signal aliasing, signal filtering, and can accomplish that bandwidth is adjustable, what reduce receiver realizes difficulty, reduce circuit scale, reduce power consumption and cost.
Accompanying drawing explanation
Fig. 1 is method flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
Fig. 1 is the flow chart of the adjustable zero intermediate frequency narrow-band reception processing method of a kind of bandwidth of the present invention, as shown in the figure, first utilizes amplifier to carry out amplification process to input signal; Signal after amplification directly enters frequency mixer, the signal mixing that the signal received and local oscillator produce by frequency mixer; Signal is after analog domain process, by analog to digital converter, analog signal is converted to digital signal, start process signal being carried out to numeric field, analog to digital converter wherein need adopt the continuous mode segma-deltaADC carrying anti-aliasing function, can solve the signal aliasing problem in ADC sampling.
Digital signal carries out second time frequency conversion respectively by frequency mixer after being divided into I road and Q road two paths of signals, solves the low frequency noises in zero-if architecture and DC maladjustment problem; Again filtering process is carried out to signal afterwards, just can obtain two-way output signal; Carrying out filtering at numeric field, can to solve the exponent number of filter high, causes circuit scale large and be not easy stable problem, realize the adjustable flexibly of bandwidth simultaneously.
The local oscillation signal of analog domain frequency conversion, the local oscillation signal of numeric field frequency conversion, ADC sampling clock produce by same frequency synthesizer, are provided by frequency division, as frequency input signal be 10MHz time, local oscillation signal frequency can adopt the frequency of 16.455MHz.
Claims (3)
1. the zero intermediate frequency narrow-band reception processing method that bandwidth is adjustable, is characterized in that: it comprises the following steps: S1: input signal carries out amplification process by the amplifier in analog domain;
S2: the signal after amplification carries out frequency conversion by the frequency mixer in analog domain to signal;
S3: in the output signal of frequency mixer analog to digital converter in the digital domain, analog signal is converted to digital signal, and eliminates the signal aliasing problem of ADC sampling;
S4: digital signal is divided into I road and Q road two paths of signals;
S5: two ways of digital signals carries out second time frequency conversion respectively by frequency mixer, solves the low frequency noises in zero-if architecture and DC maladjustment problem;
S6: the two paths of signals after second time frequency conversion carries out filtering process respectively by filter, the exponent number solving the filter that analog domain filtering faces is high, circuit scale large and be not easy stable problem;
S7: export the filtered zero intermediate frequency signals of I, Q two-way.
2. the zero intermediate frequency narrow-band reception processing method that a kind of bandwidth according to claim 1 is adjustable, it is characterized in that: the analog to digital converter in described step S3 will adopt the continuous mode segma-deltaADC carrying anti-aliasing function, to solve the signal aliasing problem of ADC sampling.
3. the zero intermediate frequency narrow-band reception processing method that a kind of bandwidth according to claim 1 is adjustable, it is characterized in that: the frequency mixer in described step S2, S3, S5 and the local oscillation signal of analog to digital converter and sampling clock produce by same frequency synthesizer, are provided by frequency division.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410480984.8A CN105490692A (en) | 2014-09-19 | 2014-09-19 | Bandwidth-adjustable zero-intermediate-frequency narrow-band receiving processing method |
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| CN201410480984.8A CN105490692A (en) | 2014-09-19 | 2014-09-19 | Bandwidth-adjustable zero-intermediate-frequency narrow-band receiving processing method |
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| CN105490692A true CN105490692A (en) | 2016-04-13 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266292A (en) * | 2008-05-08 | 2008-09-17 | 北京航空航天大学 | GNSS reflected signal frequency domain processing unit and method |
| CN101656562A (en) * | 2009-09-22 | 2010-02-24 | 武汉虹信通信技术有限责任公司 | Device and method for realizing elimination of self-excitation interference of repeater |
| CN201910922U (en) * | 2010-09-28 | 2011-07-27 | 北京交通大学 | High-speed data acquisition device for channel detection |
| CN102751998A (en) * | 2012-04-06 | 2012-10-24 | 华北电力大学 | Data intermediate frequency module based on software radio receiver |
| CN103457619A (en) * | 2013-07-16 | 2013-12-18 | 中国电子科技集团公司第四十一研究所 | Digital tuning receiving device and control method thereof |
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2014
- 2014-09-19 CN CN201410480984.8A patent/CN105490692A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266292A (en) * | 2008-05-08 | 2008-09-17 | 北京航空航天大学 | GNSS reflected signal frequency domain processing unit and method |
| CN101656562A (en) * | 2009-09-22 | 2010-02-24 | 武汉虹信通信技术有限责任公司 | Device and method for realizing elimination of self-excitation interference of repeater |
| CN201910922U (en) * | 2010-09-28 | 2011-07-27 | 北京交通大学 | High-speed data acquisition device for channel detection |
| CN102751998A (en) * | 2012-04-06 | 2012-10-24 | 华北电力大学 | Data intermediate frequency module based on software radio receiver |
| CN103457619A (en) * | 2013-07-16 | 2013-12-18 | 中国电子科技集团公司第四十一研究所 | Digital tuning receiving device and control method thereof |
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Application publication date: 20160413 |