CN105489637B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105489637B CN105489637B CN201510866051.7A CN201510866051A CN105489637B CN 105489637 B CN105489637 B CN 105489637B CN 201510866051 A CN201510866051 A CN 201510866051A CN 105489637 B CN105489637 B CN 105489637B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 138
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 107
- 230000003647 oxidation Effects 0.000 claims abstract description 102
- 230000004888 barrier function Effects 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000008569 process Effects 0.000 claims abstract description 21
- 230000001590 oxidative effect Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 28
- 238000009413 insulation Methods 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000000873 masking effect Effects 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of forming method of semiconductor structure, the forming method of the semiconductor structure include：Semiconductor substrate is provided, including：First semiconductor layer, insulating layer, the second semiconductor layer, the Semiconductor substrate include first area, second area and the 3rd region；The first oxide layer and oxidation barrier layer are formed in the second semiconductor layer surface；Remove the oxidation barrier layer on Semiconductor substrate second area and the 3rd region；Remove the first oxide layer on the 3rd region of Semiconductor substrate；Carry out oxidation processes, aoxidized the oxidation barrier layer, and the second semiconductor layer surface in second area and the 3rd region forms the second oxide layer, the second oxide layer on second area has second thickness, the second oxide layer on the 3rd region has the 3rd thickness, and the second thickness is less than the 3rd thickness；Remove second oxide layer, the first oxide layer and the oxidation barrier layer after being aoxidized.The method can improve the performance of the semiconductor structure of formation.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
Silicon-on-insulator substrate is the silica-base material of a new generation, no matter in low pressure, low consumption circuit, high temperature resistant circuit, micro-
Mechanical pick-up device, photoelectricity, which integrate etc., all has important application.Silicon-on-insulator substrate includes：Bottom silicon layer, the bottom of positioned at
The insulating layer of layer silicon surface, the top silicon layer positioned at surface of insulating layer.It is realized by insulating layer and is formed in top silicon layer
Semiconductor devices and bottom silicon layer between Fully dielectric isolation, it is possible to reduce the parasitic capacitance of device reduces power consumption, reduces leakage
Electric current etc. can significantly improve the performance of device.
There is conducting resistance R in the on-state for the transistor formed on silicon substrate on insulatoron, in transistor
There is shut-off capacitance C when it is disconnectedoff.The quality factor FOM=R of transistoron×Coff, it is to weigh switching device (such as to penetrate
Frequency device) performance primary reference point, the numerical value of FOM is lower, and device performance is higher.The numerical value for reducing FOM mainly passes through
Reduce conducting resistance RonOr reduce shut-off capacitance CoffIt realizes.In the case where conducting resistance is certain, shut-off capacitance C is reducedoffEnergy
The enough numerical value for effectively reducing FOM.
The shut-off capacitance of transistor is mainly under the overlap capacitance and grid between grid and source-drain electrode including transistor
Junction capacity between the well region and source-drain electrode of side.The junction capacity of the transistor formed on insulator on silicon substrate is subject to top layer silicon
The influence of layer thickness, the top silicon layer thickness is bigger, and junction capacity is bigger, and the reduction top silicon layer thickness can be reduced effectively
The FOM numerical value of transistor.And the transistor in different circuits, such as control circuit, logic circuit, radio circuit etc., it is necessary to
The thickness of top silicon layer is different.
It is existing there is an urgent need for a kind of method on insulator silicon substrate different zones formed different-thickness top silicon layer.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure, in the different zones of Semiconductor substrate
Upper the second semiconductor layer for forming different-thickness.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Semiconductor lining is provided
Bottom, the Semiconductor substrate include：First semiconductor layer, positioned at the insulating layer of the first semiconductor layer surface, positioned at insulating layer table
Second semiconductor layer in face, on parallel to semiconductor substrate surface direction, the Semiconductor substrate includes first area, second
Region and the 3rd region；The first oxide layer and the oxidation positioned at the described first oxidation layer surface are formed in the second semiconductor layer surface
Barrier layer；The oxidation barrier layer on Semiconductor substrate second area and the 3rd region is removed, exposes the secondth area of Semiconductor substrate
The first oxidation layer surface on domain and the 3rd region；The first oxide layer on the 3rd region of Semiconductor substrate is removed, exposes half
The 3rd region surface of conductor substrate；Oxidation processes are carried out, are aoxidized the oxidation barrier layer, and in second area and the 3rd area
Second semiconductor layer surface in domain forms the second oxide layer, and the second oxide layer on second area has second thickness, position
There is the 3rd thickness in the second oxide layer on the 3rd region, the second thickness is less than the 3rd thickness；Remove second oxygen
Change layer, the first oxide layer and the oxidation barrier layer after being aoxidized.
Optionally, the oxidation barrier layer material is polysilicon, silicon nitride or amorphous silicon.
Optionally, the thickness range of the oxidation barrier layer is
Optionally, the thickness range of first oxide layer is
Optionally, the second semiconductor layer surface further included on the first region forms the second oxide layer.
Optionally, the second oxide layer on the first area has first thickness, and the first thickness is less than the
Two thickness.
Optionally, the method for the oxidation processes includes dry-oxygen oxidation or steam oxidation.
Optionally, the dry-oxygen oxidation uses O2As oxidizing gas, oxidizing temperature is 900 DEG C~1200 DEG C, during oxidation
Between be 10min~100min.
Optionally, the steam oxidation uses H2O steam is as oxidizing gas, and oxidizing temperature is 900 DEG C~1200 DEG C, oxygen
The change time is 5min~50min.
Optionally, second oxide layer, the first oxide layer and the oxygen after being aoxidized are removed using wet-etching technology
Change barrier layer.
Compared with prior art, technical scheme has the following advantages：
In technical scheme, Semiconductor substrate the second semiconductor layer surface formed the first oxide layer, be located at
After the oxidation barrier layer of first oxidation layer surface, the oxidation barrier on Semiconductor substrate second area and the 3rd region is removed
Layer removes the first oxide layer on the 3rd region of Semiconductor substrate, oxidation processes is then carried out, in second area and the 3rd region
The second semiconductor layer surface form the second oxide layer, the second oxide layer on second area has second thickness, is located at
The second oxide layer on 3rd region has the 3rd thickness.Since second semiconductor layer surface in the 3rd region is not covered with,
And second area surface is covered by the first oxide layer, first area surface is covered by the first oxide layer and oxidation barrier layer, so
The second thickness is less than the 3rd thickness.So as to remove the second oxide layer, the first oxide layer and the oxidation barrier after being aoxidized
After layer, the second layer semiconductor thickness of first area is more than the second layer semiconductor thickness of second area, and the of second area
Two layer semiconductor thickness are more than second layer semiconductor thickness in the 3rd region, so as to simultaneously in the different zones shape of Semiconductor substrate
Into the second semiconductor layer of different-thickness, to meet the needs of different semiconductor devices, so as to improve in the semiconductor junction
The performance of the semiconductor devices formed on structure.
Further, the oxidation barrier layer material can be oxidation-treated for polysilicon, silicon nitride or amorphous silicon etc.
The material to react in journey with oxidizing gas infiltrates into the second semiconductor layer surface so as to barrier oxidation gas, to
Second semiconductor layer in one region is aoxidized.
Further, second oxide layer, the first oxide layer and the oxygen after being aoxidized are removed using wet-etching technology
Change barrier layer, compared with dry etch process, wet-etching technology has higher Etch selectivity, and it is possible to avoid pair
Second semiconductor layer surface causes to damage, and avoids influencing the performance of the semiconductor devices subsequently formed in semiconductor layer surface.
Description of the drawings
Fig. 1 to Fig. 6 is the structure diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Specific embodiment
As described in the background art, in order to meet the transistor performance requirements of different circuits, on insulator on silicon substrate
Different zones need to form the top silicon layer of different-thickness.
In the embodiment of the present invention, formed by the second semiconductor layer surface of the different zones in Semiconductor substrate top layer
Then second oxide layer of different-thickness removes second oxide layer, so that the second semiconductor layer tool of different zones
There is different thickness.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
It please refers to Fig.1, Semiconductor substrate 100 is provided, the Semiconductor substrate 100 includes the first semiconductor layer 101, is located at
The insulating layer 102 on 101 surface of the first semiconductor layer, the second semiconductor layer 103 positioned at 102 surface of insulating layer, parallel to half
On the direction on 100 surface of conductor substrate, the Semiconductor substrate 100 includes first area I, second area II and the 3rd region
III。
In the present embodiment, the Semiconductor substrate 100 be silicon-on-insulator substrate (SOI), first semiconductor layer 101
Material be silicon, 102 material of insulating layer is silica, the material of the second semiconductor layer 103 is silicon.
In other embodiments of the invention, first semiconductor layer 101, the second semiconductor layer 103 can also be it
His semi-conducting material, such as germanium, SiGe or GaAs etc..The material of first semiconductor layer, 101 and second semiconductor layer 103
Material can be identical material, can also each use different semi-conducting materials.
The thickness of second semiconductor layer 103 is generally higher thanIn the present embodiment, second semiconductor layer
103 thickness is
First area I, second area II and the 3rd region III of the Semiconductor substrate 100 are for respectively forming difference
Circuit, in the present embodiment, first area I is for forming control circuit, second area II for forming logic circuit, the 3rd area
Domain III is used to form radio circuit.In the present embodiment, the first area I, second area II and the 3rd region III are adjacent
Region, in other embodiments of the invention, the region I, second area II and the 3rd region III can also between each other between
Every other regions.
It please refers to Fig.2, the first oxide layer 201 is formed on 103 surface of the second semiconductor layer and positioned at first oxide layer
The oxidation barrier layer 202 on 201 surfaces.
The material of first oxide layer 201 is silica, may be employed depositing operation or oxidation technology forms described the
One oxide layer 201.
First oxide layer 201 has certain thickness, can be to O2Or H2The molecule of O plays certain barrier effect.
Specifically, the thickness range of first oxide layer 201 can beIn the present embodiment, first oxygen
Change layer thickness be
It is formed after first oxide layer 201, oxidation barrier layer 202 is formed on 201 surface of the first oxide layer.Institute
Stating the material of oxidation barrier layer 202 can be combined with oxygen, stop that oxygen atom diffuses to the second semiconductor layer 201.The oxidation resistance
The material of barrier 202 can be polysilicon, silicon nitride or non-crystalline silicon etc..Depositing operation may be employed and form the oxidation barrier layer
202, the depositing operation can be chemical vapor deposition method, plasma enhanced chemical vapor deposition technique etc..
In the present embodiment, the oxidation barrier layer 202 is formed using chemical vapor deposition method.The oxidation barrier layer
202 have enough thickness, stop that the oxygen atom in subsequent oxidation processing procedure infiltrates into the second half through oxidation barrier layer 202
103 surface of conductor layer, the thickness range of the oxidation barrier layer 202 areIn the present embodiment, the oxidation
The thickness on barrier layer 202 is
It please refers to Fig.3, the oxidation barrier layer 202 on removal Semiconductor substrate 100 second area II and the 3rd region III
(please referring to Fig.2) exposes 201 surface of the first oxide layer on Semiconductor substrate 100 second area II and the 3rd region III.
Specifically, in the present embodiment, the oxidation resistance on Semiconductor substrate 100 second area II and the 3rd region III is removed
The method of barrier 202 includes：Patterned masking layer is formed on 202 surface of oxidation barrier layer, the Patterned masking layer covers
Oxidation barrier layer 202 on the I of lid first area, using the Patterned masking layer as mask, etch the oxidation barrier layer 202 to
To 201 surface of oxide layer, only covering the is formed with the remaining oxidation barrier layer 202a of region I, then, is removed described graphical
Mask layer.The material of the Patterned masking layer can be photoresist, silicon nitride or amorphous carbon etc..
After oxidation barrier layer 202 on removal second area II and the 3rd region III so that subsequently carry out oxidation processes
During, oxygen atom can infiltrate into 103 surface of the second semiconductor layer so that the of second area II and the 3rd region III
Two semiconductor layers, 103 surface is aoxidized.
It please refers to Fig.4, the first oxide layer 201 (please referring to Fig.3) on the 3rd region III of removal Semiconductor substrate 100, cruelly
Expose the 3rd region III surfaces of Semiconductor substrate 100.
Removing the method for the first oxide layer 201 on the 3rd region III includes：Oxidation barrier layer after the etching
202a and 201 surface of the first oxide layer form Patterned masking layer, and the Patterned masking layer is exposed on the 3rd region III
First oxide layer, 201 surface using the Patterned masking layer as mask, etches 201 to the second semiconductor of the first oxide layer
103 surface of layer, removal are located at the first oxide layer 201 on the 3rd region III.The first oxide layer 201a coverings second after etching
The second semiconductor layer 103 of region II and first area I.Then, the Patterned masking layer, the Patterned masking layer are removed
Material can be photoresist, silicon nitride or amorphous carbon etc..Remove the first oxide layer 201 on the 3rd region III it
Afterwards, the second semiconductor layer 103 of the 3rd region III is more easy to be aoxidized in subsequent oxidation processing procedure.
Fig. 5 is refer to, oxidation processes is carried out, is aoxidized the oxidation barrier layer 202, and in second area II and the 3rd
103 surface of the second semiconductor layer of region III forms the second oxide layer 203.
The method of the oxidation processes includes dry-oxygen oxidation or steam oxidation.In the present embodiment, the side of the oxidation processes
Method is dry-oxygen oxidation technique, using O2As oxidizing gas, oxidizing temperature is 900 DEG C~1200 DEG C, oxidization time for 10min~
100min.In other embodiments of the invention, using steam oxidation technique, the oxidation processes, the steam oxidation are carried out
Using H2For O steam as oxidizing gas, oxidizing temperature is 900 DEG C~1200 DEG C, and oxidization time is 5min~50min.
Since 103 surface of the second semiconductor layer of the 3rd region III of the Semiconductor substrate 100 is exposed to oxidizing gas
In, oxidation reaction is directly generated, the second oxide layer 203 is formed on 103 surface of the second semiconductor layer, the 3rd region III's
The second oxide layer 203 that second semiconductor layer, 103 surface is formed has the 3rd thickness；And the second semiconductor layer of second area II
The second oxide layer 203 that 103 surfaces are formed has second thickness.Since 103 surface of the second semiconductor layer of second area II is covered
The first oxide layer 201a is stamped, blocks the infiltration of partial oxidation gas；Due in oxidation process, what oxidizing gas can permeate
Depth is limited, so, the formed on 103 surface of the second semiconductor layer for having second area II that the first oxide layer 201a covers
The second thickness of dioxide layer 203 is less than the 3rd thickness of the second oxide layer 203 formed on the 3rd region III.It is if described
The time long enough of oxidation processes, when the thickness of oxide layer reaches maximum, oxidizing gas will be unable to continue to infiltrate into second
103 surface of semiconductor layer, the 3rd thickness is equal to the sum of thickness of second thickness and the first oxide layer 201a at this time.It can be with
By controlling the time of oxidation processes, the second thickness and the 3rd thickness are adjusted.
In the present embodiment, the first area I of Semiconductor substrate 100 is formed with oxidation barrier layer 202a, the oxidation barrier
Layer 202a can react in oxidation processes with oxidizing gas, the oxidation barrier layer 202b after oxidation be formed, into one
Step barrier oxidation gas permeates downwards.In the present embodiment, the material of the oxidation barrier layer 202a is polysilicon, is formed after oxidation
Silica.In other embodiments of the invention, the material of the oxidation barrier layer 202a is silicon nitride, and compactness higher has
There is better oxidation barrier to act on, the mixture for including silica and silicon oxynitride is formed after oxidation.In other realities of the present invention
It applies in example, the oxidation barrier layer 202a can also be amorphous silicon, and silica is also formed after oxidation.
In the present embodiment, the oxidation barrier layer 202a has enough thickness, and oxidizing gas is stopped completely, so that
103 surface of the second semiconductor layer for obtaining first area I does not aoxidize.
In other embodiments of the invention, the thickness of the oxidation barrier layer 202a is smaller, described in oxidation process
Oxidation barrier layer 202a is fully oxidized after the oxidation barrier layer 202b after forming oxidation, is also had certain oxidizing gas and is oozed
Thoroughly to the second semiconductor layer 202a surfaces of first area I, 103 surface of the second semiconductor layer on the I of first area forms the
Dioxide layer, the second oxide layer on the first area I have a first thickness, and to be less than described second thick for the first thickness
Degree.
Fig. 6 is refer to, removes second oxide layer 203 (refer to Fig. 5), the first oxide layer 201a (refer to Fig. 5)
And the oxidation barrier layer 202b (refer to Fig. 5) after being aoxidized.
Second oxide layer 203, the first oxide layer 201a and the oxygen after being aoxidized are removed using wet-etching technology
Change barrier layer 202b.In the present embodiment, using etching solution of the hydrofluoric acid solution as wet-etching technology.
Compared with dry etch process, wet-etching technology has higher Etch selectivity, and it is possible to avoid to the
Two semiconductor layers, 103 surface causes to damage, and avoids influencing the property of the semiconductor devices subsequently formed on 103 surface of semiconductor layer
Energy.
After removing second oxide layer 203, the first oxide layer 201a and oxidation barrier layer 202b after being aoxidized,
The second semiconductor layer 103 formed is respectively provided with different thickness in first area I, second area II and the 3rd region III.The
The second semiconductor layer 103a thickness of one region I is maximum, suitably forms the semiconductor devices needed compared with high working voltage, such as shape
Into control circuit；The thickness of the second semiconductor layer 103a of 3rd region III is minimum, can significantly reduce on the 3rd region III
The FOM numerical value of the semiconductor devices of formation suitably forms the more demanding high-frequency element of switch performance, such as can form radio frequency
Circuit；The thickness of the second semiconductor layer 103a of second area II the second half leading on first area I, the 3rd region III
Between body layer 103a, the relatively low semiconductor devices of operating voltage is suitably formed, such as forms logic circuit.In the present embodiment, the
The thickness of the second semiconductor layer 103a on one region I isThe thickness of the second semiconductor layer 103a on second area II
It spends and isThe thickness of the second semiconductor layer 103a on 3rd region III is
Also, in the embodiment of the present invention, it is only necessary to carry out once oxidation and etching technics, while be formed in different zones
Second semiconductor layer 103a of different-thickness, it is simple for process, and process costs are relatively low, and it is compatible with existing CMOS technology.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (10)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Semiconductor substrate is provided, the Semiconductor substrate includes：First semiconductor layer, the insulation positioned at the first semiconductor layer surface
Layer, positioned at the second semiconductor layer of surface of insulating layer, on parallel to semiconductor substrate surface direction, the semiconductor substrate
Include first area, second area and the 3rd region；
The first oxide layer and the oxidation barrier layer positioned at the described first oxidation layer surface are formed in the second semiconductor layer surface；
Remove the oxidation barrier layer on Semiconductor substrate second area and the 3rd region, expose Semiconductor substrate second area and
The first oxidation layer surface on 3rd region；
The first oxide layer on the 3rd region of Semiconductor substrate is removed, exposes the 3rd region surface of Semiconductor substrate；
Oxidation processes are carried out, are aoxidized the oxidation barrier layer, and in second semiconductor layer in second area and the 3rd region
Surface forms the second oxide layer, and the second oxide layer on second area has second thickness, and the on the 3rd region
Dioxide layer has the 3rd thickness, and the second thickness is less than the 3rd thickness；
Remove second oxide layer, the first oxide layer and the oxidation barrier layer after being aoxidized.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that the oxidation barrier layer material is
Polysilicon or amorphous silicon.
3. the forming method of semiconductor structure according to claim 2, which is characterized in that the thickness of the oxidation barrier layer
Scope is
4. the forming method of semiconductor structure according to claim 1, which is characterized in that the thickness of first oxide layer
Scope is
5. the forming method of semiconductor structure according to claim 1, which is characterized in that further include on the first region
Second semiconductor layer surface forms the second oxide layer.
6. the forming method of semiconductor structure according to claim 5, which is characterized in that on the first area
Second oxide layer has first thickness, and the first thickness is less than second thickness.
7. the forming method of semiconductor structure according to claim 1, which is characterized in that the method bag of the oxidation processes
Include dry-oxygen oxidation or steam oxidation.
8. the forming method of semiconductor structure according to claim 7, which is characterized in that the dry-oxygen oxidation uses O2Make
For oxidizing gas, oxidizing temperature is 900 DEG C~1200 DEG C, and oxidization time is 10min~100min.
9. the forming method of semiconductor structure according to claim 7, which is characterized in that the steam oxidation uses H2O steams
For vapour as oxidizing gas, oxidizing temperature is 900 DEG C~1200 DEG C, and oxidization time is 5min~50min.
10. the forming method of semiconductor structure according to claim 1, which is characterized in that gone using wet-etching technology
Except second oxide layer, the first oxide layer and the oxidation barrier layer after being aoxidized.
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| US6329689B1 (en) * | 1997-08-20 | 2001-12-11 | Micron Technology, Inc. | Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates |
| CN1479350A (en) * | 2002-08-27 | 2004-03-03 | 上海宏力半导体制造有限公司 | Method of forming different thickness bigrid insulating layer |
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| JP4852694B2 (en) * | 2004-03-02 | 2012-01-11 | 独立行政法人産業技術総合研究所 | Semiconductor integrated circuit and manufacturing method thereof |
| TWI285783B (en) * | 2004-07-09 | 2007-08-21 | Au Optronics Corp | Poly silicon layer structure and forming method thereof |
| US20080128797A1 (en) * | 2006-11-30 | 2008-06-05 | International Business Machines Corporation | Structure and method for multiple height finfet devices |
| US20090321834A1 (en) * | 2008-06-30 | 2009-12-31 | Willy Rachmady | Substrate fins with different heights |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329689B1 (en) * | 1997-08-20 | 2001-12-11 | Micron Technology, Inc. | Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates |
| CN1479350A (en) * | 2002-08-27 | 2004-03-03 | 上海宏力半导体制造有限公司 | Method of forming different thickness bigrid insulating layer |
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