CN105489637A - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN105489637A CN105489637A CN201510866051.7A CN201510866051A CN105489637A CN 105489637 A CN105489637 A CN 105489637A CN 201510866051 A CN201510866051 A CN 201510866051A CN 105489637 A CN105489637 A CN 105489637A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 111
- 230000003647 oxidation Effects 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims description 63
- 230000001590 oxidative effect Effects 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000000873 masking effect Effects 0.000 description 10
- 239000012212 insulator Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a forming method of a semiconductor structure. The forming method of the semiconductor structure comprises the steps as follows: a semiconductor substrate is provided, wherein the semiconductor substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer; the semiconductor substrate comprises a first region, a second region and a third region; a first oxidation layer and an oxidation blocking layer are formed on the surface of the second semiconductor layer; the oxidation blocking layer in the second region and the third region of the semiconductor substrate is removed; the first oxidation layer in the third region of the semiconductor substrate is removed; oxidation treatment is carried out, so that the oxidation blocking layer is oxidized; a second oxidation layer is formed on the surface of the second semiconductor layer in the second region and the third region; the second oxidation layer in the second region has a second thickness; the second oxidation layer in the third region has a third thickness; the second thickness is smaller than the third thickness; and the second oxidation layer, the first oxidation layer and the oxidized oxidation blocking layer are removed. According to the method disclosed by the invention, the performance of the formed semiconductor structure can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
Silicon-on-insulator substrate is the silica-base material of a new generation, in low pressure, low consumption circuit, high temperature resistant circuit, micro mechanical sensor, photoelectricity are integrated etc., all have important application.Silicon-on-insulator substrate comprises: bottom silicon layer, be positioned at the insulating barrier of bottom silicon surface, be positioned at the top silicon layer of surface of insulating layer.Achieved the Fully dielectric isolation between semiconductor device and bottom silicon layer formed in top silicon layer by insulating barrier, the parasitic capacitance of device can be reduced, reduce power consumption, reduce leakage current etc., the performance of device can be significantly improved.
In the on-state there is conducting resistance R for the transistor that silicon substrate is on insulator formed
on, have under transistor off-state and turn off electric capacity C
off.The quality factor FOM=R of transistor
on× C
off, be the primary reference point of the performance weighing switching device (such as radio-frequency devices), the numerical value of FOM is lower, and device performance is higher.Reduce the numerical value of FOM mainly through reducing conducting resistance R
onor reduce shutoff electric capacity C
offrealize.When conducting resistance is certain, reduces and turn off electric capacity C
offeffectively can reduce the numerical value of FOM.
The shutoff electric capacity of transistor mainly comprises the overlap capacitance between the grid of transistor and source-drain electrode, and well region below grid and the junction capacitance between source-drain electrode.The junction capacitance of the transistor on insulator silicon substrate formed is subject to the impact of top silicon layer thickness, and described top silicon layer thickness is larger, and junction capacitance is larger, and described reduction top silicon layer thickness effectively can reduce the FOM numerical value of transistor.And the transistor in different circuit, such as control circuit, logical circuit, radio circuit etc., the thickness of the top silicon layer of needs is different.
The existing zones of different needing a kind of method silicon substrate on insulator badly forms the top silicon layer of different-thickness.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, and the zones of different of Semiconductor substrate is formed the second semiconductor layer of different-thickness.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises: the first semiconductor layer, be positioned at the insulating barrier of the first semiconductor layer surface, be positioned at the second semiconductor layer of surface of insulating layer, be parallel on semiconductor substrate surface direction, described Semiconductor substrate comprises first area, second area and the 3rd region; Form the first oxide layer in the second semiconductor layer surface and be positioned at the oxidation barrier layer on described first oxide layer surface; Remove the oxidation barrier layer on Semiconductor substrate second area and the 3rd region, expose the first oxide layer surface on Semiconductor substrate second area and the 3rd region; Remove the first oxide layer on Semiconductor substrate the 3rd region, expose Semiconductor substrate the 3rd region surface; Carry out oxidation processes, make described oxidation barrier layer oxidized, and form the second oxide layer in second semiconductor layer surface in second area and the 3rd region, the second oxide layer be positioned on second area has the second thickness, the second oxide layer be positioned on the 3rd region has the 3rd thickness, and described second thickness is less than the 3rd thickness; Remove described second oxide layer, the first oxide layer and oxidized after oxidation barrier layer.
Optionally, described oxidation barrier layer material is polysilicon, silicon nitride or amorphous silicon.
Optionally, the thickness range of described oxidation barrier layer is
Optionally, the thickness range of described first oxide layer is
Optionally, the second semiconductor layer surface also comprised on the first region forms the second oxide layer.
Optionally, the second oxide layer be positioned on described first area has the first thickness, and described first thickness is less than the second thickness.
Optionally, the method for described oxidation processes comprises dry-oxygen oxidation or steam oxidation.
Optionally, described dry-oxygen oxidation adopts O
2as oxidizing gas, oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 10min ~ 100min.
Optionally, described steam oxidation adopts H
2o steam is as oxidizing gas, and oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 5min ~ 50min.
Optionally, adopt wet-etching technology remove described second oxide layer, the first oxide layer and oxidized after oxidation barrier layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, after forming the first oxide layer in the second semiconductor layer surface of Semiconductor substrate, being positioned at the oxidation barrier layer on the first oxide layer surface, remove the oxidation barrier layer on Semiconductor substrate second area and the 3rd region, remove the first oxide layer on Semiconductor substrate the 3rd region, then oxidation processes is carried out, the second oxide layer is formed in second semiconductor layer surface in second area and the 3rd region, the second oxide layer be positioned on second area has the second thickness, and the second oxide layer be positioned on the 3rd region has the 3rd thickness.Because second semiconductor layer surface in the 3rd region is not capped, and second area surface is covered by the first oxide layer, and surface, first area is covered by the first oxide layer and oxidation barrier layer, so described second thickness is less than the 3rd thickness.Thus remove the second oxide layer, the first oxide layer and oxidized after oxidation barrier layer after, second layer semiconductor thickness of first area is greater than the second layer semiconductor thickness of second area, second layer semiconductor thickness of second area is greater than second layer semiconductor thickness in the 3rd region, thus form the second semiconductor layer of different-thickness in the zones of different of Semiconductor substrate simultaneously, with the demand of satisfied different semiconductor device, thus the performance of the semiconductor device formed on this semiconductor structure can be improved.
Further, described oxidation barrier layer material is the material that polysilicon, silicon nitride or amorphous silicon etc. can react with oxidizing gas in oxidation processes, thus the second semiconductor layer surface can be infiltrated into by barrier oxidation gas, the second semiconductor layer of first area is oxidized.
Further, adopt wet-etching technology remove described second oxide layer, the first oxide layer and oxidized after oxidation barrier layer, compared with dry etch process, wet-etching technology has higher Etch selectivity, and, can avoid causing damage to the second semiconductor layer surface, avoid the performance affecting the follow-up semiconductor device in semiconductor layer surface formation.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the structural representation of the forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As described in the background art, in order to the transistor performance requirements of satisfied different circuit, the zones of different on insulator on silicon substrate needs the top silicon layer forming different-thickness.
In embodiments of the invention, formed the second oxide layer of different-thickness by the second semiconductor layer surface of the zones of different at Semiconductor substrate top layer, then remove described second oxide layer, thus make the second semiconductor layer of zones of different have different thickness.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises the first semiconductor layer 101, is positioned at the insulating barrier 102 on the first semiconductor layer 101 surface, is positioned at second semiconductor layer 103 on insulating barrier 102 surface, on the direction being parallel to Semiconductor substrate 100 surface, described Semiconductor substrate 100 comprises first area I, second area II and the 3rd region III.
In the present embodiment, described Semiconductor substrate 100 is silicon-on-insulator substrate (SOI), and the material of described first semiconductor layer 101 is silicon, insulating barrier 102 material is silica, the material of the second semiconductor layer 103 is silicon.
In other embodiments of the invention, described first semiconductor layer 101, second semiconductor layer 103 can also be other semi-conducting materials, such as germanium, SiGe or GaAs etc.The material of described first semiconductor layer 101 and the second semiconductor layer 103 can be identical material, also can adopt different semi-conducting materials separately.
The thickness of described second semiconductor layer 103 is generally greater than
in the present embodiment, the thickness of described second semiconductor layer 103 is
First area I, second area II and the 3rd region III of described Semiconductor substrate 100 are respectively used to form different circuit, in the present embodiment, first area I for the formation of control circuit, second area II for the formation of logical circuit, the 3rd region III for the formation of radio circuit.In the present embodiment, described first area I, second area II and the 3rd region III are adjacent area, and in other embodiments of the invention, described region I, second area II and the 3rd region III also can other regions, interval each other.
Please refer to Fig. 2, form the first oxide layer 201 on the second semiconductor layer 103 surface and be positioned at the oxidation barrier layer 202 on described first oxide layer 201 surface.
The material of described first oxide layer 201 is silica, and depositing operation or oxidation technology can be adopted to form described first oxide layer 201.
Described first oxide layer 201 has certain thickness, can to O
2or H
2the molecule of O plays certain barrier effect.Concrete, the thickness range of described first oxide layer 201 can be
in the present embodiment, the thickness of described first oxide layer is
After forming described first oxide layer 201, form oxidation barrier layer 202 on described first oxide layer 201 surface.The material of described oxidation barrier layer 202 can be combined with oxygen, stops that oxygen atom diffuses to the second semiconductor layer 201.The material of described oxidation barrier layer 202 can be polysilicon, silicon nitride or amorphous silicon etc.Depositing operation can be adopted to form described oxidation barrier layer 202, and described depositing operation can be chemical vapor deposition method, plasma enhanced chemical vapor deposition technique etc.
In the present embodiment, chemical vapor deposition method is adopted to form described oxidation barrier layer 202.Described oxidation barrier layer 202 has enough thickness, and stop that the oxygen atom in subsequent oxidation processing procedure infiltrates into the second semiconductor layer 103 surface through oxidation barrier layer 202, the thickness range of described oxidation barrier layer 202 is
in the present embodiment, the thickness of described oxidation barrier layer 202 is
Please refer to Fig. 3, remove the oxidation barrier layer 202 (please refer to Fig. 2) on Semiconductor substrate 100 second area II and the 3rd region III, expose the first oxide layer 201 surface on Semiconductor substrate 100 second area II and the 3rd region III.
Concrete, in the present embodiment, the method removing the oxidation barrier layer 202 on Semiconductor substrate 100 second area II and the 3rd region III comprises: form Patterned masking layer on described oxidation barrier layer 202 surface, described Patterned masking layer covers the oxidation barrier layer 202 on the I of first area, with described Patterned masking layer for mask, etch described oxidation barrier layer 202 to surperficial to oxide layer 201, formed and only cover the with the remaining oxidation barrier layer 202a of region I, then, described Patterned masking layer is removed.The material of described Patterned masking layer can be photoresist, silicon nitride or amorphous carbon etc.
After removing the oxidation barrier layer 202 on second area II and the 3rd region III, make follow-uply to carry out in the process of oxidation processes, oxygen atom can infiltrate into the second semiconductor layer 103 surface, makes second semiconductor layer 103 surface of second area II and the 3rd region III oxidized.
Please refer to Fig. 4, remove the first oxide layer 201 (please refer to Fig. 3) on Semiconductor substrate 100 the 3rd region III, expose Semiconductor substrate 100 the 3rd region III surface.
The method removing the first oxide layer 201 on the 3rd region III comprises: the oxidation barrier layer 202a after described etching and the first oxide layer 201 surface form Patterned masking layer, described Patterned masking layer exposes the first oxide layer 201 surface on the 3rd region III, with described Patterned masking layer for mask, etch described first oxide layer 201 to the second semiconductor layer 103 surface, remove the first oxide layer 201 be positioned on the 3rd region III.The first oxide layer 201a after etching covers second semiconductor layer 103 of second area II and first area I.Then, remove described Patterned masking layer, the material of described Patterned masking layer can be photoresist, silicon nitride or amorphous carbon etc.After removing the first oxide layer 201 on described 3rd region III, second semiconductor layer 103 of described 3rd region III is in subsequent oxidation processing procedure, more easily oxidized.
Please refer to Fig. 5, carry out oxidation processes, make described oxidation barrier layer 202 oxidized, and form the second oxide layer 203 on second semiconductor layer 103 surface of second area II and the 3rd region III.
The method of described oxidation processes comprises dry-oxygen oxidation or steam oxidation.In the present embodiment, the method for described oxidation processes is dry-oxygen oxidation technique, adopts O
2as oxidizing gas, oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 10min ~ 100min.In other embodiments of the invention, adopt steam oxidation technique, carry out described oxidation processes, described steam oxidation adopts H
2o steam is as oxidizing gas, and oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 5min ~ 50min.
Because second semiconductor layer 103 surface of the 3rd region III of described Semiconductor substrate 100 is exposed in oxidizing gas, direct generation oxidation reaction, form the second oxide layer 203 on the second semiconductor layer 103 surface, the second oxide layer 203 that second semiconductor layer 103 surface of described 3rd region III is formed has the 3rd thickness; And the second oxide layer 203 that second semiconductor layer 103 surface of second area II is formed has the second thickness.Because second semiconductor layer 103 surface coverage of second area II has the first oxide layer 201a, block the infiltration of partial oxidation gas; Due in oxidizing process, the degree of depth that oxidizing gas can permeate is limited, so the second thickness of the second oxide layer 203 formed on second semiconductor layer 103 surface of the second area II having the first oxide layer 201a to cover is less than the 3rd thickness of the second oxide layer 203 formed on the 3rd region III.If the time long enough of described oxidation processes, when the thickness of oxide layer reaches maximum, oxidizing gas cannot continue to infiltrate into the second semiconductor layer 103 surface, and now described 3rd thickness equals the thickness sum of the second thickness and the first oxide layer 201a.By the time of controlled oxidization process, described second thickness and the 3rd thickness can also be adjusted.
In the present embodiment, the first area I of Semiconductor substrate 100 is formed with oxidation barrier layer 202a, described oxidation barrier layer 202a can react with oxidizing gas in oxidation processes, and form the oxidation barrier layer 202b after oxidation, further barrier oxidation gas permeates downwards.In the present embodiment, the material of described oxidation barrier layer 202a is polysilicon, forms silica after oxidation.In other embodiments of the invention, the material of described oxidation barrier layer 202a is silicon nitride, and compactness is higher, has better oxidation barrier effect, forms the mixture comprising silica and silicon oxynitride after oxidation.In other embodiments of the invention, described oxidation barrier layer 202a can also be amorphous silicon, also forms silica after oxidation.
In the present embodiment, described oxidation barrier layer 202a has enough thickness, is stopped completely by oxidizing gas, thus second semiconductor layer 103 surface of first area I is not oxidized.
In other embodiments of the invention, the thickness of described oxidation barrier layer 202a is less, in oxidizing process, after described oxidation barrier layer 202a is fully oxidized the oxidation barrier layer 202b after forming oxidation, also have the second semiconductor layer 202a surface that certain oxidizing gas infiltrates into first area I, the second semiconductor layer 103 surface on the I of first area forms the second oxide layer, the second oxide layer on described first area I has the first thickness, and described first thickness is less than described second thickness.
Please refer to Fig. 6, remove described second oxide layer 203 (please refer to Fig. 5), the first oxide layer 201a (please refer to Fig. 5) and oxidized after oxidation barrier layer 202b (please refer to Fig. 5).
Adopt wet-etching technology remove described second oxide layer 203, first oxide layer 201a and oxidized after oxidation barrier layer 202b.In the present embodiment, adopt hydrofluoric acid solution as the etching solution of wet-etching technology.
Compared with dry etch process, wet-etching technology has higher Etch selectivity, and, can avoid causing damage to the second semiconductor layer 103 surface, avoid the performance affecting the follow-up semiconductor device formed on semiconductor layer 103 surface.
Remove described second oxide layer 203, first oxide layer 201a and oxidized after oxidation barrier layer 202b after, the second semiconductor layer 103 of formation has different thickness respectively at first area I, second area II and the 3rd region III.The second semiconductor layer 103a thickness of first area I is maximum, is applicable to forming the semiconductor device of needs compared with high working voltage, such as formation control circuit; The thickness of the second semiconductor layer 103a of the 3rd region III is minimum, significantly can reduce the FOM numerical value of the semiconductor device that the 3rd region III is formed, and is applicable to forming switch performance and requires higher high-frequency element, such as, can form radio circuit; Between the thickness of the second semiconductor layer 103a of second area II the second semiconductor layer 103a on first area I, the 3rd region III, be suitable for forming the lower semiconductor device of operating voltage, such as, form logical circuit.In the present embodiment, the thickness of the second semiconductor layer 103a on the I of first area is
the thickness of the second semiconductor layer 103a on second area II is
the thickness of the second semiconductor layer 103a on the 3rd region III is
Further, in embodiments of the invention, only need to carry out once oxidation and etching technics, form the second semiconductor layer 103a of different-thickness simultaneously in zones of different, technique is simple, and process costs is lower, and compatible with existing CMOS technology.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises: the first semiconductor layer, be positioned at the insulating barrier of the first semiconductor layer surface, be positioned at the second semiconductor layer of surface of insulating layer, be parallel on semiconductor substrate surface direction, described Semiconductor substrate comprises first area, second area and the 3rd region;
Form the first oxide layer in the second semiconductor layer surface and be positioned at the oxidation barrier layer on described first oxide layer surface;
Remove the oxidation barrier layer on Semiconductor substrate second area and the 3rd region, expose the first oxide layer surface on Semiconductor substrate second area and the 3rd region;
Remove the first oxide layer on Semiconductor substrate the 3rd region, expose Semiconductor substrate the 3rd region surface;
Carry out oxidation processes, make described oxidation barrier layer oxidized, and form the second oxide layer in second semiconductor layer surface in second area and the 3rd region, the second oxide layer be positioned on second area has the second thickness, the second oxide layer be positioned on the 3rd region has the 3rd thickness, and described second thickness is less than the 3rd thickness;
Remove described second oxide layer, the first oxide layer and oxidized after oxidation barrier layer.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, described oxidation barrier layer material is polysilicon, silicon nitride or amorphous silicon.
3. the formation method of semiconductor structure according to claim 2, is characterized in that, the thickness range of described oxidation barrier layer is
4. the formation method of semiconductor structure according to claim 1, is characterized in that, the thickness range of described first oxide layer is
5. the formation method of semiconductor structure according to claim 1, is characterized in that, the second semiconductor layer surface also comprised on the first region forms the second oxide layer.
6. the formation method of semiconductor structure according to claim 5, is characterized in that, the second oxide layer be positioned on described first area has the first thickness, and described first thickness is less than the second thickness.
7. the formation method of semiconductor structure according to claim 1, is characterized in that, the method for described oxidation processes comprises dry-oxygen oxidation or steam oxidation.
8. the formation method of semiconductor structure according to claim 7, is characterized in that, described dry-oxygen oxidation adopts O
2as oxidizing gas, oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 10min ~ 100min.
9. the formation method of semiconductor structure according to claim 7, is characterized in that, described steam oxidation adopts H
2o steam is as oxidizing gas, and oxidizing temperature is 900 DEG C ~ 1200 DEG C, and oxidization time is 5min ~ 50min.
10. the formation method of semiconductor structure according to claim 1, is characterized in that, adopt wet-etching technology remove described second oxide layer, the first oxide layer and oxidized after oxidation barrier layer.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329689B1 (en) * | 1997-08-20 | 2001-12-11 | Micron Technology, Inc. | Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates |
| CN1479350A (en) * | 2002-08-27 | 2004-03-03 | 上海宏力半导体制造有限公司 | Method of forming different thickness bigrid insulating layer |
| US20050199919A1 (en) * | 2004-03-02 | 2005-09-15 | National Institute Of Advanced Industrial Science And Technology | Semiconductor integrated circuit and method for manufacturing the same |
| US20070176180A1 (en) * | 2004-07-09 | 2007-08-02 | Au Optronics Corp. | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
| US20080128797A1 (en) * | 2006-11-30 | 2008-06-05 | International Business Machines Corporation | Structure and method for multiple height finfet devices |
| US20100276756A1 (en) * | 2008-06-30 | 2010-11-04 | Willy Rachmady | Substrate fins with different heights |
-
2015
- 2015-11-27 CN CN201510866051.7A patent/CN105489637B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329689B1 (en) * | 1997-08-20 | 2001-12-11 | Micron Technology, Inc. | Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates |
| CN1479350A (en) * | 2002-08-27 | 2004-03-03 | 上海宏力半导体制造有限公司 | Method of forming different thickness bigrid insulating layer |
| US20050199919A1 (en) * | 2004-03-02 | 2005-09-15 | National Institute Of Advanced Industrial Science And Technology | Semiconductor integrated circuit and method for manufacturing the same |
| US20070176180A1 (en) * | 2004-07-09 | 2007-08-02 | Au Optronics Corp. | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
| US20080128797A1 (en) * | 2006-11-30 | 2008-06-05 | International Business Machines Corporation | Structure and method for multiple height finfet devices |
| US20100276756A1 (en) * | 2008-06-30 | 2010-11-04 | Willy Rachmady | Substrate fins with different heights |
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| CN105489637B (en) | 2018-06-05 |
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