CN105489493A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN105489493A CN105489493A CN201410499479.8A CN201410499479A CN105489493A CN 105489493 A CN105489493 A CN 105489493A CN 201410499479 A CN201410499479 A CN 201410499479A CN 105489493 A CN105489493 A CN 105489493A
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Abstract
A manufacturing method for a semiconductor device is disclosed. The manufacturing method comprises the steps of forming a grid electrode stacked structure and a first grid electrode side wall on a substrate; performing epitaxial growth on the two sides of the first grid electrode side wall to form a lifting region; performing ion implantation for the first time, and doping the lifting region and/or the substrate to form a light-doped source-drain region; forming a second gird electrode side wall on the lifting region on the two sides of the first grid electrode side wall; performing ion implantation for the second time, and doping the lifting region and/or the substrate to form a heavily-doped source-drain region; and completing subsequent processes, and forming contact interconnection. According to the manufacturing method for the semiconductor device, the epitaxial growth of the lifted source-drain region is performed on the substrate firstly, and then the light-doped ion implantation is carried out, so that the epitaxial growth quality of the lifted source-drain region can be improved, a short-channel effect of small-size devices can be slowed down, and the performance and the reliability of the device are improved.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to the manufacture method of a kind of FinFET (FinFET).
Background technology
The current method reduced costs by single reduction characteristic size encounters bottleneck, particularly when characteristic size is down to below 150nm, a lot of physical parameter can not change in proportion, such as silicon energy gap Eg, Fermi potential φ F, interfacial state and Oxide trapped charge Qox, thermoelectric potential Vt and pn tie self-built gesture etc., and these are by device performance scaled for impact.Over nearly 30 years, semiconductor device is always according to Moore's Law scaled down, and the characteristic size of semiconductor integrated circuit constantly reduces, and integrated level improves constantly.Along with technology node enters deep-submicron field, such as, within 100nm, even within 45nm, conventional field effect transistor (FET), also be plane FET, start the restriction meeting with various basic physical law, the prospect of its scaled down is challenged.The FET of numerous new structure is developed, and to tackle the demand of reality, wherein, FinFET is exactly a kind of new construction device of having very much scaled down potentiality.
FinFET, FinFET is a kind of multiple-grid semiconductor device.Due to structural exclusive feature, FinFET becomes the device of deep submicron integrated circuit field very with prospects.As its name suggests, FinFET comprises a Fin perpendicular to the substrate of body silicon, and Fin is called as fin or fin-shaped semiconductor column, and different FinTET is separated by sti structure.Be different from conventional plane FET, the channel region of FinFET is positioned within Fin.Gate insulator and grid surround Fin in side and end face, thus form the grid at least two sides, are namely positioned at the grid on two sides of Fin; Meanwhile, by the thickness of control Fin, FinFET is made to have splendid characteristic: better short-channel effect rejection ability, better sub-threshold slope, lower off-state current, eliminates floater effect, lower operating voltage, is more conducive to scaled.
Because the fin structure of FinFET is narrower, self area and the contact area in source region, drain region are all less, therefore cause the non-essential resistance of device larger.Usually, the general flow process of industry comprises, after formation fin structure, LDD is formed at fin structure top by light dope ion implantation, after annealing activates and injects ion, the lifting of LDD epitaxial growth on top source-drain area with increase source-drain area size thus reduce contact resistance, adulterate to lifting source drain region dopant implant or at epitaxial process situ more afterwards.In LDD injection process, the materials such as the Si of fin structure top surface can to a certain degree be subject to inject ion bombardment and produce local or all decrystallized, destroy the single crystal characteristics on surface, have impact on the quality in subsequently epitaxial growing lifting source drain region, the epitaxial growth defect that bottom lifting source drain region and even top exists greatly will destroy device performance.In addition; in epitaxial growth technology; usually a technical process of baking and banking up with earth in advance can be comprised; the ion mixing LDD district by light dope ion implantation before epitaxial growth technology can order about lower to channel region diffusion at high temperature action, make short-channel effect in as the FinFET of small size device become more serious.
Summary of the invention
From the above mentioned, the object of the invention is to overcome above-mentioned technical difficulty, propose a kind of method, semi-conductor device manufacturing method, the epitaxial growth quality in lifting source drain region can be improved and slow down the short-channel effect of small size device.
For this reason, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: step 1, substrate is formed gate stack structure and first grid side wall; Step 2, forms lifting district in the epitaxial growth of first grid side wall both sides; Step 3, performs the first ion implantation, adulterates to lifting district and/or substrate, forms lightly-doped source drain region; Step 4, the lifting district of first grid side wall both sides forms second grid side wall; Step 5, performs the second ion implantation, adulterates to lifting district and/or substrate, forms heavy-doped source drain region; Step 6, completes subsequent technique, forms contact interconnection.
Wherein, substrate comprises multiple fin structure, described gate stack structure, first grid side wall, lifting district, lightly-doped source drain region, heavy-doped source drain region to be all formed on each fin structure and/or in.
Wherein, gate stack structure is the stacked structure of high K insulating barrier for first grid technique and metal conducting layer, or is the stacked structure of insulating barrier for rear grid technique and packed layer.
Wherein, comprise further before step 2, precleaning substrate surface.
Wherein, the degree of depth of the second ion implantation equals, is slightly smaller than or is a bit larger tham lifting district height and fin structure height sum
Wherein, the ion major part that second time is injected be distributed in shallow trench isolation from fin structure top and the lifting district of extension.
Wherein, second grid side wall thicknesses is greater than first grid side wall thicknesses.
Wherein, step 6 comprises further: step a, forms interlayer dielectric layer on the semiconductor device; Step b, etching interlayer dielectric layer forms source and drain contact hole, exposes heavy-doped source drain region; Step c, fills metal and forms contact plug in source and drain contact hole.
Wherein, comprise in taking a step forward of step b: selective etch is removed gate stack structure and in interlayer dielectric layer, leaves gate openings, forms second grid stacked structure in gate openings.
Present invention also offers a kind of method, semi-conductor device manufacturing method, comprising: step 1, form lifting district at substrate Epitaxial growth; Step 2, lifting district is formed gate stack structure and first grid side wall; Step 3, performs the first ion implantation, adulterates to lifting district and/or substrate, forms lightly-doped source drain region; Step 4, the lifting district of first grid side wall both sides forms second grid side wall; Step 5, performs the second ion implantation, adulterates to lifting district and/or substrate, forms heavy-doped source drain region; Step 6, completes subsequent technique, forms contact interconnection.
According to method, semi-conductor device manufacturing method of the present invention, light dope ion implantation is carried out again after substrate Epitaxial growth lifting source drain region, the epitaxial growth quality in lifting source drain region can be improved and slow down the short-channel effect of small size device, improve device performance and reliability.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 6 is the cutaway view according to each step of method, semi-conductor device manufacturing method of the present invention; And
Fig. 7 is the flow chart according to method, semi-conductor device manufacturing method of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose the epitaxial growth quality in enough raising lifting source drain regions and slow down the method, semi-conductor device manufacturing method of the short-channel effect of small size device.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process.These modify the space of not hint institute's modification device architecture or manufacturing process unless stated otherwise, order or hierarchical relationship.
As shown in Figure 1, gate stack structure 3 is formed on substrate 1, as the first step of Fig. 7.It should be noted that each accompanying drawing is not in strict accordance with scale, such as, reduce fin 1F height and exaggerate the height of lifting district 1H, only conveniently illustrate the object illustrated.
Substrate 1 is first provided, substrate 1 needs and choose reasonable according to device application, monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (StrainedSi), germanium silicon (SiGe) can be comprised, or compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc.For the consideration with CMOS technology compatibility, substrate 1 is preferably body Si.
Optional, graphically form fin structure 1F to substrate 1, also namely substrate 1 top comprises fin structure 1F.Such as, at substrate 1 top coating photoresist film and exposure imaging forms the multiple photoetching offset plate figure (not shown) extended along the first direction left and right directions of level (in the Fig. 1).With photoetching offset plate figure be mask anisotropically etched substrate 1 form multiple fin structure 1F, such as dry plasma etch or RIE, etching gas is carbon fluorine base gas (CF such as
4, CH
2f
2, CHF
3, CH
3f, C
3h
6, C
4f
8deng), or adopt TMAH wet etching for Si material.Further preferably, between multiple fin structure 1F, around by thermal oxidation, chemical oxidation, CVD (such as HDPCVD, PECVD etc.) fill formed such as silica, silicon oxynitride material insulating barrier and form shallow trench isolation from (STI) 2.It should be noted that in accompanying drawing of the present invention and diagrammatically illustrate a preferred embodiment, also namely make improvement for FinFET, but it should be noted that the present invention can also be used for the epitaxial growth in the lifting source drain region at planar MOSFET top.In other words, technical scheme of the present invention can not adopt fin structure 1F, but directly in substrate 1 active area surrounded by STI2, carries out subsequent technique, and therefore fin structure 1F is optional.
On substrate 1 end face, (on fin structure 1F) forms gate stack structure 3.Such as form gate insulator 3A, grid conducting layer 3B by techniques such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputterings, and form gate stack structure 3 by anisotropic etching subsequently.In a preferred embodiment of the invention, grid technique after adopting, therefore gate stack structure is dummy grid stacked structure 3, and dummy grid insulating barrier 3A is such as silica, and dummy grid conductive layer 3B is such as amorphous silicon, polysilicon, amorphous carbon and combination thereof.In another preferred embodiment of the present invention, adopt first grid technique, therefore gate stack structure finally retains, gate insulator 3A is hafnium, grid conducting layer 3B is metal, metal alloy, metal nitride and combination thereof, can also insert work function regulating course (not shown) between two-layer.Subsequently, at (puppet) gate stack structure 3 top, sidewall and substrate 1 on the surface and/or fin structure 1F deposits the insulating barrier 4 of such as silica, silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC) material and isotropic etching forms first grid side wall 4A.First side wall 4A only injects for following LDD, and therefore can adopt the silica that thermal oxidation or LPCVD technique are formed, thickness is usually thinner, such as only 0..8 ~ 2nm.
As shown in Figure 2, as the second step of Fig. 7, epitaxial growth lifting district 1H (also namely epitaxial growth structure is a part of higher than that of original fin 1F), is preferably located in dummy grid stacked structure 3 both sides (along first direction) on substrate 1.Preferably, adopt fluorine-based solution--such as dilute HF (dHF) solution or dilute the surface cleaning that slowly-releasing etching agent (dBOE) carries out the short time, remove substrate 1, the surperficial oxide that may exist of fin structure 1F, such as thin layer of silicon oxide.After this, the lifting district 1H adopting the process selectivity epitaxial growths such as PECVD, MOCVD, MBE, ALD identical or close with substrate 1 material.Such as, when substrate 1 is Si, 1H material in lifting district can be Si, SiGe, SiC, SiGeC, GeSn, InSn etc., and can have lattice constant resilient coating between or crystal seed layer (not shown) matches to make upper and lower two-layer lattice between substrate 1 and lifting district 1H.In the process, because gate stack structure 3 and first grid side wall 4A and STI2 are insulating material, huge with the semiconductor material lattice constant of substrate 1, therefore epitaxial growth only grows the region place of exposing at fin structure 1F or substrate 1 surface, also namely self aligned or optionally.
As shown in Figure 3, as the third step of Fig. 7, with first grid side wall 4A for mask, the first ion implantation is performed to lifting district 1H, in first grid side wall 4A lifting district and/or both sides substrate 1 (fin structure 1F), form lightly-doped source drain region (LDD structure) 1LS and 1LD.By adjusting the technological parameter such as ion weight, Implantation Energy of ion implantation, the degree of depth of injection region can be controlled.In a preferred embodiment of the invention, inject the half that the degree of depth can exceed the height of lifting district 1H, even exceedes the whole height of lifting district 1H and enter (not shown) in the fin 1F below it, but preferably injecting the degree of depth is no more than lifting district 1H and fin 1F height sum---namely lower substrate 1 is not goed deep in injection region yet.
As shown in Figure 4, as the 4th step of Fig. 7, form second grid side wall 4B in gate stack structure 3 both sides.Adopt the technique such as PECVD, HDPCVD, sputtering, the insulating barrier 4B of deposited silicon nitride, silicon oxynitride, DLC material isotropic etching forms second grid side wall 4B.Second grid side wall 4B is greater than first grid side wall 4A along the width/thickness of first direction, so that the position controlling heavy-doped source drain region makes its distance channel region far away.Second grid side wall 4B thickness is 3--10nm also preferred 5nm such as.
As shown in Figure 5, as the 5th step of Fig. 7, with second grid side wall 4B for mask, the second ion implantation is performed to lifting district 1H, in grid curb wall 4B both sides substrate 1 (fin structure 1F), form heavy-doped source drain region 1HS and 1HD.Preferably, increase ion weight and Implantation Energy, make the degree of depth of the second ion implantation exceed lifting district 1H thus enter in substrate 1 (fin structure 1F), also namely the degree of depth of the second ion implantation equals lifting district 1H height and fin 1F height sum, or be a bit larger tham this height sum, such as exceed this height sum 1 ~ 3nm, or be slightly smaller than this height sum, such as, lower than this height sum 1 ~ 3nm.In second time ion implantation process, the ion major part (more than 80% and even more than 90%, this term is only for qualitative description for such as number percent) injected be distributed in shallow trench isolation from fin structure top and extension lifting district in.
As shown in Figure 6, as the 6th step of Fig. 7, subsequent technique is completed.Such as on whole device, spin coating or CVD deposit the interlayer dielectric layer (ILD) 5 of low-k materials.For first grid technique, retain the gate stack structure 3 of high K/ metal (HKMG), direct etching ILD5 forms the contact hole (not shown) exposing lifting source drain region, fills metal in the contact hole and forms contact plug 6.For rear grid technique, selective etch removes gate stack structure 3, gate openings (not shown) is left in ILD5, the final grid structure 3 ' (not shown) of HKMG is filled in gate openings, etch ILD5 subsequently and form the contact hole (not shown) exposing lifting source drain region, fill metal in the contact hole and form contact plug 6.Finally, can each layer of planarization until expose gate stack structure 3/3 '.
In addition, illustrations 1,2 only illustrates the operation first forming gate stack structure 3 then extension, but the application also can adopt first on fin 1F extension form lifting district 1H, then deposition of gate stacked structure 3.In other words, the step 1 shown in Fig. 7,2 can sequentially be exchanged.
According to method, semi-conductor device manufacturing method of the present invention, light dope ion implantation is carried out again after substrate Epitaxial growth lifting source drain region, the epitaxial growth quality in lifting source drain region can be improved and slow down the short-channel effect of small size device, improve device performance and reliability.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (10)
1. a method, semi-conductor device manufacturing method, comprising:
Step 1, substrate is formed gate stack structure and first grid side wall;
Step 2, forms lifting district in the epitaxial growth of first grid side wall both sides;
Step 3, performs the first ion implantation, adulterates to lifting district and/or substrate, forms lightly-doped source drain region;
Step 4, the lifting district of first grid side wall both sides forms second grid side wall;
Step 5, performs the second ion implantation, adulterates to lifting district and/or substrate, forms heavy-doped source drain region;
Step 6, completes subsequent technique, forms contact interconnection.
2. method as claimed in claim 1, wherein, substrate comprises multiple fin structure, described gate stack structure, first grid side wall, lifting district, lightly-doped source drain region, heavy-doped source drain region to be all formed on each fin structure and/or in.
3. method as claimed in claim 1, wherein, gate stack structure is the stacked structure of high K insulating barrier for first grid technique and metal conducting layer, or is the stacked structure of insulating barrier for rear grid technique and packed layer.
4. method as claimed in claim 1, wherein, comprises, precleaning substrate surface before step 2 further.
5. method as claimed in claim 2, wherein, the degree of depth of the second ion implantation equals, is a bit larger tham or is slightly smaller than lifting district height and fin structure height sum.
6. method as claimed in claim 5, the ion major part that second time is injected be distributed in shallow trench isolation from fin structure top and the lifting district of extension.
7. method as claimed in claim 1, wherein, second grid side wall thicknesses is greater than first grid side wall thicknesses.
8. method as claimed in claim 1, wherein, step 6 comprises further:
Step a, forms interlayer dielectric layer on the semiconductor device;
Step b, etching interlayer dielectric layer forms source and drain contact hole, exposes heavy-doped source drain region;
Step c, fills metal and forms contact plug in source and drain contact hole.
9. method as claimed in claim 8, wherein, comprises in taking a step forward of step b: selective etch is removed gate stack structure and in interlayer dielectric layer, leaves gate openings, forms second grid stacked structure in gate openings.
10. a method, semi-conductor device manufacturing method, comprising:
Step 1, forms lifting district at substrate Epitaxial growth;
Step 2, lifting district is formed gate stack structure and first grid side wall;
Step 3, performs the first ion implantation, adulterates to lifting district and/or substrate, forms lightly-doped source drain region;
Step 4, the lifting district of first grid side wall both sides forms second grid side wall;
Step 5, performs the second ion implantation, adulterates to lifting district and/or substrate, forms heavy-doped source drain region;
Step 6, completes subsequent technique, forms contact interconnection.
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| CN201410499479.8A CN105489493A (en) | 2014-09-25 | 2014-09-25 | Manufacturing method for semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090149012A1 (en) * | 2004-09-30 | 2009-06-11 | Brask Justin K | Method of forming a nonplanar transistor with sidewall spacers |
| US20120012932A1 (en) * | 2010-07-15 | 2012-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (finfet) device and method of manufacturing same |
| US20140061734A1 (en) * | 2012-08-31 | 2014-03-06 | International Business Machines Corporation | Finfet with reduced parasitic capacitance |
| CN105470133A (en) * | 2014-09-06 | 2016-04-06 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
-
2014
- 2014-09-25 CN CN201410499479.8A patent/CN105489493A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090149012A1 (en) * | 2004-09-30 | 2009-06-11 | Brask Justin K | Method of forming a nonplanar transistor with sidewall spacers |
| US20120012932A1 (en) * | 2010-07-15 | 2012-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (finfet) device and method of manufacturing same |
| US20140061734A1 (en) * | 2012-08-31 | 2014-03-06 | International Business Machines Corporation | Finfet with reduced parasitic capacitance |
| CN105470133A (en) * | 2014-09-06 | 2016-04-06 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
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Application publication date: 20160413 |
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