CN105469828B

CN105469828B - A kind of high speed sense amplifier

Info

Publication number: CN105469828B
Application number: CN201510695077.XA
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2015-10-22
Filing date: 2015-10-22
Publication date: 2019-09-17
Anticipated expiration: 2035-10-22
Also published as: CN105469828A

Abstract

The invention discloses a kind of high speed sense amplifiers, including traditional sense amplifier circuit, the high speed sense amplifier further includes a quick discharging circuit and comparison circuit, described quick discharging circuit one end connects the bit line output voltage of traditional sense amplifier circuit, the other end connects reference voltage, for the bit line output voltage to be dropped quickly to the reference voltage, two input terminal of comparison circuit is separately connected the bit line output voltage and the reference voltage, its output end exports the output of the high speed sense amplifier, through the invention, the reading rate of NOR flash memory can be improved.

Description

A kind of high speed sense amplifier

Technical field

The present invention relates to a kind of high speed sense amplifiers, amplify more particularly to a kind of high speed sensitivity applied to flash Device.

Background technique

Fig. 1 is the circuit diagram of sensitive (reading) amplifier (Traditional sense amplifier) of tradition.Such as Shown in Fig. 1, PMOS tube P1-2 forms mirror-image constant flow source, and by reference memory unit current source Irefcell, mirror image is exported in proportion (being illustrated as 30%), PMOS tube P3 are pre-charge circuit, and output and mirror-image constant flow source output are by by NMOS tube N1 and touching The read-out control circuit of hair phase inverter INV1 composition is connected to bit line BL, and CBL is that equivalent capacity, N2 are the storage chosen to bit line over the ground Unit cell, bit line BL are connected to comparator inverting input terminal, the connection reference of comparator non-inverting input terminal through read-out control circuit Voltage Vref_e, output obtain the output dout of sense amplifier after buffer Buf1-2 buffering.

PMOS tube P1-3 source electrode meets supply voltage vdd, and the drain electrode of the grid and P1 of PMOS tube P1-2 is connected to reference to storage The output of unit current source Irefcell, the drain electrode of PMOS tube P2-3 and the drain electrode of NMOS tube N1 and comparator inverting input terminal It is connected to form node e, the grid of PMOS tube P3 connects precharge control signal Precharge_enb, and the source electrode of NMOS tube N1 connects The input terminal of bit line BL and triggering phase inverter INV1, the grid of the output end connection NMOS tube N1 of triggering phase inverter INV1, by It controls in reading enable signal SEN, storage unit cell control grid is chosen to meet wordline WL, the non-inverting input terminal of comparator CMP1 connects Reference voltage Vref _ e is met, comparator CMP1 is controlled by comparator enable signal SEN2, and output connection buffer Buf1's is defeated Enter end, the input terminal of the output end connection buffer Buf2 of buffer Buf1, the output of buffer Buf2 is sense amplifier Export dout.

Fig. 2 and Fig. 3 is respectively that traditional sense amplifier reads 1 and reads 0 signal timing diagram.When reading beginning, decoding circuit Choosing designated memory cell cell, wordline WL is height, reads enable signal SEN and is got higher by low, and triggering phase inverter INV1 work makes It obtains NMOS tube N1 grid voltage to be connected to be high, while precharge control signal Precharge_enb is lower by height, PMOS tube P3 Conducting, supply voltage vdd are pre-charged by NMOS tube N1 to bit line BL, and node e voltage (being approximately bit line BL voltage) rises rapidly Up to storage unit sets voltage needed for reading, and precharge control signal Precharge_enb is got higher by low at this time, PMOS tube P3 Cut-off, if storage unit store " 1 " signal, should " 1 " signal storage unit can be made to have electric current to flow through, thus bit line BL voltage or Node e voltage will be reduced due to the electric current of storage unit, and after waiting time Tsen2, which, which drops to, examines voltage Vref_e, comparator control signal SEN2 are got higher by low, and comparator CMP1 is opened, with the further decline of node e voltage, etc. Comparator CMP1 stablizes output high level after time Tcomparator, and it is that sense amplifier is defeated that dout is exported after buffering Location information " 1 " out, if storage unit stores " 0 " signal, being somebody's turn to do " 0 " signal will not make storage unit have electric current stream It crosses, so that bit line BL voltage or node e voltage will keep setting voltage constant, after waiting the Tsen2 time, comparator controls signal SEN2 is got higher by low, comparator CMP1 open, due to the constant of node e voltage and be higher than examine voltage Vref_e, waiting time Comparator CMP1 stablizes output low level after Tcomparator, and it is depositing for sense amplifier output that dout is exported after buffering Storage unit information " 0 ".

As it can be seen that traditional sense amplifier drops to reference voltage Vref _ e from pre-charge voltage and needs to wait for time Tsen2, lead Cause the reading rate of traditional sense amplifier slower.

Summary of the invention

In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of high speed sense amplifier, Its reading rate that NOR flash memory (NOR flash) can be improved.

In order to achieve the above object, the present invention proposes a kind of high speed sense amplifier, including traditional sense amplifier circuit, the height Fast sense amplifier further includes a quick discharging circuit and comparison circuit, and it is quick that described quick discharging circuit one end connects the tradition Feel the bit line output voltage of amplifier circuit, the other end connects reference voltage, for dropping quickly to the bit line output voltage The reference voltage, two input terminal of comparison circuit are separately connected the bit line output voltage and the reference voltage, and output end is defeated The output of the high speed sense amplifier out.

Further, which includes a transmission gate.

Further, which includes one by the second phase inverter, the 4th PMOS tube and third NMOS tube group At transmission gate, the transmission gate one end connect bit line output voltage, the other end connect reference voltage, the 4th PMOS tube grid connect The output of second phase inverter is connect, the input terminal of second phase inverter and the grid of third NMOS tube are connected to narrow pulse signal.

Further, which includes at least a comparator and buffer, and two input terminals of the comparator connect respectively The bit line output voltage and the reference voltage are connect, output obtains the output of the high speed sense amplifier after buffer buffers.

Further, the homophase input of the comparator terminates the bit line output voltage, and anti-phase input terminates the reference voltage.

Further, which is controlled by a comparator enable signal.

Further, which is multiple.

Further, which includes the mirror image constant current being made of the first PMOS tube and the second PMOS tube Pre-charge circuit that source, third PMOS tube are constituted, by the first NMOS tube and the read-out control circuit that forms of triggering phase inverter.

Further, mirror image exports the mirror-image constant flow source reference memory unit current source in proportion.

Further, the generating circuit from reference voltage for generating the reference voltage includes the 5th PMOS tube, the 4th NMOS tube, zero Threshold value pipe, triggering phase inverter, the first reference current source, the second reference current source and filter capacitor, for reading enabled letter Reference voltage needed for generating the sense amplifier under number control, the 5th PMOS tube source electrode connects supply voltage, and grid connects It controls signal (EN), drain electrode connects the drain electrode of the 4th NMOS tube and the drain electrode of zero threshold value pipe, and the 4th NMOS tube source electrode connects first reference Current source and the triggering inverter input, the triggering inverter output connect the 4th NMOS tube grid and the zero threshold value pipe grid Pole, the triggering phase inverter are controlled by reading enable signal, which connects second reference current source and filter capacitor.

Compared with prior art, a kind of high speed sense amplifier of the present invention utilizes quick discharging circuit by bit line output voltage Reference voltage is dropped quickly to, the reading rate of NOR flash memory (NOR flash) is improved.

Detailed description of the invention

Fig. 1 is the circuit diagram of sensitive (reading) amplifier (Traditional sense amplifier) of tradition；

Fig. 2 and Fig. 3 is respectively that traditional sense amplifier reads 1 and reads 0 signal timing diagram；

Fig. 4 is a kind of circuit structure diagram of high speed sense amplifier of the present invention；

Fig. 5 is the circuit diagram of generating circuit from reference voltage in present pre-ferred embodiments；

Fig. 6 and Fig. 7 is respectively that present pre-ferred embodiments read 1 and read 0 signal timing diagram；

Fig. 8 is a kind of emulation schematic diagram of high speed sense amplifier of the present invention.

Specific embodiment

Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from Various modifications and change are carried out under spirit of the invention.

Fig. 4 is a kind of circuit structure diagram of high speed sense amplifier of the present invention.As shown in figure 4, a kind of high speed of the present invention is quick Feel amplifier, including traditional sense amplifier circuit 10, comparison circuit 20 and quick discharging circuit 30.

Wherein, traditional sense amplifier circuit 10 include PMOS tube P1-2 composition mirror-image constant flow source, PMOS tube P3, by The read-out control circuit of NMOS tube N1 and triggering phase inverter INV1 composition, mirror-image constant flow source is by reference memory unit current source Irefcell in proportion mirror image output (being illustrated as 30%, but not limited to this), PMOS tube P3 be pre-charge circuit, output and Mirror-image constant flow source output is connected to bit line BL, C by the read-out control circuit being made of NMOS tube N1 and triggering phase inverter INV1_BL For bit line, equivalent capacity, N2 are the storage unit cell chosen over the ground, and bit line BL is connected to comparison circuit through read-out control circuit 20 non-inverting input terminal and one end of quick discharging circuit 30,30 other end of quick discharging circuit and the reverse phase of comparison circuit 20 are defeated Enter end connection reference voltage Vref _ e, quick discharging circuit 30 is used to bit line output voltage dropping quickly to reference voltage Vref_e, in a preferred embodiment of the present invention, quick discharging circuit 30 be typically include one by phase inverter INV2, PMOS tube P4 with And the transmission gate (but not limited to this) of NMOS tube N3 composition, the transmission gate one end connect bit line output voltage, other end connection Reference voltage Vref _ e；Comparison circuit 20 includes comparator CMP1 and buffer Buf1, the non-inverting input terminal of comparator CMP1 Bit line output voltage is connect, anti-phase input terminates reference voltage Vref _ e, and output obtains sensitive put after buffer Buf1 buffering The output dout of big device.

Specifically, the PMOS tube P1-3 source electrode of traditional sense amplifier circuit 10 meets supply voltage vdd, PMOS tube P1-2's The drain electrode of grid and P1 are connected to the output of reference memory unit current source Irefcell, the drain electrode and NMOS tube of PMOS tube P2-3 The drain electrode of N1 and comparator non-inverting input terminal are connected to form node e (e point voltage is referred to as bit line output voltage), PMOS tube P4, NMOS tube N3 and phase inverter INV2 form transmission gate, one end connecting node e, and the other end connects reference voltage Vref _ e, pass The output of the PMOS tube P4 grid connection phase inverter INV2 of defeated door control, the input terminal and transmission gate NMOS tube N3 of phase inverter INV2 Grid be connected to narrow pulse signal SEN_E, the grid of PMOS tube P3 connects precharge control signal Precharge_enb, The source electrode of NMOS tube N1 meets bit line BL and triggers the input terminal of phase inverter INV1, and the output end of triggering phase inverter INV1 connects NMOS The grid of pipe N1 is controlled by and reads enable signal SEN, and storage unit cell control grid is chosen to connect wordline WL, comparator The inverting input terminal of CMP1 connects reference voltage Vref _ e, and comparator CMP1 is controlled by comparator enable signal SEN2, exports The input terminal of buffer Buf1 is connected, the output of buffer Buf1 is the output dout of sense amplifier, in the present invention, node E be connected to comparator same phase or inverting input terminal and output connection buffer number it is related to system, do not make herein It limits.

Fig. 5 is the circuit diagram of generating circuit from reference voltage in present pre-ferred embodiments.Specifically, reference voltage produces Raw circuit includes PMOS tube P5, NMOS tube N4, zero threshold value pipe N5, triggering phase inverter INV3, reference current source I1-2 and filtering Capacitor Cref, reference voltage Vref needed for being used under reading enable signal control generate reading circuit (sense amplifier) _ E, PMOS tube P5 source electrode meet supply voltage vdd, and grid meets control signal EN, and drain electrode connects NMOS tube N4 drain electrode and zero threshold value pipe N5 drain electrode, NMOS tube N4 source electrode meet reference current source I1 and triggering phase inverter INV3 input terminal, trigger phase inverter INV3 output end NMOS tube N4 grid and zero threshold value pipe N5 grid are connect, triggering phase inverter INV3 is controlled by reading enable signal, zero source threshold value pipe N5 Pole meets reference current source I2 and filter capacitor Cref.

Fig. 6 and Fig. 7 is respectively that present pre-ferred embodiments read 1 and read 0 signal timing diagram.Below cooperation Fig. 6 and Fig. 7 into One step illustrates the present invention:

1) when reading beginning, it is height that decoding circuit, which chooses designated memory cell cell, wordline WL, reads enable signal SEN It is got higher by low, triggering phase inverter INV1 works so that NMOS tube N1 grid voltage is high and is connected, while precharge control signal Precharge_enb is lower by height, and PMOS tube P3 conducting, supply voltage vdd is pre-charged by NMOS tube N1 to bit line BL, node E voltage (being approximately bit line BL voltage) is quickly raised to set voltage needed for storage unit is read, at this time precharge control signal Precharge_enb is got higher by low, and PMOS tube P3 cut-off, precharge terminates, when precharge control signal Precharge_enb by Low system when get higher generates burst pulse (pluse) signal SEN_E (pulse width < 1ns), the high level wink of SEN_E Between open the transmission gate that is made of NMOS tube N3 and PMOS tube P4 and phase inverter INV2, transmission gate conducting makes the voltage of node e Moment is pulled to reference voltage Vref _ e, disconnects transmission gate since narrow pulse signal SEN_E is lower later, thus node e electricity Ballast is newly controlled by the control of storage unit cell:

If storage unit stores " 1 " signal, being somebody's turn to do " 1 " signal can make storage unit have electric current to flow through, thus bit line BL electricity Pressure or node e voltage will be reduced since Vref_e due to the electric current of storage unit, wait burst pulse high level lasting time After Tsen_e, comparator control signal SEN2 is got higher by low, and comparator CMP1 is opened, with the further decline of node e voltage, Comparator CMP1 stablizes output high level after waiting time Tcomparator, and it is sense amplifier that dout is exported after buffering The location information " 1 " of output；If storage unit stores " 0 " signal, being somebody's turn to do " 0 " signal will not make storage unit have electric current stream It crosses, so that bit line BL voltage or node e voltage will keep setting voltage constant, waits burst pulse high level lasting time Tsen_e Afterwards, comparator control signal SEN2 is got higher by low, and comparator CMP1 is opened, due to the charging current of mirror-image constant flow source efferent duct P2 Charging effect, node e voltage reduces raising since Vref_e, comparator CMP1 stabilization after waiting time Tcomparator Low level is exported, the location information " 0 " that dout is sense amplifier output is exported after buffering.

Fig. 8 is a kind of emulation schematic diagram of high speed sense amplifier of the present invention.As it can be seen that the sense amplifier of the present invention is comparable The reading rate of NOR flash memory (NOR flash) can be improved in traditional fast Tsen2-Tsen_e of sense amplifier, the present invention.

In conclusion a kind of high speed sense amplifier of the present invention using quick discharging circuit by bit line output voltage it is quick under It is down to reference voltage, improves the reading rate of NOR flash memory (NOR flash).

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore, The scope of the present invention, should be as listed in the claims.

Claims

1. a kind of high speed sense amplifier, including traditional sense amplifier circuit, it is characterised in that: the high speed sense amplifier is also Including a quick discharging circuit and comparison circuit, described quick discharging circuit one end connects traditional sense amplifier circuit Bit line output voltage, the other end connects reference voltage, described for the bit line output voltage to be dropped quickly to the reference voltage Two input terminal of comparison circuit is separately connected the bit line output voltage and the reference voltage, and output end exports the sensitive amplification of the high speed The output of device.

2. a kind of high speed sense amplifier as described in claim 1, it is characterised in that: the quick discharging circuit includes a transmission Door.

3. a kind of high speed sense amplifier as claimed in claim 2, it is characterised in that: the quick discharging circuit includes one by the The transmission gate of two phase inverters, the 4th PMOS tube and third NMOS tube composition, the transmission gate one end connect bit line output voltage, separately One end connects reference voltage, and the 4th PMOS tube grid connects the output of second phase inverter, the input terminal of second phase inverter Narrow pulse signal is connected to the grid of third NMOS tube.

4. a kind of high speed sense amplifier as claimed in claim 3, it is characterised in that: the comparison circuit includes at least one and compares Device and buffer, two input terminals of the comparator are separately connected the bit line output voltage and the reference voltage, export through buffering The output of the high speed sense amplifier is obtained after device buffering.

5. a kind of high speed sense amplifier as claimed in claim 4, it is characterised in that: the homophase input termination of the comparator should Bit line output voltage, anti-phase input terminate the reference voltage.

6. a kind of high speed sense amplifier as claimed in claim 5, it is characterised in that: the comparator is controlled by a comparator and makes It can signal.

7. a kind of high speed sense amplifier as claimed in claim 4, it is characterised in that: the buffer number is multiple.

8. a kind of high speed sense amplifier as described in claim 1, it is characterised in that: the tradition sense amplifier includes by the One PMOS tube and the second PMOS tube composition mirror-image constant flow source, third PMOS tube constitute pre-charge circuit, by the first NMOS tube With the read-out control circuit of triggering phase inverter composition.

9. a kind of high speed sense amplifier as claimed in claim 8, it is characterised in that: the mirror-image constant flow source will be single with reference to storage Mirror image exports in proportion in elementary current source.

10. a kind of high speed sense amplifier as claimed in claim 8, it is characterised in that: generate the reference electricity of the reference voltage Pressing generation circuit includes the 5th PMOS tube, the 4th NMOS tube, zero threshold value pipe, triggering phase inverter, the first reference current source, the second ginseng Examine current source and filter capacitor, for read enable signal control under generate the sense amplifier needed for reference voltage, The 5th PMOS tube source electrode connects supply voltage, and grid connects control signal (EN), and drain electrode meets the drain electrode of the 4th NMOS tube and zero The drain electrode of threshold value pipe, the 4th NMOS tube source electrode connect first reference current source and the triggering inverter input, the triggering phase inverter Output the 4th NMOS tube grid of termination and the zero threshold value tube grid, the triggering phase inverter are controlled by reading enable signal, this zero Threshold value pipe source electrode connects second reference current source and filter capacitor.