CN102881318B

CN102881318B - Sensitive amplifier used in static random access memory (RAM)

Info

Publication number: CN102881318B
Application number: CN201110195689.4A
Authority: CN
Inventors: 杨昌楷; 张建杰; 熊冰; 温芝权
Original assignee: SUZHOU XIONGLI TECHNOLOGY Co Ltd
Current assignee: SUZHOU XIONGLI TECHNOLOGY Co Ltd
Priority date: 2011-07-13
Filing date: 2011-07-13
Publication date: 2015-02-18
Anticipated expiration: 2031-07-13
Also published as: CN102881318A

Abstract

The invention discloses a sensitive amplifier used in a static RAM. The sensitive amplifier comprises a latch amplification circuit, a pulse generation sub-circuit and a pulse end judgment sub-circuit, wherein the pulse end judgment sub-circuit judges whether the read-write operation of the static memory ends or not through detecting the voltage signal on the latch bit line of the global latch of the static RAM, and a low-level pulse is output to control the sensitive amplifier to stop running when the detected voltage signal on the latch bit line has a low level. The pulse width of the pulse generated by the pulse generation sub-circuit automatically adapts to the work demand of the latch amplification circuit, so the reliability of the sensitive amplifier is improved.

Description

A kind of sense amplifier be applied in static RAM

Technical field

The application relates to static RAM technical field, particularly relates to a kind of sense amplifier be applied in static RAM.

Background technology

The read-write operation of random access memory be by control circuit and word line driver to drive enable wordline, the voltage difference by a small margin on two complementary bit lines is amplified through sense amplifier, reaches high level or low level scope.When carrying out read operation, the logic level signal after sense amplifier amplifies is delivered in global lock storage, is finally pinned by latch and reads this logic level signal.The reliability effect data write of sense amplifier or the correctness of reading, and then the acceptance rate of static RAM can be affected.

Sense amplifier, mainly comprise latch type amplifying circuit and pulse-generating circuit, when the Enable Pin of sense amplifier is high level, voltage difference on two bit lines is transferred in latch-type amplifying circuit, when the voltage difference on two bit lines reaches preset value, the control circuit of static RAM makes the Enable Pin of described amplifier become low level, now pulse-generating circuit produces high level pulse, cut off the carrying path of bit line to latch-type amplifying circuit, make the work of latch-type amplifying circuit simultaneously, the voltage difference of the small-signal received by described latch-type amplifying circuit is amplified to logic level, write random memory unit, or read by overall latches, until when pulse-generating circuit produces low level, sensitive-type amplifier is quit work, thus the read-write operation terminated static RAM.

Pulse-generating circuit in traditional sense amplifier is made up of the phase inverter be connected in series, the time of the high level pulse produced is determined by the delay time of phase inverter, therefore, be difficult to accurately control the high level pulse lasting time, if the high level pulse duration is long, will greatly reduce the read or write speed of static RAM; If the high level pulse duration is too short, sense amplifier will be caused correctly not read and write.

Summary of the invention

For solving the problems of the technologies described above, the embodiment of the present application provides a kind of sense amplifier being applied to static RAM, can according to the self-adjusting gating pulse of the state of sense amplifier to make the pulse-generating circuit in sensitive-type amplifier produce width, technical scheme is as follows:

A kind of sense amplifier being applied to static RAM, comprise: the series arm of being connected by two groups of PMOS and NMOS tube is connected in parallel the latch-type amplifying circuit formed, described in described two groups of series arms, the common point of PMOS and NMOS tube is connected to two bit lines respectively by two transfer tubes, and the common point of described PMOS in described two groups of series arms and NMOS tube two of being connected in overall latch cicuit respectively by phase inverter and switching tube latch lines, the end of described series arm connects earth terminal by switching tube, also comprises:

The pulse-generating circuit be connected with described latching amplification circuit, this pulse-generating circuit comprises: pulses generation electronic circuit and end-of-pulsing decision circuit, wherein:

Two input ends of described end-of-pulsing decision circuit connect described two respectively and latch bit line, and output terminal connects the input end of described pulses generation electronic circuit, controls the duty of described pulses generation electronic circuit; Meanwhile, the output terminal of this end-of-pulsing decision circuit connects the control end of the switching tube in described latch-type amplifying circuit, controls the duty of latch-type amplifying circuit;

When described reception of impulse decision circuit detects the low level signal on described latch bit line, export end-of-pulsing control signal, control latch-type amplifying circuit and quit work.

Preferably, described latch-type amplifying circuit mainly comprises: the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, wherein:

The first end of described first PMOS connects direct supply, second end of described first PMOS is connected with the first end of described first NMOS tube, the control of described first PMOS is connected with the control end of described first NMOS tube, and the second end of described first NMOS tube is by the first switching tube of being connected in series and second switch pipe ground connection;

Described second PMOS is connected with described second NMOS tube and is formed series arm, and this series arm is connected in parallel on the series arm two ends of described first PMOS and the first NMOS tube formation;

Described first PMOS is connected positive bit line with the common point of described first NMOS tube by the 3rd switching tube, and this common point is connected to one article of latch bit line by the first phase inverter and the 4th switching tube, the input end of described first phase inverter connects described common point, the output terminal of this first phase inverter connects the control end of described 4th switching tube, the first end ground connection of described 4th switching tube, the second end connects described another and latches bit line;

Described second PMOS is connected negative bit line with the common point of the second NMOS tube by the 5th switching tube, and this common point is connected to latch bit line by the second phase inverter and the 6th switching tube, the input end of described second phase inverter connects described common point, the output terminal of this second phase inverter connects the control end of described 6th switching tube, the first end ground connection of described 6th switching tube, the second end connects described latch bit line.

Preferably, described end-of-pulsing decision circuit specifically comprises: the first Sheffer stroke gate, the 3rd phase inverter, rest-set flip-flop, and described pulses generation electronic circuit comprises: the second Sheffer stroke gate and the 5th phase inverter, wherein

The first input end of the first Sheffer stroke gate is connected with latch bit line, and the second input end is connected with latch bit line, and output terminal connects the input end of described 3rd phase inverter;

The reset terminal of described rest-set flip-flop connects the output terminal of described 3rd phase inverter, the set end of described rest-set flip-flop connects the output terminal of the 4th phase inverter, the input end of the 4th phase inverter connects the Enable Pin of described sensitive-type amplifier, the output terminal of described rest-set flip-flop connects the control end of the second switch pipe in described latch-type amplifying circuit, and the output terminal of this rest-set flip-flop connects the first input end of described second Sheffer stroke gate, the output terminal of this second Sheffer stroke gate connects the input end of described 5th phase inverter, the output terminal of the 5th phase inverter is connected to the control end of described 3rd switching tube and the 5th switching tube, and the second input end of described second Sheffer stroke gate connects the output terminal of described 4th phase inverter,

Meanwhile, the output terminal of described 4th phase inverter connects the control end of described first switching tube.

Preferably, described first switching tube, described second switch pipe, the 4th switching tube and the 6th switching tube are NMOS tube, and first end is drain electrode, and the second end is source electrode, and control end is grid.

Preferably, described 3rd switching tube and the 5th switching tube are PMOS, and first end is drain electrode, the second end is source electrode, and control end is grid.

The technical scheme provided from above the embodiment of the present application, pulse-generating circuit is realized by pulses generation electronic circuit and end-of-pulsing decision circuit, this end-of-pulsing decision circuit, by detecting the voltage signal on the latch bit line of the global lock storage of static RAM, judge whether the read-write operation of this static memory terminates, when detecting that the voltage signal on described latch bit line is low level, the pulse of output low level, control sense amplifier quits work, the pulse width of the pulse that this pulse-generating circuit produces adapts to the work requirements of latch-type amplifying circuit automatically, can not along with the change of the manufacture craft of components and parts in circuit, the change of working environment and change the width exporting pulse, thus improve the reliability of sense amplifier.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the schematic block circuit diagram of a kind of sense amplifier of the embodiment of the present application;

Fig. 2 is the concrete electrical block diagram of a kind of sense amplifier of the embodiment of the present application;

Fig. 3 is the circuit theory diagrams of a kind of overall latch cicuit of the embodiment of the present application;

The oscillogram of sensitive-type amplifier of Fig. 4 for providing for the embodiment of the present application

Fig. 5 is the oscillogram of traditional sense amplifier.

Embodiment

Technical scheme in the application is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all should belong to the scope of the application's protection.

Refer to Fig. 1, show the circuit theory schematic diagram of a kind of sense amplifier be applied in static RAM of the embodiment of the present application, this sense amplifier mainly comprises: latch-type amplifying circuit 100, pulse-generating circuit 200, wherein:

Latch-type amplifying circuit 100 by two groups of PMOS and NMOS tube in series, there is latch enlarging function.

Pulse-generating circuit 200, comprises pulses generation electronic circuit 210 and end-of-pulsing decision circuit 220, wherein:

Two input ends of end-of-pulsing decision circuit 220, two of connecting respectively in the overall latch cicuit in static RAM latch bit line GBL (Global bit line, global bit line) and GBLN (Globalbit line Negative, anti-phase global bit line), the output terminal of described end-of-pulsing decision circuit 220 connects the control end of the switching tube in described latch-type amplifying circuit 100 by rest-set flip-flop, for controlling the duty of described latch-type amplifying circuit 100.

Described end-of-pulsing decision circuit 220 detect described two latch in bit line GBL or GBLN any one for low level time, export end-of-pulsing control signal, control described latch-type amplifying circuit 100 and quit work.

When latch-type amplifying circuit has completed after by low level signal amplification to logic level signal, when will there is low level in described latch bit line, now, end-of-pulsing decision circuit 220 can produce the magnifying state that low level signal closes described latch-type amplifying circuit 100, the pulse signal that this pulse-generating circuit produces can according to the pulse of the work requirements output adaptive of described latch-type amplifying circuit, thus, there will not be the duty due to sense amplifier to affect read or write speed and the accuracy of static RAM.

Refer to Fig. 2, show a kind of electrical block diagram being applied to the sense amplifier of static RAM, describe the embodiment of latch-type amplifying circuit and pulse-generating circuit in detail, thus introduce the course of work of this sense amplifier in detail.

Latch-type amplifying circuit 100, mainly comprises the first PMOS P1, the second PMOS P0, the first NMOS tube N1, the second NMOS tube N0, wherein:

The first end of the first PMOS P1 connects direct supply Vdd, and the second end connects the first end of the first NMOS tube N1, and control end is connected with the control end of the first NMOS tube N1; Second end of the first NMOS tube N1 is by the first switching tube N2 and second switch pipe N3 ground connection, and the first switching tube N2 and second switch pipe N3 connects.

Second PMOS P0 and the second NMOS tube N0 is connected in parallel on the series arm two ends that the first PMOS P1 and the first NMOS tube N0 is formed after connecting, concrete, the first end that the first end of the 2nd PMIOS pipe P1 connects the first PMOS P1 is connected, second end of the second PMOS P0 is connected with the first end of the second NMOS tube N0, and the control end of the second PMOS P0 is connected with the control end of the second NMOS tube N0; Second end of the second NMOS tube N0 connects second end of described first NMOS tube N1.

And, the control end of described first PMOS P1 is by being connected with the control end of the second PMOS P0, wherein, the control end of described first PMOS P1 connects the first end of PMOS P2, the control end of the second PMOS P0 connects second end of PMOS P2, and the control end of PMOS P2 connects the output terminal SE of described rest-set flip-flop.

Voltage signal on bit line BL (Bit Line, bit line) and BLN (Bit Line Negative, anti-phase bit line) transfers to described latch-type amplifying circuit 100 and carries out differential amplification, and concrete structure is as follows:

Described first PMOS P1 is connected with bit line BL by the 3rd switching tube P3 with the points of common connection of the first NMOS tube N1, wherein, the first end of the 3rd switching tube P3 is connected with described with second end of the first PMOS P1, second end of the 3rd switching tube P3 connects described bit line BL, and the control end of the 3rd switching tube P3 connects the output terminal of described pulses generation electronic circuit 210.

Described second PMOS P0 is connected described bit line BLN with the points of common connection of the second NMOS tube N0 by the 5th switching tube P4, wherein, the first end of the 5th switching tube P4 connects second end of described second PMOS P0, second end of the 5th switching tube P4 connects described bit line BLN, and the control end of described five PMOS P4 connects the output terminal of described pulses generation electronic circuit 210.

The output signal of described latch-type amplifying circuit is transferred to global bit line GBL and GBLN, and concrete structure is as follows:

Described first PMOS P1 is connected latch bit line GBL by the first phase inverter I10 with the 4th switching tube N6 with the points of common connection of the first NMOS tube N1, wherein, second end of described first PMOS P1 connects the input end of described first phase inverter I10, the output terminal of the first phase inverter I10 connects the control end of described 4th switching tube N6, the first end ground connection of the 4th switching tube N6, second end of the 4th switching tube N6 connects latch bit line GBL.

Described second PMOS P0 is connected described latch line GBLN by the second phase inverter I9 with the 6th switching tube N7 with the points of common connection of the second NMOS tube N0, wherein, second end of described second PMOS P0 connects the input end of the second phase inverter I9, the output terminal of the second phase inverter I9 connects the control end of described 6th switching tube N7, the first end ground connection of the 6th switching tube N7, the second end connects latch bit line GBLN.

Described pulse-generating circuit 200, comprises pulses generation electronic circuit 210 and end-of-pulsing decision circuit 220, wherein:

Described end-of-pulsing decision circuit 220 comprises: the first Sheffer stroke gate I37, the 3rd phase inverter I38, and the rest-set flip-flop be made up of Sheffer stroke gate I5 and Sheffer stroke gate I6, wherein:

The first input end of the first Sheffer stroke gate I37 connects latch bit line GBL, second input end connects latch bit line GBLN, output terminal connects the input end of the 3rd phase inverter I38, the output terminal of the 3rd phase inverter I38 connects the reset terminal of described rest-set flip-flop, the i.e. first input end of Sheffer stroke gate I6, the output terminal SE of described rest-set flip-flop connects the control end of the second switch pipe N3 in described latch amplifier 100, and the output terminal SE of described rest-set flip-flop is the output terminal of Sheffer stroke gate I5.

Pulses generation electronic circuit 210 comprises: the 4th phase inverter I7, the second Sheffer stroke gate I4 and the 5th phase inverter I3, wherein:

The Enable Pin SA_EN of described sense amplifier, the control end of the first switching tube N2 in described latch-type amplifying circuit is connected to by the 4th phase inverter I7, and the output terminal of the 4th phase inverter I7 is connected to the first input end of described second Sheffer stroke gate I4, second input end of this second Sheffer stroke gate I4 connects the output terminal SE of described rest-set flip-flop, i.e. the output terminal of Sheffer stroke gate I5; The output terminal of the second Sheffer stroke gate I4 connects the input end of described 5th phase inverter I3, the output terminal i.e. output terminal of this pulses generation electronic circuit of the 5th phase inverter I3, is connected to institute-state the 3rd switching tube P3 and the 5th switch controlled end.

And the set end of rest-set flip-flop, namely the first input end of Sheffer stroke gate I5 is connected to the output terminal of described 4th phase inverter.

The course of work of this sense amplifier is as follows:

As Enable Pin SA_EN=Vdd, the 4th phase inverter I7 output low level, rest-set flip-flop exports high level, second switch pipe N3 conducting; Simultaneously, second Sheffer stroke gate I4 exports high level, 5th phase inverter I3 output low level, make the 3rd switching tube P3 and the 5th switching tube P4 conducting, thus make the signal on bit line BL and BLN transfer to SO node (points of common connection of the first PMOS P1 and the first NMOS tube N1) and the SON node (points of common connection of the second PMOS P0 and the second NMOS tube N0) of latch-type amplifying circuit respectively.

When the differential voltage on bit line BL and BLN is enough large, control circuit in static RAM makes described Enable Pin SA_EN=0, 4th phase inverter I7 exports high level, therefore, first switching tube N2 conducting, simultaneously, due to the maintenance Last status of rest-set flip-flop, export high level, second switch pipe N3 conducting, and, two of the second Sheffer stroke gate I4 input ends are made to be high level, output terminal is low level, 5th phase inverter I3 exports high level pulse, therefore, 3rd switching tube P3 and the 5th switching tube P4 turns off, close bit line BL and SO node and the path between bit line BLN and SON node.Now, the first switching tube N2 and second switch pipe N3 conducting simultaneously, latch-type amplifying circuit is started working, and by low level signal amplification to logic level, makes latch bit line GBL or GBLN be pulled down to low level.

Latch bit line GBL or GBLN with a concrete example introduction below and be pulled down to low level process:

When bit line BL is logic high 1, bit line BLN and bit line BL is complementary, for low level small-signal 0, signal now on BLN after latch-type amplifying circuit is amplified to logic level, through the second phase inverter I9 carry out anti-phase after, obtain logic high, thus make the 6th switching tube N7 conducting, due to the source ground of the 6th switching tube, therefore, latch bit line GBLN and be pulled to low level; In like manner, when bit line BL is logic low, latch bit line GBL and be pulled to low level.

Now, when end-of-pulsing decision circuit 220 detects that latching bit line GBL or GBLN is low level, first Sheffer stroke gate I37 exports high level, through the 3rd phase inverter I38 carry out anti-phase after become low level, be supplied to the reset terminal of rest-set flip-flop, then rest-set flip-flop output low level, second switch pipe N3 is turned off, latch-type amplifying circuit quits work, meanwhile, the 3rd switching tube P3 and the 5th switching tube P4 is made to recover conducting, like this, can guarantee just to close latch-type amplifying circuit after latch bit line GBL or GBLN receives drop-down level, make its state that quits work.

Described end-of-pulsing decision circuit, latch after bit line GBL or GBLN receives drop-down level in detection and just close latch-type amplifying circuit, therefore, there will not be the pulse width due to the generation of latch-type pulse-generating circuit inadequate, the level transmissions caused less than on described latch bit line GBL or GBLN or level not can completely be transferred to and latch on bit line GBL or GBLN, thus improve the reliability of sense amplifier.

In Fig. 2, PMOS P5, P8 and P9 are through phase inverter I48, I43, I49, the electric signal utilizing Enable Pin SA_SE to hold carries out precharge for BL and BLN, BL and BLN is charged to high level VDD in advance, wherein, the effect of phase inverter I48, I43, I49 the electric signal that SA_SE holds is carried out time delay form pulse waveform.

Preferably, in above-described embodiment, described 3rd switching tube and the 5th switching tube are PMOS, and the first end of described switching tube be the source electrode of PMOS, the second end is the drain electrode of PMOS, the control end of switching tube is the grid of PMOS; Described first switching tube, described second switch pipe, the 4th switching tube and the 6th switching tube are NMOS tube, and the first end of switching tube be the source electrode of NMOS tube, the second end of switching tube is the drain electrode of NMOS tube, the control end of switching tube is the grid of NMOS tube.

More than describe the work process of sense amplifier in detail, introduce the course of work of the overall latch cicuit be connected with sense amplifier in static RAM below in conjunction with Fig. 3:

Refer to Fig. 3, show the circuit theory schematic diagram of the overall latch cicuit of static RAM, PMOS P10 in figure, P11, P12 is the preliminary filling fulgurite latching bit line GBL and GBLN, electric capacity C2 is the load of latching bit line GBLN, C3 is the load of latching bit line GBL, when latch-type amplifying circuit normally works, P10P11, P12 is in closed condition, now, the drop-down level of GBL or GBLN is latched by the rest-set flip-flop be made up of Sheffer stroke gate I11 and I12, data output end DOUT exports correct logic level, thus, quickly and accurately from storage unit data reading.

Refer to Fig. 4 and Fig. 5, the oscillogram of the sensitive-type amplifier that Fig. 4 provides for the embodiment of the present application, Fig. 5 is the oscillogram of traditional sensitive-type amplifier.

In Fig. 4 and Fig. 5, abscissa representing time, unit is second (S) V, ordinate is the magnitude of voltage unit of pulse signal is volt (V), wherein, (SA_EN) be the voltage waveform of the Enable Pin of sensitive-type amplifier, the voltage waveform of the control end of the second switch pipe N3 that V (SE) is latch-type amplifier, the voltage waveform of the data output end that V (dout) is static RAM, V (SQ) connects the voltage waveform of one end of bit line BL for sensitive-type amplifier, V (SQN) connects the voltage waveform of one end of BLN for sensitive-type amplifier.

Waveform is as shown in Figure 4 known, when latching the load on bit line GBL and GBLN and changing, the change of following load broadens greatly by the width of the pulse waveform corresponding to V (SE), thus the width of the pulse waveform corresponding to V (SQ) is broadened, thus, make the working time of sensitive-type amplifier elongated, signal on bit line correctly can be amplified, finally make the logic level signal on the correct output bit-line of V (dout), the data stored in namely correct reading static RAM.Fig. 4 shows that the amplifier control signal of the static RAM applying the sensitive-type amplifier that the embodiment of the present application provides can change according to the change of load, specifically can also see table 1, between the signal that the static RAM output terminal of sensitive-type amplifier that table 1 provides for application the embodiment of the present application exports and load situation, in table 1, gbl_load is the situation of the load of latching on bit line GBL and GBLN, unit is farad (F), Vdout is the numerical value of the voltage signal that static RAM output terminal exports, and unit is volt (V):

Table 1

gbl_load (F)	Vdout(V)
		3.00E-13	1.2
4.00E-13	1.2
		5.00E-13	1.2
6.00E-13	1.2
		7.00E-13	1.2
8.00E-13	1.2
		9.00E-13	1.2
1.00E-12	1.2

In upper table, when gbl_load is 3.00E-13F, namely when load is 0.3pF, output terminal DOUT holds the voltage Vdout exported to be 1.2V, until the load of latching on bit line GBL is 1.00E-12F, namely during lpF, output terminal DOUT holds the signal exported still effective, output voltage Vdout is 1.2V, shows to utilize the static RAM of this sensitive-type amplifier can work in all loads, namely exports correct logic level.

And the pulse width of V (SQ) waveform in the oscillogram of the traditional sensitive-type amplifier shown in Fig. 5 can not be followed the change of the load on GBL and GBLN and change, cause the output terminal of static RAM can not export correct logic level with the change of load, specifically can also see table 2, table 2 is for the output of the static RAM of the traditional sense amplifier of application is with load situation of change, gbl_load is the situation of the load of latching on bit line GBL and GBLN, unit is farad (F), Vdout is the numerical value of the voltage signal that static RAM output terminal exports, unit is volt (V):

Table 2

gbl_load(F)	vdout(V)
		3.00E-13	1.2
4.00E-13	1.2
		5.00E-13	1.2
6.00E-13	1.2
		7.00E-13	8.79E-02
8.00E-13	3.03E-02
		9.00E-13	1.35E-02
1.00E-12	6.47E-03

As shown in Table 2, when the load on GBL and GBLN is greater than 6.00E-13, namely after 0.6pF, traditional sensitive-type amplifier starts to lose efficacy, the output of also namely applying the static RAM of traditional sensitive-type amplifier was lost efficacy, and under sensitive-type amplifier provided by the invention can be operated in arbitrary load situation.

It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.

The above is only the embodiment of the application; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection domain of the application.

Claims

1. one kind is applied to the sense amplifier of static RAM, comprise: latch-type amplifying circuit, described latch-type amplifying circuit respectively with bit line BL, bit line BLN, hold, latch bit line GBL and latch bit line GBLN and be connected, it is characterized in that, described sense amplifier also comprises:

The pulse-generating circuit be connected with described latch-type amplifying circuit, this pulse-generating circuit comprises: pulses generation electronic circuit and end-of-pulsing decision circuit, wherein:

Two input ends of described end-of-pulsing decision circuit connect described latch bit line GBL respectively and latch bit line GBLN, and output terminal connects the input end of described pulses generation electronic circuit, controls the duty of described pulses generation electronic circuit; Meanwhile, the output terminal of this end-of-pulsing decision circuit connects described latch-type amplifying circuit, controls the duty of latch-type amplifying circuit;

When described end-of-pulsing decision circuit detects the low level signal on described latch bit line GBL or described latch bit line GBLN, export end-of-pulsing control signal, control latch-type amplifying circuit and quit work;

Described latch-type amplifying circuit mainly comprises: the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, wherein:

The first end of described first PMOS connects direct supply, second end of described first PMOS is connected with the first end of described first NMOS tube, the control end of described first PMOS is connected with the control end of described first NMOS tube, and the second end of described first NMOS tube is by the first switching tube of being connected in series and second switch pipe ground connection; The first end of described first switching tube is connected with the second end of the first NMOS tube, the control end of described first switching tube is connected with the output terminal of the 4th phase inverter, second end of described first switching tube is connected with the first end of described second switch pipe, the described control end of second switch pipe is connected with the output terminal of rest-set flip-flop, the second end ground connection of described second switch pipe; Described second PMOS is connected with described second NMOS tube and is formed series arm, and this series arm is connected in parallel on the series arm two ends of described first PMOS and the first NMOS tube formation;

Described first PMOS is connected described bit line BL with the common point of described first NMOS tube by the 3rd switching tube, the described first end of the 3rd switching tube is connected with the second end of the first PMOS, second end of described 3rd switching tube connects described bit line BL, the control end of the 3rd switching tube connects the output terminal of pulses generation electronic circuit, and this common point is connected to latch bit line GBL by the first phase inverter and the 4th switching tube, the input end of described first phase inverter connects described common point, the output terminal of this first phase inverter connects the control end of described 4th switching tube, the first end ground connection of described 4th switching tube, second end connects described latch bit line GBL,

Described second PMOS is connected described bit line BLN with the common point of the second NMOS tube by the 5th switching tube, the first end of described 5th switching tube connects the second end of described second PMOS, second end of the 5th switching tube connects described bit line BLN, the control end of described 5th switching tube connects the output terminal of described pulses generation electronic circuit, and this common point is connected to latch bit line GBLN by the second phase inverter and the 6th switching tube, the input end of described second phase inverter connects described common point, the output terminal of this second phase inverter connects the control end of described 6th switching tube, the first end ground connection of described 6th switching tube, second end connects described latch bit line GBLN,

Described end-of-pulsing decision circuit specifically comprises: the first Sheffer stroke gate, the 3rd phase inverter, rest-set flip-flop, and described pulses generation electronic circuit comprises: the second Sheffer stroke gate and the 5th phase inverter, wherein,

The first input end of the first Sheffer stroke gate is connected with latch bit line GBL, and the second input end is connected with latch bit line GBLN, and output terminal connects the input end of described 3rd phase inverter;

The reset terminal of described rest-set flip-flop connects the output terminal of described 3rd phase inverter, the set end of described rest-set flip-flop connects the output terminal of the 4th phase inverter, the input end of the 4th phase inverter connects the Enable Pin of described sense amplifier, the output terminal of described rest-set flip-flop connects the control end of the second switch pipe in described latch-type amplifying circuit, and the output terminal of this rest-set flip-flop connects the first input end of described second Sheffer stroke gate, the output terminal of this second Sheffer stroke gate connects the input end of described 5th phase inverter, the output terminal of the 5th phase inverter is connected to the control end of described 3rd switching tube and the 5th switching tube, and the second input end of described second Sheffer stroke gate connects the output terminal of described 4th phase inverter,

2. the sense amplifier being applied to static RAM according to claim 1, it is characterized in that, described first switching tube, described second switch pipe, the 4th switching tube and the 6th switching tube are NMOS tube, and first end is drain electrode, second end is source electrode, and control end is grid.

3. the sense amplifier being applied to static RAM according to claim 1, is characterized in that, described 3rd switching tube and the 5th switching tube are PMOS, and first end is drain electrode, the second end is source electrode, and control end is grid.