CN105469822A - Semiconductor memory apparatus, semiconductor system and reading method - Google Patents
Semiconductor memory apparatus, semiconductor system and reading method Download PDFInfo
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Abstract
The present invention relates to a semiconductor memory apparatus, a semiconductor system and a reading method, and provides a flash memory that can effectively protect information with high safety. The flash memory (100) comprises a setting part, a comparison part (300) and a control part (310), wherein when a specific command is inputted into the setting part, the setting part sets specific address information for a non-volatile configuration register (240) and sets specific data in a hidden storage area (112); in a read operation, the comparison part (300) compares inputted address information with the specified address information; and when two pieces of address information are consistent, the specific data set in the storage area (112) is read, and the specific address is erased, and when two pieces of address information are inconsistent, data stored in a memory array is read according to the inputted address information.
Description
Technical field
The invention relates to a kind of with non-(NotAND, NAND) type flash memory (flashmemory) etc. semiconductor memory system, in particular to storage and the reading thereof of the high information of security.
Background technology
NAND flash memory has memory cell array (memorycellarray), and described memory cell array comprises NAND string (string) being connected in series with multiple memory cell (memorycell).Compare or non-(NOTOR, NOR) type flash memory, NAND flash memory can realize the high memory cell array of closeness, is therefore suitable for the jumbo data such as view data or music data and stores.Except this kind of purposes, NAND flash memory is also used as the storer providing start-up code (bootcode) when starting electronic equipment or system (system).Start-up code is the data of the operating system (operatingsystem) of electronic equipment for starting main frame (host) side or system etc.
The System's composition that can export the existing semiconductor memory of start-up code to host computer system (hostsystem) is represented in Figure 1A, Figure 1B.As shown in Figure 1B, semiconductor memory 10 is connected to main process equipment (hostdevice) 30 via bus-bar (bus) etc.As shown in Figure 1A, semiconductor memory 10 has input and output pin (pin) 12, Memory Controller (controller) 14 and the memory section 16 of carrying out data input and output between main process equipment 30.Memory Controller 14 possesses: host interface (hostinterface) 20, via input and output pin 12 and carry out data transmission between main process equipment 30; Memory interface 22, and carry out data transmission between memory section 16; Microprocessing unit (Micro-ProcessingUnit, MPU) 24, control data transmission etc.; And ROM (read-only memory) (ReadOnlyMemory, ROM) 26, random access memory (RandomAccessMemory, RAM) 28, storage program or data.Memory section 16 such as comprises the chip of two NAND flash memories.In addition, as shown in Figure 1B, memory section 16 comprises the physics accessing zone 16A that can access with physical address (address) and can with the logic accessing zone 16B of logic address access, in the start-up code of physics accessing zone 16A storage host equipment 30.Start-up code is the data of operating system for starting main process equipment 30 etc.Form according to this kind, when main process equipment 30 only supports physics access mode, start-up code (patent documentation 1) can be provided to main process equipment 30.
Existing technical literature
Patent documentation 1: Japanese Patent Laid-Open 2009-175877 publication
Store in memory-aided host computer system at use NAND flash memory as start-up code, during startup or when being energized, start-up code can be read from flash memory, start up system.In addition, except start-up code, also have following application: prestore the secret important information that security is high, read this information and for Systematical control.As an example, there is following application: prestore the distinctive security code of system (securitycode) or decruption key (decryptionkey) at flash memory, if cannot read this security code, accumulator system just cannot normally be run.More particularly, by contrast security code, and allow to start and be stored in the operating system of flash memory or software etc.In addition, as another example, there is following application: personal information high for privacy be pre-stored within flash memory, and this personal information is used for specific program.
But, prestore the information that this kind of security is high in a flash memory, and when operationally reading this information, there are the following problems.If repeatedly read as security code or this important information of privacy, the risk of these information leakage just can increase.Such as, read without authorization by nonspecific system or malicious user or copy sometimes, can say that protection may not be abundant thus.On the other hand, being only read when starting although can be set to as start-up code, can utilizing the time restriction of information just can be excessive thus.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor memory system possessing the novel structure of the information that can effectively protect security high.
Semiconductor memory system of the present invention comprises: nand type memory array; Input part, can Input Address information and data; Reading part, based on the address information inputted from described input part, reads the data being stored in described memory array; Configuration part, when have input particular command from described input part, to the address information of order memory area setting input as particular address information, and the data that the setting of territory, data memory area inputs from described input part are as particular data; And control part, control described reading part; Described control part compares the address information of input and described particular address information when read operation, when two-address information is consistent, read the particular data being set in described data storage areas, and wipe described particular address information or establish described particular address information invalid, when two-address information is inconsistent, read according to the address information of input the data being stored in described memory array.
Be preferably, described configuration part comprises non-volatile address storage area and volatibility order memory area, described configuration part is responded power supply and is connected, the particular address information being set in non-volatile address storage area is made to be held in volatibility order memory area, described control part is when the address information inputted is consistent with described particular address information, and erasing is held in the particular address information of described volatibility order memory area.Be preferably, described particular address information is held concurrently the address of the address space for selecting described memory array.Be preferably, described data storage areas is set in the different region of memory array available from user.Be preferably, described order memory area is configuration working storage (configurationregister).Be preferably, described control part comprises count section, the number of times that the address information of described count section to input is consistent with described particular address information counts, and described control part is when the count results of described count section reaches the value predetermined, and wipes described particular address information.
The read method of particular data of the present invention uses in the semiconductor system comprising semiconductor memory system and main process equipment, particular command is exported to semiconductor memory system, to the order memory area setting particular address information of semiconductor memory system, and territory, data memory area setting particular data, when read operation, the address information relatively inputted and described particular address information, when two-address information is consistent, read the particular data being set in described data storage areas, and wipe described particular address information or establish described particular address information invalid, when two-address information is inconsistent, the data being stored in described memory array are read according to the address information of input.
Be preferably, described read method is also after connection system power supply, make the particular address information being set in non-volatile address storage area be held in volatibility order memory area, when described two-address information is consistent, wipe the particular address information of described volatibility order memory area.Be preferably, after reclosing system power supply, make the particular address information being set in non-volatile address storage area be held in volatibility order memory area.Be preferably, read method also counts the number of times that the address information of input is consistent with described particular address information, when count results reaches the value predetermined, wipes described particular address information.
According to the present invention, when the address information inputted is consistent with particular address information, read particular data, and wipe particular address information or establish particular address information invalid, therefore, the reading of particular data after this can be limited.Thus, the security of particular data can be improved.
Accompanying drawing explanation
Figure 1A, Figure 1B are the figure of the formation of the semiconducter memory system representing existing output start-up code.
Fig. 2 is the figure of a configuration example of the flash memory representing embodiments of the invention.
Fig. 3 is the circuit diagram of the formation of the NAND string representing embodiments of the invention.
Fig. 4 is the skeleton diagram of the system of the flash memory comprising the present embodiment.
Fig. 5 is the process flow diagram of the initial setting operation of a read mode (onetimereadmode) of the flash memory that the present embodiment is described.
Fig. 6 is the figure of the example representing the non-volatile of flash memory and volatibility configuration working storage.
The figure of the write of routine data when Fig. 7 is the initial setting of the flash memory that the present embodiment is described.
The figure of functional formation when Fig. 8 is once reading of the flash memory representing control the present embodiment.
Fig. 9 is the process flow diagram of a read operation of the flash memory that the present embodiment is described.
Figure 10 A is the figure of the operation represented volatibility configuration working storage setting particular address.
Figure 10 B is the figure of operation when representing that the address of particular address and input is inconsistent.
Figure 10 C is the figure of operation when representing that particular address is consistent with the address of input.
Figure 10 D is the figure representing the reading example after once reading.
The figure of functional formation when Figure 11 is once reading of the flash memory representing the control second embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10: semiconductor memory
12: input and output pin
14,230: Memory Controller
16: memory section
16A: physics accessing zone
16B: logic accessing zone
20: host interface
22: memory interface
24: microprocessing unit
26: ROM (read-only memory)
28: random access memory
30,210: main process equipment
100: flash memory
110: memory array
112: storage area
120: inputoutput buffer
130: address register
140: Data buffer
150: controller
160: word line selection circuit
170: page buffer/sensing circuit
180: column select circuit
190: internal voltage generating circuit
200: system
220: memory module
240: non-volatile configuration working storage
242: order memory area
244: marked region
246: region
250: volatibility configuration working storage
300: comparing section
310: control part
320: counter
Ax: row address information
Ay: column address information
BLK (0) ~ BLK (m): block
C1, C2, C3: control signal
GBL0 ~ GBLn: bit line
I/O: outside input and output terminal
MC0 ~ MC31: memory cell
NU: string location
PA00 ~ PAXX: page address
PA_N: specific webpage address
S1, S2, S3: control
S100 ~ S106, S200 ~ S226: step
SGD, SGS: select gate line
SL: common source line
TD, TS: select transistor
Vers: erasing voltage
Vpass: forward voltage
Vprog: programming voltage
Vread: read voltage
WL: wordline
Embodiment
Below, with reference to accompanying drawing, describe embodiments of the present invention in detail.Fig. 2 represents the formation of the flash memory of embodiments of the invention.But the formation of flash memory shown here is for illustrating, and non-essential this kind that be defined in of the present invention is formed.
As shown in Figure 2, the flash memory 100 of the present embodiment is configured to comprise: memory array 110, is formed and is arranged as rectangular multiple memory cells; Inputoutput buffer (buffer) 120, is connected to outside input and output terminal I/O and keeps inputoutput data; Address register (addressregister) 130, receives the address date from inputoutput buffer 120; Data buffer 140, keeps the data of input and output; Controller 150, based on from the order data of inputoutput buffer 120 and external control signal (not shown chip is energized (chipenable) or address door bolt energizes (addresslatchenable) etc.), supply controls control signal C1, C2, the C3 etc. in each portion; Wordline (wordline) selection circuit 160, decodes (decode) to the row address information Ax from address register 130, and carries out block selection and wordline selection etc. based on decoded result; Page buffer (pagebuffer)/sensing circuit 170, keeps the data that read from the page selected by word line selection circuit 160 or keeps to by the data of page write selected; Column select circuit 180, decodes to the column address information Ay from address register 130, and selects the column data in page buffer 170 based on this decoded result; And internal voltage generating circuit 190, produce and be used for carrying out the necessary voltage such as digital independent, sequencing and erasing (programming voltage Vprog, forward voltage Vpass, reading voltage Vread, erasing voltage Vers etc.).
Memory array 110 have be configured at column direction multiple block BLK (0), BLK (1) ..., BLK (m).At configuration page face, an end impact damper/sensing circuit 170 of block.But page buffer/sensing circuit 170 also can be configured at the other end of block or the end of both sides.
As shown in Figure 3, form multiple NAND string location NU in a memory block, described NAND string location NU is connected by multiple memory cell to be formed by connecting, and is arranged with n+1 string location NU in a block in the row direction.String location NU comprises: multiple memory cell MCi of being connected in series (i=0,1,31); Select transistor (transistor) TD, be connected to the drain side of the memory cell MC31 as an end; And select transistor TS, be connected to the source side of the memory cell MC0 as the other end; And select the drain electrode of transistor TD to be connected to corresponding bit line (bitline) GBL, select the source electrode of transistor TS to be connected to common source line SL.
The control gate of memory cell MCi is connected to wordline WLi, selects the grid of transistor TD, TS to be connected to selection gate line SGD, the SGS parallel with wordline WL.Word line selection circuit 160 is when selecting block based on row address Ax, selection gate line SGS, SGD via this block optionally drive and select transistor TD, TS.
Typical case, memory cell has metal-oxide semiconductor (MOS) (Metal-Oxide-Semiconductor, MOS)) structure, described MOS structure comprises: as the source/drain of N-type diffusion zone, is formed in P well (well); Tunneling oxide film, is formed on the passage of source/drain interpolar; Floating grid (charge accumulation layer), is formed on tunneling oxide film; And control gate, be formed on floating grid across dielectric film.When the non-accumulated charge of floating grid, when namely data " 1 " are written into, threshold value is in negative state, and memory cell is for often to open (normallyon).When floating grid accumulation has electronics, when namely data " 0 " are written into, threshold shift is just, memory cell is normal pass (normallyoff).But memory cell is not limited to storage cell (bit), also can store multidigit.
Table 1 is the table of the example representing bias voltage (bias) voltage applied when each operation of flash memory.In read operation, pairs of bit line applies certain positive voltage, certain voltage (such as 0V) is applied to selected wordline, forward voltage Vpass (such as 4.5V) is applied to non-selection wordline, positive voltage (such as 4.5V) is applied to selection gate line SGD, SGS, make bit line selection transistor TD, source electrode line select transistor TS to connect, 0V is applied to common source line.In sequencing (write) operation, high-tension programming voltage Vprog (15V ~ 20V) is applied to selected wordline, intermediate potential (such as 10V) is applied to non-selected wordline, bit line selection transistor TD is connected, make source electrode line select transistor TS to disconnect, supply the corresponding current potential of data with " 0 " or " 1 " to bit line GBL.In erase operation, 0V is applied to the wordline selected by block, high voltage (such as 20V) is applied to P well, the electronics of floating grid is drawn to substrate, by this, in units of block, carrys out obliterated data.
[table 1]
Fig. 4 is the figure of an example of the system representing the flash memory comprising the present embodiment.The system 200 of the present embodiment comprises main process equipment 210 and is connected to the memory module 220 of this main process equipment 210.Main process equipment 210 is not particularly limited, and is the electronic installations such as computer, digital camera, printer or the chip being equipped on chipset.Memory module 220 comprises the Memory Controller 230 and flash memory 100 with the function identical with the Memory Controller 14 shown in Figure 1A, Figure 1B.Data transmission etc. between Memory Controller 230 main control system equipment 210 and flash memory 100.
The flash memory of the present embodiment, when the information that storage security is high, in order to prevent this information leakage, possesses a read mode.If set a read mode, the information being set in a reading area after switching on power just can only be read once.Before this state continues to and switches on power next time, namely when again switching on power, the information being set in a reading area just can only be read once again.Thus, prevent in the operating process of system, the high information of security is repeatedly read.
In order to make a read mode of flash memory 100 effective, initial setting is carried out to flash memory 100.Initial setting utilizes the prespecified particular command different from common order, sets specific address information to order memory area, and the confidential information high to a reading area setting security.In preference, only when specific address information is consistent, the confidential information being set in a reading area just can be read once.
Fig. 5 is the process flow diagram for illustration of initial setting.First, the particular command (S100) for carrying out initial setting is sent from main process equipment 210 to memory module 220.Particular command is the order different from common sequencing initiation command (80h, 81h, 85h), preferably only has the hidden command that specific user or system can be known.If the particular command that from host equipment 210 sends is received by the controller 150 of flash memory 100, controller 150 just starts the sequence for initial setting based on particular command.
Then, from main process equipment 210 to flash memory 100, input is used for the address (S102) of once reading.In this, in order to be distinguished with common address, the address inputted when inputting particular command is called particular address.Particular address can comprise row address (page address) and column address, but also can be row address (page address) when selection one page entirety.If be transfused to particular address, particular address is just stored in non-volatile address storage area (S104) by controller 150.Be preferably, non-volatile address storage area is non-volatile configuration working storage (ConfigurationRegister, CR).
As shown in Figure 6, the flash memory 100 of the present embodiment has non-volatile configuration working storage 240 and volatibility configuration working storage 250.Usually, non-volatile configuration working storage 240, volatibility configuration working storage 250 cannot be undertaken reading or writing by user when operating, but can be undertaken reading or writing by certain AD HOC of execution or order.
Non-volatile configuration working storage 240 comprises the order memory area 242 of storage particular address and represents mark (flag) region 244 having stored particular address in order memory area 242.Non-volatile configuration working storage 240 also comprises the region 246 of the operation information of setting flash memory 100.Region 246 stores necessary information when such as starting flash memory.Non-volatile configuration working storage 240 can comprise such as NOR type or NAND memory element, Electrical Erasable programmble read only memory PROM (ElectricallyErasableProgrammableRead-OnlyMemory, EEPROM), magnetic random access memory (MagneticRandomAccessMemory, MRAM), the memory element etc. such as variable resistance type random access memory (ResistiveRandomAccessMemory, ReRAM).
Volatibility configuration working storage 250 can keep the information such as the particular address read from non-volatile configuration working storage 240 after system start-up.Volatibility configuration working storage 250 can comprise such as static RAM (StaticRandomAccessMemory, SRAM), the memory element such as dynamic RAM (DynamicRandomAccessMemory, DRAM).
It should be noted, particular address represents the spendable address space of user in memory array 110 herein, and is become possible identifying information for making once to read.In addition, when being transfused to particular address in initial setting, word line selection circuit 160 is not the page of selection memory array 110, but selects the page of the storage area hidden from memory array 110.The storage area hidden is the storage area of non-volatile programmable, such as, be set in the region that available memory array 110 is separated with user.
The concrete example of initial setting is represented in Fig. 7.After input particular command, then just can input " PA_N " as specific webpage address.In addition, particular address only comprises page address.If specific webpage address PA_N is input to address register 130, under control of the controller 150, specific webpage address PA_N just can be stored in the order memory area 242 of non-volatile configuration working storage 240.
Specific webpage address PA_N is the page of the available address space of user in memory array 110, but word line selection circuit 160 is with the specific webpage address PA_N of not selection memory array 110, but the mode of the storage area 112 hidden from memory array 110 is selected to operate.Although the storage area 112 hidden also can physically be formed in memory array 110, it is that user cannot the unserviceable data storage areas of assigned address, i.e. user.Hide storage area 112 be such as formed in the same manner as memory array 110 comprise NAND string location block in, when being transfused to particular command, can have been selected by word line selection circuit 160.In addition, the storage area 112 hidden also can comprise the memory element beyond NAND string location.Such as, storage area 112 also can comprise the memory elements such as MRAM, ReRAM, EEPROM, NOR.In this case, to the non-essential use word line selection circuit 160 of the access of storage area 112, other special selection circuits can also be used.
Again be back to Fig. 5, then the routine data (S106) of input for once reading.This routine data is the high confidential information of security, such as, be security code, decruption key, privacy information etc.The routine data of input is supplied to page buffer/sensing circuit 170 via Data buffer 140, as shown in Figure 7, is programmed the page in the storage area 112 hidden.When the size of routine data is less than a page, can only to the bit line supply routine data selected by column select circuit 180 according to particular address.On the contrary, when the size of routine data is greater than a page, such as, specific webpage address PA_N can be specified to be header page, to from header page continuous print page write-in program data.Like this, the initial setting being used for once reading is terminated.
Then, a read operation of the flash memory of the present embodiment is described.Controller 150 comprises program for controlling a read mode or state machine.Fig. 8 is the block diagram of functional formation when representing that controller 150 controls a read mode.Comparing section 300 possesses: comparing section 300, when the page carrying out flash memory 100 reads, compares the address being input to address register 130 and the particular address being held in volatibility configuration working storage 250; And control part 310, the comparative result in portion 300 controls each portion based on the comparison.
As described below, control part 310 is when the energising sequence of flash memory 100, perform control S1, control S2 and control S3 etc., described control S1 transfers to volatibility configuration working storage 250 for making the particular address being stored in non-volatile configuration working storage 240 and keeps this particular address, described control S2 is used for when showing that two-address is consistent by comparing section 300, erasing is held in the particular address of volatibility configuration working storage 250, described control S3, when showing that two-address is consistent by comparing section 300, allows word line selection circuit 160 select the page of the storage area 112 hidden.
Then, with reference to the process flow diagram of Fig. 9, a read operation of the present embodiment is illustrated in greater detail.This example is, when initial setting, sets specific webpage address, and do not set column address to the order memory area 242 of non-volatile configuration working storage 240.
If the system shown in Fig. 4 200 starts, switch on power (S200) to flash memory 100, controller 150 just starts the program or state machine that sort for being energized.First, controller 150 accesses non-volatile configuration working storage 240, checks the mark being set in marked region 244, judges whether initial setting carries out (S202).If do not carry out initial setting, controller 150 just can not move to a read mode, but carries out the operation (S204) as in the past.
On the other hand, when being set with mark, when namely initial setting completes, controller 150 goes to a read mode, the control of once reading (S206).If go to a read mode, controller 150 just owing to storing specific webpage address in non-volatile configuration working storage 240, and performs internal read command " 00h " (S208).By performing " 00h ", reading specific webpage address (S210) from the order memory area 242 of non-volatile configuration working storage 240, and specific webpage address is held in volatibility configuration working storage 250 (S212).Figure 10 A represents situation specific webpage address PA_N being set in volatibility configuration working storage 250.Process before step S212 is undertaken by energising sequence.
Afterwards, main process equipment 210 pairs of flash memories 100 carry out read operation (S214).Read operation is as in the past, and flash memory 100 receives reading order and address from main process equipment 210.Respond read operation, controller 150 performs internal read command " 30h " (S216).By performing this order, the address inputing to address register 130 is read.
Then, comparing section 300 compares the specific webpage address being held in volatibility configuration working storage 250 and the page address of reading from address register 130, judges two-address whether consistent (S218).Suppose that address is inconsistent, just implement the common page and read (S220).That is, selected the page address be transfused to by word line selection circuit 160, transmit by the data of the page selected to page buffer/sensing circuit 170, and export to main process equipment 210 via inputoutput buffer 120.Figure 10 B represents the example of input PA01 as page address.Because page address PA01 and specific webpage address PA_N is inconsistent, therefore, word line selection circuit 160 selects page address PA01, reads the data of page address PA01.
On the other hand, when judging that the page address of input is consistent with particular address by comparing section 300 (S218), controller 150 (control part 300) makes word line selection circuit 160 select the page of the storage area 112 hidden, and is stored in the data (S222) of storage area 112 to page buffer/sensing circuit 170 transmission.Then, control part 300 erasing is held in the specific webpage address of volatibility configuration working storage 250 or makes its invalid (S224).Afterwards, the data (S226) being stored in the page of storage area 112 are read from inputoutput buffer 120.
Figure 10 C represents the example of input specific webpage address PA_N as page address.Because the page address PA_N of input is consistent with specific webpage address PA_N, word line selection circuit 160 selects the page of the storage area 112 hidden, and is stored in the data of this page to page buffer/sensing circuit 170 transmission.Now, should notice that the specific webpage address PA_N of memory array 110 is not selected.
Like this, if the page address be transfused to is consistent with specific webpage address, just can read the data of the page being stored in hiding storage area 112, but this reading is restricted to for once.Namely, if the page address consistent with specific webpage address is transfused to once, just can wipe the specific webpage address that is held in volatibility configuration working storage 250 or make it invalid, therefore, even if the page address consistent with specific webpage address is transfused to again, comparing section 300 also can judge that two-address is inconsistent, and can not judge that two-address is consistent.So word line selection circuit 160 can not select the page of the storage area 112 hidden.Figure 10 D represents after once reading, the example when page address consistent with particular address is transfused to.When page address PA_N is transfused to, because volatibility configuration working storage 250 does not keep in fact specific webpage address, therefore comparing section 300 judges that two-address is inconsistent.Therefore, word line selection circuit 160 page of non-selection hiding storage area 112, but the specific webpage address PA_N of selection memory array 110, read the data being stored in this specific webpage address PA_N.
According to the present embodiment, when the very high information of the confidentialities such as security code, decruption key or private data in flash memory storage, the reading times of information high for this kind of confidentiality is restricted to once, important information therefore can be prevented to be read easily or to be replicated.In addition, by using the specific webpage address PA_N of virtual data (dummydata) sequencing in the memory array 110 as user area, system, when virtual data is read because of malice access or illegal access, can utilize virtual data to follow the trail of illegal access.
In the example shown in described Fig. 9, what represent is set mark to non-volatile configuration working storage 240, go to the example (S202, S206) of a read mode when being set with mark, but this kind of flag settings or utilize mark judgement and nonessential.In another preferred embodiment, flash memory 100 when power supply is connected, can have nothing to do in flag settings and optionally performs once reading or common operation.Do not perform once read time, when namely initial setting not being carried out to non-volatile configuration working storage 240, the address information (being the data of F) of erase status, for presetting (default), is therefore transmitted in the order memory area 242 of non-volatile configuration working storage 240 to volatibility configuration working storage 250.When the page address information of this erase status and at user option address information inconsistent, must common read operation be carried out.On the other hand, if set particular address to order memory area 242, by with described identical operation, only just read the data of hiding storage area when particular address is consistent with the address that user selects.
Then, the second embodiment of the present invention is described.What described embodiment represented is the example once read, and the second embodiment can carry out limited repeatedly reading.Figure 11 is the figure of the functional formation representing the second embodiment.In a second embodiment, add counter 320, the consistent number of times of this counter 320 to the two-address utilizing comparing section 300 to judge counts.Counter 320, when the consistent number of times of two-address reaches the times N predetermined, notifies this situation to control part 300.Control part 300 responds this notice, and erasing is held in the specific webpage address of volatibility configuration working storage 250 or makes it invalid.Thus, the data being stored in hiding storage area 112 can only be read with limited times N.
Although described the preferred embodiment of the present invention in detail, the present invention has been not limited to specific embodiment, carries out various distortion, change in the main scope of the present invention that can record in the claims.
In the described embodiment, if the specific webpage address of initial setting is user area, just can be set in any place, therefore can expand the degree of freedom of address maps (mapping).In addition, what described embodiment represented is example specific webpage address being stored in configuration working storage, but specific webpage address is non-essential is stored in configuration working storage, also can be stored in other storage areas.And, the internal read command that described embodiment performs as flash memory exemplified with " 00h ", " 30h ", but be not limited thereto, as long as order or the control signal of the page address being set in working storage can be read.
And, in the described embodiment, exemplified with a specific webpage address, but be not limited thereto, also can use multiple specific webpage address, to storage area 112 programming data corresponding with multiple specific webpage address.
Claims (11)
1. a semiconductor memory system, it comprises:
With nand-type memory array;
Input part, can Input Address information and data;
Reading part, based on the address information inputted from described input part, reads and is stored in data that are described and nand-type memory array;
Configuration part, when have input particular command from described input part, to the address information of order memory area setting input as particular address information, and the data that the setting of territory, data memory area inputs from described input part are as particular data; And
Control part, controls described reading part; And
Described control part compares the address information of input and described particular address information when read operation, when two-address information is consistent, read the described particular data being set in described data storage areas, and wipe described particular address information or establish described particular address information invalid, when described two-address information is inconsistent, reads according to the address information of input and be stored in data that are described and nand-type memory array.
2. semiconductor memory system as claimed in claim 1, wherein said configuration part comprises non-volatile address storage area and volatibility order memory area, described configuration part is responded power supply and is connected, the described particular address information being set in described non-volatile address storage area is made to be held in described volatibility order memory area, described control part is when the address information inputted is consistent with described particular address information, and erasing is held in the described particular address information of described volatibility order memory area.
3. semiconductor memory system as claimed in claim 1 or 2, wherein said particular address information is held concurrently as selecting address that the is described and address space of nand-type memory array.
4. semiconductor memory system as claimed in claim 1 or 2, wherein said data storage areas is set in the different region of memory array available from user.
5. semiconductor memory system as claimed in claim 1 or 2, wherein said order memory area is configuration working storage.
6. semiconductor memory system as claimed in claim 1 or 2, wherein said control part comprises count section, the number of times that the address information of described count section to input is consistent with described particular address information counts, described control part, when the count results of described count section reaches the value predetermined, wipes described particular address information.
7. a semiconductor system, the main process equipment comprising semiconductor memory system as claimed in claim 1 or 2 and be connected with described semiconductor memory system, and
Described main process equipment exports described particular address information and described particular data to described semiconductor memory system.
8. a read method, for reading particular data in the system comprising semiconductor memory system and main process equipment, and
Export particular command to described semiconductor memory system, to the order memory area setting particular address information of described semiconductor memory system, and territory, data memory area sets described particular data,
When read operation, the address information relatively inputted and described particular address information, when two-address information is consistent, read the particular data being set in described data storage areas, and wipe described particular address information or establish described particular address information invalid, when described two-address information is inconsistent, read according to the address information of input the data being stored in memory array.
9. read method as claimed in claim 8, wherein said read method is also after connection system power supply, the particular address information being set in non-volatile address storage area is made to be held in volatibility order memory area, when described two-address information is consistent, wipe the described particular address information of described volatibility order memory area.
10. read method as claimed in claim 8 or 9, wherein after reclosing system power supply, is held in described volatibility order memory area by the described particular address information being set in described non-volatile address storage area.
11. read methods as claimed in claim 8 or 9, wherein said read method also counts the number of times that the address information of input is consistent with described particular address information, when count results reaches the value predetermined, wipes described particular address information.
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