CN105469822B - Semiconductor memory system, semiconductor system and read method - Google Patents
Semiconductor memory system, semiconductor system and read method Download PDFInfo
- Publication number
- CN105469822B CN105469822B CN201410464625.3A CN201410464625A CN105469822B CN 105469822 B CN105469822 B CN 105469822B CN 201410464625 A CN201410464625 A CN 201410464625A CN 105469822 B CN105469822 B CN 105469822B
- Authority
- CN
- China
- Prior art keywords
- address information
- address
- data
- read
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Read Only Memory (AREA)
Abstract
The present invention relates to semiconductor memory system, semiconductor system and read methods, provide a kind of flash memory that can be effectively protected highly-safe information.Flash memory (100) includes configuration part, and the configuration part sets particular address information when being entered specific command, to non-volatile configuration buffer (240), and sets specific data in hiding storage region (112).Flash memory (100) further include: comparing section (300) compares the address information and particular address information of input in read operation；And control unit (310), when two-address information is consistent, the specific data for being set in storage region (112) is read, and wipe particular address, when two-address information is inconsistent, the data for being stored in memory array are read according to the address information of input.
Description
Technical field
The invention relates to a kind of semiconductor storages such as and non-(Not AND, NAND) type flash memory (flash memory)
Device device, in particular to the storage and its reading of highly-safe information.
Background technique
NAND-type flash memory has memory cell array (memory cell array), the memory cell array packet
Containing the NAND string (string) for being connected in series with multiple memory cells (memory cell).It compares or non-(NOT OR, NOR)
Type flash memory, NAND-type flash memory may be implemented the high memory cell array of closeness, be consequently adapted to image data or music data
The data storage of equal large capacities.In addition to such purposes, NAND-type flash memory also serves as starting electronic equipment or system (system)
When provide starting code (boot code) memory.Starting code be electronic equipment for starting the side host (host) or
The data of the operating system (operating system) of system etc..
Indicate that the existing semiconductor that starting code can be exported to host system (host system) is deposited in Figure 1A, Figure 1B
The system of reservoir is constituted.As shown in Figure 1B, semiconductor memory 10 is connected to host equipment (host via busbar connector (bus) etc.
device)30.As shown in Figure 1A, semiconductor memory 10 has the input that data input and output are carried out between host equipment 30
Output connecting pin (pin) 12, Memory Controller (controller) 14 and memory portion 16.Memory Controller 14 has: main
Machine interface (host interface) 20, carries out data transmission between host equipment 30 via input and output pin 12；It deposits
Carry out data transmission between memory interface 22, with memory portion 16；Microprocessing unit (Micro-Processing Unit, MPU)
24, control data transmission etc.；And 26, random access memory (Random read-only memory (Read Only Memory, ROM)
Access Memory, RAM) 28, store program or data.Chip of the memory portion 16 for example comprising two NAND-type flash memories.Separately
Outside, as shown in Figure 1B, memory portion 16 include can be with physical address (address) physics accessing zone 16A accessed and can be with
The logic accessing zone 16B of logic address access, in the starting code of physics accessing zone 16A storage host equipment 30.Starting
Code is the data for starting operating system of host equipment 30 etc..According to such composition, object is only supported in host equipment 30
In the case where managing access mode, starting code (patent document 1) can be provided to host equipment 30.
Existing technical literature
Patent document 1: Japanese Patent Laid-Open 2009-175877 bulletin
NAND-type flash memory is being used to store in memory-aided host system as starting code, when starting or the when of energization can
To read starting code, activation system from flash memory.In addition, there are also following applications: safety is stored in advance in addition to starting code
High secret important information reads the information and controls for system.As an example, there is following application: being stored in advance in flash memory
The distinctive safety code of system (security code) or decruption key (decryption key), if the safety can not be read
Code, storage system are just unable to operate normally.More specifically, by compareing safety code, and allow to start and be stored in flash memory
Operating system or software etc..In addition, having following application as another example: the high personal information of privacy is pre-stored within sudden strain of a muscle
In depositing, and the personal information is used for specific program.
However, such highly-safe information is stored in advance in a flash memory, and in the case where reading the information at runtime,
There are the following problems.If the risk of these information leakages will as safety code or this important information of privacy are read several times
Increase.For example, being read or being replicated without authorization by nonspecific system or malicious user sometimes, thus it may be said that protection may not
Sufficiently.On the other hand, it is only read on startup as starting code although can be set to, consequently letter can be utilized
The time restriction of breath will be excessive.
Summary of the invention
The purpose of the present invention is to provide a kind of novel structures for having and being effectively protected highly-safe information
Semiconductor memory system.
Semiconductor memory system of the invention includes: NAND type memory array；Input unit, can be with input address information
And data；Reading part reads the data for being stored in the memory array based on the address information inputted from the input unit；
Configuration part is used as the address information of order memory area setting input special when having input specific command from the input unit
Determine address information, and the data that the setting of data memory area domain is inputted from the input unit are as specific data；And control unit,
Control the reading part；The control unit compares the address information and the particular address information of input in read operation, when
When two-address information is consistent, the specific data for being set in the data storage areas is read, and wipe the particular address information
Or to set the particular address information invalid, when two-address information is inconsistent, is stored in institute according to the address information reading of input
State the data of memory array.
Preferably, the configuration part includes non-volatile address storage region and volatibility order memory area, described to set
Determine portion and respond power supply connection, so that the particular address information for being set in non-volatile address storage region is held in volatibility address and deposit
Storage area domain, when the address information of input is consistent with the particular address information, erasing is held in described volatile the control unit
The particular address information of property order memory area.Preferably, it is that can select the memory array that the particular address information is simultaneous
The address of the address space of column.Preferably, the data storage areas is set in different from the available memory array of user
Region.Preferably, the order memory area is configuration buffer (configuration register).Preferably, institute
Stating control unit includes count section, and the count section carries out the address information of input and the consistent number of the particular address information
It counts, and the control unit wipes the particular address letter when the count results of the count section reach pre-determined value
Breath.
The read method of specific data of the invention is in the semiconductor comprising semiconductor memory system and host equipment
It is used in system, exports specific command to semiconductor memory system, the order memory area of semiconductor memory system is set
Determine particular address information, and data memory area domain sets specific data, in read operation, compare the address information of input with
The particular address information reads the specific data for being set in the data storage areas, and wipe when two-address information is consistent
Except the particular address information or to set the particular address information invalid, when two-address information is inconsistent, according to the ground of input
Location information reads the data for being stored in the memory array.
Preferably, the read method makes to be set in non-volatile address storage region also after connecting system power supply
Particular address information is held in volatibility order memory area, when the two-address information is consistent, with wiping the volatibility
The particular address information of location storage region.Preferably, after reclosing system power supply, make to be set in non-volatile address memory block
The particular address information in domain is held in volatibility order memory area.Preferably, read method also to the address information of input with
The consistent number of particular address information is counted, and when count results reach pre-determined value, is wiped described specific
Address information.
According to the present invention, when the address information of input is consistent with particular address information, specific data is read, and is wiped special
Determine address information or to set particular address information invalid, therefore, the reading of specific data hereafter can be limited.Thus, it is possible to improve
The safety of specific data.
Detailed description of the invention
Figure 1A, Figure 1B are the figures for indicating the composition of semiconducter memory system of existing output starting code.
Fig. 2 is the figure for indicating a configuration example of flash memory of the embodiment of the present invention.
Fig. 3 is the circuit diagram for indicating the composition of NAND string of the embodiment of the present invention.
Fig. 4 is the skeleton diagram of the system of the flash memory comprising the present embodiment.
Fig. 5 is the initial setting behaviour for illustrating a read mode (one time read mode) for the flash memory of the present embodiment
The flow chart of work.
Fig. 6 is the figure for indicating non-volatile and volatibility configuration buffer an example of flash memory.
Fig. 7 is the figure of the write-in of program data when illustrating the initial setting of the flash memory of the present embodiment.
Fig. 8 is the functional figure constituted when indicating the primary reading of the flash memory of control the present embodiment.
Fig. 9 is the flow chart for illustrating a read operation of flash memory of the present embodiment.
Figure 10 A is the figure for indicating to set volatibility configuration buffer the operation of particular address.
Figure 10 B is the figure for indicating the operation in the case that the address of particular address and input is inconsistent.
Figure 10 C is the figure for indicating particular address and the operation under the address unanimous circumstances of input.
Figure 10 D is the figure for indicating the reading example after once reading.
Figure 11 is the functional figure constituted when indicating the primary reading of the flash memory of the control second embodiment of the present invention.
Wherein, the reference numerals are as follows:
10: semiconductor memory
12: input and output pin
14,230: Memory Controller
16: memory portion
16A: physics accessing zone
16B: logic accessing zone
20: host interface
22: memory interface
24: microprocessing unit
26: read-only memory
28: random access memory
30,210: host equipment
100: flash memory
110: memory array
112: storage region
120: inputoutput buffer
130: address register
140: Data buffer
150: controller
160: word line selection circuit
170: page buffer/sensing circuit
180: column select circuit
190: internal voltage generating circuit
200: system
220: memory module
240: non-volatile configuration buffer
242: order memory area
244: marked region
246: region
250: volatibility configuration buffer
300: comparing section
310: control unit
320: counter
Ax: row address information
Ay: column address information
BLK (0)~BLK (m): block
C1, C2, C3: control signal
GBL0~GBLn: bit line
I/O: external input output terminal
MC0~MC31: memory cell
NU: string location
PA00~PAXX: page address
PA_N: specific webpage address
S1, S2, S3: control
S100~S106, S200~S226: step
SGD, SGS: selection grid polar curve
SL: common source line
TD, TS: selection transistor
Vers: erasing voltage
Vpass: conducting voltage
Vprog: programming voltage
Vread: voltage is read
WL: wordline
Specific embodiment
In the following, referring to attached drawing, the embodiment that the present invention will be described in detail.Fig. 2 indicates the flash memory of the embodiment of the present invention
It constitutes.But the composition of flash memory shown here is to illustrate, and the present invention is not necessarily limited to such composition.
As shown in Fig. 2, the flash memory 100 of the present embodiment be configured to include: memory array 110 is formed with and is arranged as matrix
Multiple memory cells of shape；Inputoutput buffer (buffer) 120, is connected to external input output terminal I/O and holding
Inputoutput data；Address register (address register) 130 receives the address from inputoutput buffer 120
Data；Data buffer 140 keeps the data of input and output；Controller 150, based on the life from inputoutput buffer 120
Enabling data and external control signal, (chip (not shown) is energized (chip enable) or address fastens (the address latch that energizes with a bolt or latch
Enable) etc.), supply controls control signal C1, C2, the C3 etc. in each portion；Wordline (word line) selection circuit 160, to coming from
The row address information Ax of address register 130 is decoded (decode), and carries out block selection and wordline based on decoding result
Selection etc.；Page buffer (page buffer)/sensing circuit 170 is kept from the page selected by word line selection circuit 160
The data of reading or keep the data being written to the page that is selected；Column select circuit 180, to from address register 130
Column address information Ay be decoded, and based on the decoding result selection page buffer 170 in column data；And builtin voltage
Generation circuit 190, generate for carry out voltage necessary to reading data, sequencing and erasing etc. (programming voltage Vprog,
Conducting voltage Vpass, reading voltage Vread, erasing voltage Vers etc.).
Memory array 110 have be configured at multiple block BLK (0) of column direction, BLK (1) ..., BLK (m).In area
The one end of block configures page buffer/sensing circuit 170.But page buffer/sensing circuit 170 can also be configured at area
The other end of block or the end of two sides.
As shown in figure 3, form multiple NAND string unit NU in a memory block, the NAND string unit NU be by
Multiple memory cell series connection are formed by connecting, and are arranged with n+1 string location NU along line direction in a block.String location NU packet
Contain: multiple memory cell MCi of series connection (i=0,1,31)；Selection transistor (transistor) TD, even
It is connected to the drain side of the memory cell MC31 as one end；And selection transistor TS, it is connected to depositing as the other end
The source side of storage unit MC0；And the drain electrode of selection transistor TD is connected to a corresponding bit line (bit line) GBL, choosing
The source electrode for selecting transistor TS is connected to common source line SL.
The control grid of memory cell MCi is connected to wordline WLi, and the grid of selection transistor TD, TS are connected to and word
Line WL parallel selection grid polar curve SGD, SGS.Word line selection circuit 160 is when based on row address Ax selection block, via the area
Selection grid polar curve SGS, SGD of block selectively drive selection transistor TD, TS.
For typical case, memory cell have metal-oxide semiconductor (MOS) (Metal-Oxide-Semiconductor,
MOS)) structure, the MOS structure includes: as the source/drain of N-type diffusion zone, being formed in P well (well)；Tunneling oxygen
Change film, is formed on the channel of source/drain interpolar；Floating grid (charge accumulation layer), is formed on tunnel oxide film；And control
Grid is formed on floating grid across dielectric substance film.When the non-accumulated charge of floating grid, i.e., when data " 1 " are written into, threshold
Value is in negative state, and memory cell is normally opened (normally on).When floating grid accumulation has electronics, i.e. data " 0 " quilt
When write-in, threshold shift is positive, and memory cell is often to close (normally off).But memory cell is not limited to store
Unit (bit), also can store multidigit.
Table 1 is the table for indicating an example of bias (bias) voltage applied in each operation of flash memory.In read operation,
Certain positive voltage is applied to bit line, certain voltage (such as 0V) is applied to selected wordline, conducting voltage is applied to non-selection wordline
Vpass (such as 4.5V) applies positive voltage (such as 4.5V) to selection grid polar curve SGD, SGS, makes bit line selection transistor TD, source
Polar curve selection transistor TS is connected, and applies 0V to common source line.In sequencing (write-in) operation, selected wordline is applied
The programming voltage Vprog (15V~20V) of high voltage applies intermediate potential (such as 10V) to non-selected wordline, makes position
Line options transistor TD is connected, and disconnects source electrode line selection transistor TS, corresponding for the data for giving " 0 " or " 1 " to bit line GBL
Current potential.In erasing operation, 0V is applied to the selected wordline in block, high voltage (such as 20V) is applied to P well, it will
The electronics of floating grid is drawn to substrate, whereby, wipes data as unit of block.
[table 1]
Fig. 4 is the figure for indicating an example of system of the flash memory comprising the present embodiment.The system 200 of the present embodiment includes host
Equipment 210 and the memory module 220 for being connected to the host equipment 210.Host equipment 210 is not particularly limited, and is computer, number
The electronic devices such as word camera, printer or the chip for being equipped on chipset.Memory module 220 includes to have and Figure 1A, Figure 1B
Shown in the identical function of Memory Controller 14 Memory Controller 230 and flash memory 100.Memory Controller 230 controls
Data transmission between host equipment 210 and flash memory 100 etc..
For the flash memory of the present embodiment in the case where storage security high information, the information leakage, has one in order to prevent
Secondary read mode.If setting a read mode, the information that a reading area is set in after powering on just can only be read
It takes primary.The state continues to before power on next time, i.e., when being again switched on power supply, is set in the letter of a reading area
Breath just can only be read primary again.It is prevented in the operating process of system as a result, highly-safe information is read several times.
In order to keep a read mode of flash memory 100 effective, flash memory 100 is initially set.Initial setting using with
The different prespecified specific command of common order, sets specific address information to order memory area, and to primary
Reading area sets highly-safe confidential information.In preference, only when specific address information is consistent, it is set in one
The confidential information of secondary reading area can be just read once.
Fig. 5 is for illustrating flow chart initially set.It is used firstly, being issued from host equipment 210 to memory module 220
In progress specific command (S100) initially set.Specific command is and common sequencing initiation command (80h, 81h, 85h)
Different orders, the preferably only hiding order that would know that of specific user or system.If the spy sent from host equipment 210
Fixed order is received by the controller 150 of flash memory 100, and controller 150 is just started based on specific command for sequence initially set.
Then, address (S102) of the input for once reading from host equipment 210 to flash memory 100.In this, in order to it is logical
Normal address is distinguish, and the address inputted when inputting specific command is known as particular address.Particular address may include row ground
Location (page address) and column address, but can also be row address (page address) in the case where selecting a page entirety.If
It is entered particular address, particular address is just stored in non-volatile address storage region (S104) by controller 150.Preferably,
Non-volatile address storage region is non-volatile configuration buffer (Configuration Register, CR).
As shown in fig. 6, the flash memory 100 of the present embodiment has non-volatile configuration buffer 240 and volatibility configuration temporary
Device 250.In general, non-volatile configuration buffer 240, volatibility configuration buffer 250 can not be read in operation by user
It takes or is written, but can be read out or be written and executing certain AD HOC or order.
Non-volatile configuration buffer 240 includes the order memory area 242 of storage particular address and indicates in address
Storage region 242 stores region label (flag) 244 of particular address.Non-volatile configuration buffer 240 is also comprising setting
The region 246 of the operation information of flash memory 100.Necessary information when the storage of region 246 such as starting flash memory.Non-volatile configuration
Buffer 240 may include such as NOR type or NAND type memory element, Electrical Erasable programmble read only memory PROM
(Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic-resistance random access are deposited
Reservoir (Magnetic Random Access Memory, MRAM), variable resistance type random access memory (Resistive
Random Access Memory, ReRAM) etc. memory elements etc..
Volatibility configuration buffer 250 may remain in after system starts from the reading of non-volatile configuration buffer 240
The information such as particular address.Volatibility configuration buffer 250 may include such as static random access memory (Static Random
Access Memory, SRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM) etc. deposits
Store up element.
It should be noted here that particular address indicates address space workable for user in memory array 110, and also
It is the identification information for making it possible once to read.In addition, when being entered particular address in initial setting, wordline choosing
The page of circuit 160 and non-selection memory array 110 is selected, but selects the storage region hidden from memory array 110
The page.Hiding storage region is the storage region of non-volatile programmable, such as is set in and user is available deposits
The separated region of memory array 110.
Concrete example initially set is indicated in Fig. 7.After inputting specific command, " PA_N " can be then inputted as specific page
Face address.In addition, particular address only includes page address.If specific webpage address PA_N is input to address register 130,
Under control of the controller 150, it deposits the address that specific webpage address PA_N will be stored in non-volatile configuration buffer 240
Storage area domain 242.
Specific webpage address PA_N is the page of the available address space of user in memory array 110, but wordline is selected
Circuit 160 is selected not select the specific webpage address PA_N of memory array 110, but selects to hide from memory array 110
The mode of storage region 112 operate.Although hiding storage region 112 can also physically be formed in memory array 110
It is interior, but it is that user can not specify the unserviceable data storage areas of address, i.e. user.Hiding storage region 112 is for example
It is identically formed with memory array 110 in the block comprising NAND string unit, when being entered specific command, Ke Yitong
Word line selection circuit 160 is crossed to be selected.In addition, hiding storage region 112 also may include the storage other than NAND string unit
Element.For example, storage region 112 also may include the memory elements such as MRAM, ReRAM, EEPROM, NOR.In this case, right
The access of storage region 112 not necessarily uses word line selection circuit 160, other dedicated selection circuits also can be used.
Fig. 5 is returned again to, then program data (S106) of the input for once reading.The program data is safety
High confidential information, for example, safety code, decruption key, privacy information etc..The program data of input is via Data buffer 140
And it is supplied to page buffer/sensing circuit 170, as shown in fig. 7, being programmed in the page of hiding storage region 112.
It, can be only to being selected according to particular address by column select circuit 180 in the case where the size of program data is less than a page
Bit line supplies program data.On the contrary, in the case where the size of program data is greater than a page, such as can specify specific webpage
Address PA_N is header page, to from the continuous page write-in program data of header page.In this way, what end was used to once read
Initial setting.
Then, a read operation of the flash memory of the present embodiment is illustrated.Controller 150 includes primary for controlling
The program or state machine of read mode.Fig. 8 is the functional frame constituted indicated when controller 150 controls a read mode
Figure.Comparing section 300 has: comparing section 300, when the page for carrying out flash memory 100 is read, compares and is input to address register
130 address and the particular address for being held in volatibility configuration buffer 250；And control unit 310, the ratio based on comparing section 300
Relatively result controls each portion.
As described below, control unit 310 executes control S1, control S2 and control S3 etc. in the energization sequence of flash memory 100,
The control S1 is for making the particular address for being stored in non-volatile configuration buffer 240 be transmitted to volatibility configuration buffer
250 and the particular address is kept, the control S2 is used for when showing that two-address is consistent by comparing portion 300, and erasing is held in
The particular address of volatibility configuration buffer 250, the control S3 allow word when showing that two-address is consistent by comparing portion 300
The page of the hiding storage region 112 of the selection of line options circuit 160.
Then, referring to the flow chart of Fig. 9, a read operation of the present embodiment is described in more detail.The example is, initial
When setting, specific webpage address is set to the order memory area 242 of non-volatile configuration buffer 240, and do not set column ground
Location.
If system 200 shown in Fig. 4 starts, flash memory 100 is powered on (S200), controller 150 just starts to be used for
Be powered the program to sort or state machine.Firstly, controller 150 accesses non-volatile configuration buffer 240, inspection is set in label
The label in region 244, determines whether initial setting is carrying out (S202).If do not set initially, controller 150 is just not
A read mode can be moved to, but carries out operating (S204) as previous.
On the other hand, when being set with label, i.e., when initial setting is completed, controller 150 goes to a read mode, into
The control (S206) that row is once read.If going to a read mode, controller 150 is just due to non-volatile configuration buffer
It is stored with specific webpage address in 240, and executes internal read command " 00h " (S208).By execution " 00h ", from non-volatile
Property configuration buffer 240 order memory area 242 read specific webpage address (S210), and specific webpage address is held in
Volatibility configuration buffer 250 (S212).Figure 10 A indicates specific webpage address PA_N being set in volatibility configuration buffer
250 the case where.Processing before step S212 is carried out by the sequence that is powered.
Later, host equipment 210 is read (S214) to flash memory 100.Read operation is as in the past, flash memory
100 receive reading order and address from host equipment 210.Response read operation, the execution of controller 150 internal read command "
30h"(S216).By executing the order, the address for being input to address register 130 is read.
Then, comparing section 300 compare be held in the specific webpage address of volatibility configuration buffer 250 with from address temporary
The page address that device 130 is read determines whether two-address is consistent (S218).Assuming that address is inconsistent, just implement the common page
It reads (S220).That is, the page address being entered is selected by word line selection circuit 160, to page buffer/sensing circuit
The data for the page that 170 transmission are selected, and exported via inputoutput buffer 120 to host equipment 210.Figure 10 B is indicated
Input example of the PA01 as page address.Since page address PA01 and specific webpage address PA_N are inconsistent, wordline
Selection circuit 160 selects page address PA01, reads the data of page address PA01.
On the other hand, the page address that input is determined by comparing portion 300 and (S218) under particular address unanimous circumstances,
The page for the storage region 112 that controller 150 (control unit 300) enables the selection of word line selection circuit 160 hiding, and to page buffer
Device/sensing circuit 170 transmits the data (S222) for being stored in storage region 112.Then, the erasing of control unit 300 is held in volatile
Property configuration buffer 250 specific webpage address or make its invalid (S224).Later, it is deposited from the reading of inputoutput buffer 120
It is stored in the data (S226) of the page of storage region 112.
Figure 10 C indicates example of the input specific webpage address PA_N as page address.Due to the page address PA_ of input
N is consistent with specific webpage address PA_N, the page of the hiding storage region 112 of the selection of word line selection circuit 160, and slow to the page
It rushes device/sensing circuit 170 and transmits the data for being stored in the page.At this time, it should be noted that the specific webpage address of memory array 110
PA_N is simultaneously unselected.
In this way, just can read if the page address being entered is consistent with specific webpage address and be stored in hiding storage
The data of the page in region 112, but the reading is restricted to only once.That is, if with the consistent page in specific webpage address
Address is entered once, will be wiped the specific webpage address for being held in volatibility configuration buffer 250 or be kept it invalid, because
This, even if being entered again with the consistent page address in specific webpage address, comparing section 300 can also determine that two-address is different
It causes, without determining that two-address is consistent.So word line selection circuit 160 will not select the page of hiding storage region 112.
Example of Figure 10 D expression after once read, when being entered with the consistent page address of particular address.In page address
When PA_N is entered, since volatibility configuration buffer 250 does not substantially keep specific webpage address, comparing section 300 is sentenced
It is inconsistent to determine two-address.Therefore, the page of word line selection circuit 160 and non-selection hiding storage region 112, but selection is deposited
The specific webpage address PA_N of memory array 110 reads the data for being stored in specific webpage address PA_N.
According to the present embodiment, in the very high letter of the confidentialities such as flash memory storage safety code, decruption key or private data
In the case where breath, the reading times of the high information of such confidentiality are limited to once, therefore important information can be prevented easily
Ground is read or is replicated.In addition, by by virtual data (dummy data) sequencing in the memory array as user area
The specific webpage address PA_N of column 110, system are read out because of malice access or illegal access in virtual data, can use
Virtual data tracks illegal access.
In the example shown in Fig. 9, expression is to set to mark to non-volatile configuration buffer 240, is being set
The example (S202, S206) of a read mode is gone to when having label, but such label sets or is not using the judgement of label
It is required.In another preferred embodiment, flash memory 100 can set independent of label and selectively hold when power supply is connected
The primary reading of row or common operation.When being not carried out primary reading, i.e., non-volatile configuration buffer 240 is not carried out initially
When setting, the order memory area 242 of non-volatile configuration buffer 240 is default (default), therefore to volatibility configuration
The address information (being the data of F) of the transmission erase status of buffer 250.In the page address information of the erase status and user
In the case that selectable address information is inconsistent, common read operation is necessarily carried out.On the other hand, if stored to address
Region 242 sets particular address, by with the identical operation, only when particular address is consistent with the address that user selects
Just read the data of hiding storage region.
Then, illustrate the second embodiment of the present invention.What the embodiment indicated is the example once read, and second implements
Example is able to carry out limited multiple reading.Figure 11 is the functional figure constituted for indicating second embodiment.In a second embodiment,
The consistent number of additional counter 320,320 pairs of two-addresses determined using comparing section 300 of the counter is counted.Counter
When the 320 consistent number in two-address reaches pre-determined times N, the situation is notified to control unit 300.Control unit 300 returns
It should notify, erasing is held in the specific webpage address of volatibility configuration buffer 250 or keeps it invalid.It is stored in as a result, hidden
The data of the storage region 112 of hiding can only be read with limited times N.
Although describing the preferred embodiment of the present invention in detail, the present invention is not limited to a specific embodiment,
Various modifications and changes are carried out in the main scope of the invention that can be recorded in the claims.
In the described embodiment, if specific webpage address initially set is user area, it can be set in any place,
Therefore it can expand the freedom degree of address of cache (mapping).In addition, the embodiment expression is to deposit specific webpage address
It is stored in the example of configuration buffer, but specific webpage address is not necessarily stored in configuration buffer, is stored in other
Storage region.Moreover, the internal read command that the embodiment instantiates " 00h ", " 30h " is executed as flash memory, but and it is unlimited
Due to this, as long as the order for being set in the page address of buffer or control signal can be read.
Moreover, in the described embodiment, instantiating a specific webpage address, but not limited to this, also can be used
Multiple specific webpage addresses, to 112 programming data of storage region corresponding with multiple specific webpage addresses.
Claims (10)
1. a kind of semiconductor memory system comprising:
With nand-type memory array；
Input unit, input address information, data and instruction store the specific command of the first address information and the first data, wherein institute
It states specific command to receive from host equipment, and including first address information and first data；
Reading part, based on the address information inputted from the input unit, reading is stored in described and nand-type memory array
The data；
Configuration part stores first address information in the semiconductor memory system according to the specific command of input
Order memory area using as particular address information,
Wherein the configuration part stores first data and fills in the semiconductor memory according to the specific command of input
Believed by first address wherein first data are not stored in as specific data in the hiding data storage region set
First address of the described and nand-type memory array of breath instruction；And
Control unit controls the reading part, and
The control unit particular address information and the second address letter from input unit input in read operation
Breath, wherein the read operation is to be stored in and nand-type memory array to read by second address information instruction
Two address second data,
Wherein when second address information and the particular address information are inconsistent, the reading part is not read from described
The specific data of hiding data storage region, but read according to second address information and stored from described with nand-type
Two address second data of device array,
Wherein when second address information is consistent with the particular address information, the control unit is wiped or makes to be stored in institute
The particular address information for stating order memory area is invalid, and the reading part reads and comes from the hiding data memory block
The specific data in domain.
2. semiconductor memory system as described in claim 1, wherein the configuration part includes non-volatile address memory block
Domain and volatibility order memory area, and the order memory area domain is non-volatile order memory area, wherein described set
Portion is determined after power supply connection, and the particular address information for being stored in the non-volatile address storage region is sent and stored
To the volatibility order memory area, the control unit is consistent with the particular address information in second address information
When, erasing is stored in the particular address information of the volatibility order memory area.
3. semiconductor memory system as claimed in claim 1 or 2, wherein the particular address information is simultaneous described to may be selected
With the address of the address space of nand-type memory array.
4. semiconductor memory system as claimed in claim 1 or 2, wherein the hiding data storage region is set in and uses
The different region of the available memory array in family.
5. semiconductor memory system as claimed in claim 1 or 2, wherein the order memory area is configuration buffer.
6. semiconductor memory system as claimed in claim 1 or 2, wherein the control unit includes count section, the counting
Portion counts second address information that the input unit inputs with the consistent number of the particular address information, and
In the read operation of the control unit, when second address information is consistent with the particular address information, erasing or
Keep the particular address information for being stored in the order memory area invalid,
The control unit is wiped when the count results of the count section reach pre-determined value or believes the particular address
Breath is invalid.
7. a kind of semiconductor system, comprising semiconductor memory system as claimed in claim 1 or 2 and with the semiconductor
The host equipment of memory device connection, and
The host equipment by the specific command to the semiconductor memory system export the particular address information and
The specific data.
8. a kind of read method, for reading specific data in the system comprising semiconductor memory system and host equipment,
Include:
Specific command is exported to the semiconductor memory system by the host equipment, wherein the specific command includes spy
Determine address information and specific data, and indicates to store the particular address information and the specific data；
The particular address information is stored in the order memory area of the semiconductor memory system according to the specific command,
And the specific data is stored in the hiding data storage region of the semiconductor memory system, wherein the specific data is not
It is stored in being indicated by the particular address information with nand-type memory array the first address；And
In read operation, the address information of the particular address information and the input corresponding to the read operation,
Described in read operation be to read be stored in described in the semiconductor memory system with nand-type memory array
Two address data, and second address is as indicated by the address information of the input,
When the address information of the input and the inconsistent particular address information, do not read from the hiding data storage region
Take the specific data, but according to the address information of the input from described with nand-type memory array second address
The data are read,
When the address information of the input is consistent with the particular address information, wipes or make to be stored in the address storage area
The particular address information in domain is invalid, and reads the specific data from the hiding data storage region.
9. read method as claimed in claim 8, wherein the semiconductor memory system is stored comprising non-volatile address
Region and volatibility order memory area, and the order memory area domain is non-volatile order memory area, wherein described
Read method further includes that will be stored in the particular address of the non-volatile address storage region after connecting system power supply
Information sends and is stored in the volatibility order memory area, and when the address information and the particular address of the input
When information is consistent, the particular address information of the volatibility order memory area is wiped.
10. read method as claimed in claim 8 or 9, wherein the read method further include:
The address information and the consistent number of the particular address information of the input are counted；And
When count results reach pre-determined value, wipes or keep the particular address information invalid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410464625.3A CN105469822B (en) | 2014-09-12 | 2014-09-12 | Semiconductor memory system, semiconductor system and read method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410464625.3A CN105469822B (en) | 2014-09-12 | 2014-09-12 | Semiconductor memory system, semiconductor system and read method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105469822A CN105469822A (en) | 2016-04-06 |
| CN105469822B true CN105469822B (en) | 2019-10-18 |
Family
ID=55607440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410464625.3A Active CN105469822B (en) | 2014-09-12 | 2014-09-12 | Semiconductor memory system, semiconductor system and read method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105469822B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6492202B1 (en) * | 2018-03-05 | 2019-03-27 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor memory device and erasing method |
| US11049565B2 (en) | 2018-04-23 | 2021-06-29 | Micron Technology, Inc. | Non-volatile memory devices and systems with volatile memory features and methods for operating the same |
| US10446248B1 (en) * | 2018-04-23 | 2019-10-15 | Micron Technology, Inc. | Non-volatile memory devices and systems with read-only memory features and methods for operating the same |
| CN109542685A (en) * | 2018-11-20 | 2019-03-29 | 江门市兰格电子有限公司 | Checking memory data method, apparatus, equipment and medium based on more sectors |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3892832B2 (en) * | 2003-08-11 | 2007-03-14 | 株式会社東芝 | Semiconductor memory device |
| KR20090043823A (en) * | 2007-10-30 | 2009-05-07 | 삼성전자주식회사 | Memory system for sensing external attack |
| KR20100058825A (en) * | 2008-11-25 | 2010-06-04 | 삼성전자주식회사 | Semiconductor device using variable resistive element, card or system using the same and operating method the semiconductor device |
| JP2011108306A (en) * | 2009-11-16 | 2011-06-02 | Sony Corp | Nonvolatile memory and memory system |
| WO2014061064A1 (en) * | 2012-10-18 | 2014-04-24 | Hitachi, Ltd. | Cache control apparatus and cache control method |
-
2014
- 2014-09-12 CN CN201410464625.3A patent/CN105469822B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN105469822A (en) | 2016-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI665682B (en) | Semiconductor memory device and memory system | |
| JP4603892B2 (en) | Current limited latch | |
| TW201822212A (en) | Memory cell | |
| JP2005108273A (en) | Nonvolatile semiconductor memory device | |
| US9489143B2 (en) | Method for accessing flash memory and associated controller and memory device | |
| KR20080021649A (en) | Devices for programming a memory | |
| CN105469822B (en) | Semiconductor memory system, semiconductor system and read method | |
| CN106558330B (en) | Semiconductor device, method of operating the same, and data storage apparatus including the same | |
| US8064267B2 (en) | Erase voltage reduction in a non-volatile memory device | |
| CN101740124A (en) | Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method | |
| KR101731408B1 (en) | Method for writing data into flash memory and associated memory device and flash memory | |
| US8942038B2 (en) | High endurance nonvolatile memory | |
| JP2012048770A (en) | Nonvolatile semiconductor storage device, and memory system | |
| KR20130119830A (en) | Semiconductor memory devices | |
| US20180330793A1 (en) | Responding to power loss | |
| JP5734492B1 (en) | Semiconductor memory device | |
| TWI724778B (en) | Random bit cell and random bit system | |
| US20140136579A1 (en) | File storing method, and storage medium, computer system usable for the file storing method | |
| TWM320715U (en) | Operating system for extending life-time of flash memory | |
| US20050232021A1 (en) | Non-volatile memory comprising means for distorting the output of memory cells | |
| JP2010218623A (en) | Nonvolatile semiconductor storage device | |
| JP2007257748A (en) | Nonvolatile storage device | |
| KR101633442B1 (en) | Semiconductor memory device, semiconductor system and reading method | |
| TWI537963B (en) | Semiconductor memory device, semiconductor system and reading method | |
| JP2006313873A (en) | Nonvolatile memory element with uniform program speed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |