CN105450234A - Verification apparatus of QC-LDPC code in DTMB - Google Patents
Verification apparatus of QC-LDPC code in DTMB Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
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Abstract
The invention provides a verification apparatus of a QC-LDPC code in DTMB. The verification apparatus is composed of five parts, i.e., sixty-two ring-shift-left devices C1 to C62, sixty-one b-bit XOR gates X1 to X61, sixty-two multiplexers M1 to M62, sixty-two b-bit registers R1 to R62 and one look-up table ROM. According to the invention, a full-diagonal structure of a QC-LDPC code verification matrix in the DTMB is fully utilized, and the provided verification apparatus is compatible with three code rates and has the advantages of simple structure, fast verification speed, small memory demand and the like.
Description
Technical field
The present invention relates to field of channel coding, particularly the efficient calibration equipment of QC-LDPC code in a kind of DTMB standard.
Background technology
Low-density checksum (Low-DensityParity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code.The generator matrix G of QC-LDPC code and check matrix H are all the arrays be made up of circular matrix, have the feature of Circulant Block, therefore are called as quasi-cyclic LDPC code.The first trip of circular matrix is the result of footline ring shift right 1, and all the other each provisional capitals are results of its lastrow ring shift right 1, and therefore, circular matrix is characterized by its first trip completely.Usually, the first trip of circular matrix is called as its generator polynomial.
The row of circular matrix is heavy identical with column weight, is denoted as w.If w=0, so this circular matrix is full null matrix.If w=1, so this circular matrix is replaceable, is called permutation matrix, and it is by obtaining the some positions of unit matrix I ring shift right.The check matrix H of QC-LDPC code is by c × t b × b rank circular matrix H
i,jthe following array that (1≤i≤c, 1≤j≤t) is formed:
Usually, all circular matrixes in H are full null matrix (w=0) or are permutation matrix (w=1).
In a communications system, receiving terminal can carry out decoding to the code word received and verify.When decode results v meets Hv
twhen=0, calibration equipment thinks that v is exactly the code word that transmitting terminal sends, and decoding terminates.
For general QC-LDPC code, calibration equipment forms primarily of ROM, barrel shifter and accumulator.Clock periodicity needed for verification equals the number α of permutation matrix in H.ROM stores the ring shift right figure place of the relative I of each permutation matrix and the block line number at place thereof and block row number, needs α ([log
2b]+[log
2t]+[log
2c]) memory of bit, wherein, symbol [x] represents the smallest positive integral being not less than x.
DTMB is the English abbreviation of digital television terrestrial broadcasting system, and English full name is DigitalTelevisionTerrestrialMultimediaBroadcasting.DTMB standard have employed the QC-LDPC code of 3 kinds of different code checks.For these 3 kinds of QC-LDPC codes, all there is t=59 and b=127.Fig. 1 gives parameter c under different code check η and α.
For 3 kinds of different code checks, in DTMB standard, the checking time needed for existing calibration equipment of QC-LDPC code is 275,296 and 294 clock cycle respectively.3 kinds of code checks need 16435 bit ROM altogether.
Summary of the invention
The check matrix of the QC-LDPC code that DTMB standard adopts has full diagonal structure, the present invention is directed to this QC-LDPC code and provides a kind of efficient calibration equipment.
As shown in Figure 5, calibration equipment is made up of 4 parts: 62 ring shift left device C
1~ C
62, 61 b bit XOR gate X
1~ X
61, 62 multiplexer M
1~ M
62, 62 b bit register R
1~ R
62with 1 look-up table ROM.Whole checking procedure divides 6 steps to complete: the 1st step, resets all b bit register R
1~ R
62; 2nd step, input decoding section v
j, look-up table ROM is the H of η according to code check η and row j bit rate output
ejth row 62 bit, wherein, 1≤j≤t; 3rd step, as 0≤s
kduring <b, ring shift left device C
kto decoding section v
jring shift left s
kposition, and work as s
kduring=∞, ring shift left device C
knot to decoding section v
jring shift left but it is directly exported, as k=62, ring shift left device C
koutput and multiplexer M
kbe connected, and as 1≤k<62, ring shift left device C
koutput and b bit XOR gate X
kbe connected, wherein, 1≤k≤62, s
k∈ ∞, 0,1 ..., b-1}; 4th step, b bit XOR gate X
kto ring shift left device C
koutput rusults and b bit register R
k+1content carry out mould 2 and add, and send into multiplexer M
k; 5th step, multiplexer M
kinput alternatives according to the kth bit that look-up table ROM exports to 2, selection result sends into b bit register R
k, as k=62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect full null vector, otherwise, multiplexer M
kselect ring shift left device C
koutput rusults, as 1≤k<62, if look-up table ROM export kth bit be 0, then multiplexer M
kselect b bit register R
k+1content, otherwise, multiplexer M
kselect b bit XOR gate X
koutput rusults; 6th step, with 1 for step-length increases progressively the value changing j, repeats 2nd ~ 5 step t-1 time, until whole decode results v inputs complete, now, if b is bit register R
1~ R
tcontent be all zero, then decode results is correct, otherwise, decode results mistake.
The present invention takes full advantage of the full diagonal structure of QC-LDPC code check matrix in DTMB standard, and the compatible 3 kinds of code checks of the calibration equipment provided, have the advantages such as structure is simple, verification speed is fast, memory footprint is few.
Be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.
Accompanying drawing explanation
Fig. 1 gives parameter c under different code check η and α;
Fig. 2 is the check matrix H schematic diagram of η=0.8 code check QC-LDPC code in DTMB standard;
Fig. 3 is the basic matrix H of η=0.8 code check QC-LDPC code in DTMB standard
bASEschematic diagram;
Fig. 4 is the extended matrix H of η=0.8 code check QC-LDPC code in DTMB standard
eschematic diagram;
Fig. 5 is the calibration equipment functional block diagram of QC-LDPC code in DTMB standard.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.
For the QC-LDPC code of code check arbitrary in DTMB standard, the arbitrary circular matrix H in check matrix H
i,j(1≤i≤c, 1≤j≤t) is full null matrix or is permutation matrix.Work as H
i,jwhen being permutation matrix, it can be considered unit matrix I ring shift right s
i,jthe result of position, wherein, 0≤s
i,j<b.For ease of describing, work as H
i,jwhen being full null matrix, it is denoted as to unit matrix I ring shift right s
i,jthe result of=∞ position, i.e. I
∞=0.To sum up, s
i,j∈ ∞, 0,1 ..., b-1}.
In DTMB standard, arbitrary code check QC-LDPC code all has full diagonal check matrix H.Fig. 2 is the H schematic diagram of η=0.8 code check QC-LDPC code in DTMB standard, and the numeral circular matrix in figure is relative to the ring shift right figure place s of unit matrix I
i,j.Fig. 2 has t+c-1 bar diagonal, and every bar diagonal is all circular matrix.For the circular matrix on arbitrary diagonal, may be all full null matrix (as shown in article diagonal of the 68th in Fig. 2, s
10,1=s
11,2=∞), also may be all identical permutation matrix (as shown in article diagonal of the 3rd in Fig. 2, s
1,57=s
2,58=s
3,59=65), also may a part be full null matrix, remainder be identical permutation matrix (as shown in the Sub_clause 11 diagonal in Fig. 2, s
isosorbide-5-Nitrae 9=∞, and s
2,50=s
3,51=...=s
11,59=34).If the circular matrix on kth bar diagonal is all full null matrix, then they are all to unit matrix I ring shift right s
kthe result of=∞ position; Otherwise the permutation matrix on this diagonal is all to unit matrix I ring shift right s
k∈ 0,1 ..., the result of b-1} position, wherein, 1≤k≤t+c-1.To sum up, s
k∈ ∞, 0,1 ..., b-1}.In fig. 2, s
68=∞, s
3=65, s
11=34.
If by the full null matrix in " 0 " mark H, with " 1 " mark permutation matrix, so H just can be expressed as basic matrix H
bASE.Fig. 3 is the H that in Fig. 2, H is corresponding
bASE.H
bASEit is the binary matrix on c × t rank.
Next, to H
bASEcarry out expansion and cyclic shift.First, at H
bASEtop increase the full null matrix on (t-1) × t rank, be extended to the binary matrix on (t+c-1) × t rank.Then, to the H after expansion
bASEjth row circulation on move j-1 position, wherein, 2≤j≤t.Finally, all full zero row of bottom of the matrix after circulation moves are deleted.According to aforesaid operations, the H in Fig. 3
bASEbecome the extended matrix H shown in Fig. 4
e.
For code check QC-LDPC code arbitrary in DTMB standard, H
eall the binary matrix on 62 × t rank, and s
1~ s
62114 respectively, 79,65,68,23,117,28,13,92,84,34,12,29,102,62,3,8,122,78,115,17,70,110,53,74,21,41,67,66,42,81,60,126,31,2,63,16,116,24,57,40,22,69,18,89,48,113,120,124,5,83,93,105,47,90,101,30,0, ∞, 1,32 and 104.
In a communications system, receiving terminal can carry out decoding to the code word received and verify.Be one section with b bit, decode results v is divided into t section, i.e. v=(v
1, v
2..., v
t).When meeting Hv
twhen=0, calibration equipment thinks that v is exactly the code word that transmitting terminal sends, and decoding terminates.
For the QC-LDPC code in DTMB standard, Fig. 5 gives its calibration equipment, compatible 3 kinds of code checks.This calibration equipment is by 62 ring shift left device C
1~ C
62, 61 b bit XOR gate X
1~ X
61, 62 multiplexer M
1~ M
62, 62 b bit register R
1~ R
62form with 1 look-up table ROM.
Look-up table ROM stores 62 × t rank extended matrix H by column
ein binary data, 3 kinds of code check QC-LDPC codes share this look-up table ROM, and its width is 62 bits, and the degree of depth is 3 × t.Look-up table ROM is the H of η according to code check η and row j bit rate output
ejth row 62 bit, wherein, 1≤j≤t.
As 0≤s
kduring <b, ring shift left device C
kto decoding section v
jring shift left s
kposition; Work as s
kduring=∞, ring shift left device C
knot to decoding section v
jring shift left but it is directly exported, wherein, 1≤j≤t, 1≤k≤62, s
k∈ ∞, 0,1 ..., b-1}.As k=62, ring shift left device C
koutput and multiplexer M
kbe connected; As 1≤k<62, ring shift left device C
koutput and b bit XOR gate X
kbe connected.
B bit XOR gate X
kto ring shift left device C
koutput rusults and b bit register R
k+1content carry out mould 2 and add, and send into multiplexer M
k, wherein, 1≤k≤61.
Multiplexer M
k, input alternatives according to the kth bit that look-up table ROM exports to 2, selection result sends into b bit register R
k, wherein, 1≤k≤62.As k=62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect full null vector; Otherwise, multiplexer M
kselect ring shift left device C
koutput rusults.As 1≤k<62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect b bit register R
k+1content; Otherwise, multiplexer M
kselect b bit XOR gate X
koutput rusults.
For the QC-LDPC code in DTMB standard, the invention provides a kind of efficient method of calibration, compatible 3 kinds of code checks, its checking procedure is described below:
1st step, resets all b bit register R
1~ R
62;
2nd step, input decoding section v
j, look-up table ROM is the H of η according to code check η and row j bit rate output
ejth row 62 bit, wherein, 1≤j≤t;
3rd step, as 0≤s
kduring <b, ring shift left device C
kto decoding section v
jring shift left s
kposition, and work as s
kduring=∞, ring shift left device C
knot to decoding section v
jring shift left but it is directly exported, as k=62, ring shift left device C
koutput and multiplexer M
kbe connected, and as 1≤k<62, ring shift left device C
koutput and b bit XOR gate X
kbe connected, wherein, 1≤k≤62, s
k∈ ∞, 0,1 ..., b-1};
4th step, b bit XOR gate X
kto ring shift left device C
koutput rusults and b bit register R
k+1content carry out mould 2 and add, and send into multiplexer M
k;
5th step, multiplexer M
kinput alternatives according to the kth bit that look-up table ROM exports to 2, selection result sends into b bit register R
k, as k=62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect full null vector, otherwise, multiplexer M
kselect ring shift left device C
koutput rusults, as 1≤k<62, if look-up table ROM export kth bit be 0, then multiplexer M
kselect b bit register R
k+1content, otherwise, multiplexer M
kselect b bit XOR gate X
koutput rusults;
6th step, with 1 for step-length increases progressively the value changing j, repeats 2nd ~ 5 step t-1 time, until whole decode results v inputs complete, now, if b is bit register R
1~ R
tcontent be all zero, then decode results is correct, otherwise, decode results mistake.
Be not difficult to find out from above step, whole checking procedure needs t clock cycle altogether, and the clock periodicity needed for existing calibration equipment equals the number α of permutation matrix in H.For 3 kinds of code check QC-LDPC codes in DTMB standard, all have t=59, and α is 275,296 and 294 respectively.Therefore, the former coding rate is 4.7,5.0 and 5.0 times of the latter respectively.
The present invention needs 7874 registers, 7747 two input XOR gate and 10974 bit memory.Ring shift left device just changes line, not consumption of natural resource.Existing calibration equipment needs use 16435 bit memory.
As fully visible, the present invention takes full advantage of the full diagonal structure of QC-LDPC code check matrix in DTMB standard, compatible 3 kinds of code checks, has the advantages such as structure is simple, verification speed is fast, memory footprint is few.
The above; be only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the technical scope disclosed by the present invention; the change can expected without creative work or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection range that protection scope of the present invention should limit with claims is as the criterion.
Claims (2)
1. the calibration equipment of QC-LDPC code in a DTMB, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is DigitalTelevisionTerrestrialMultimediaBroadcasting, DTMB standard have employed the QC-LDPC code of 3 kinds of different code checks, 3 kinds of different code check η are 0.4,0.6,0.8 respectively, check matrix H is the array be made up of c × t b × b rank circular matrix, arbitrary circular matrix H
i,jbe full null matrix or be permutation matrix, wherein, 1≤i≤c, 1≤j≤t, for these 3 kinds different code check QC-LDPC codes, all has t=59 and b=127, and the parameter c that 3 kinds of different code checks are corresponding is 35,23,11 respectively, works as H
i,jwhen being permutation matrix, it can be considered b × b rank unit matrix I ring shift right s
i,jthe result of position, wherein, 0≤s
i,j<b, works as H
i,jwhen being full null matrix, it is denoted as to b × b rank unit matrix I ring shift right s
i,jthe result of=∞ position, i.e. I
∞=0, check matrix H has t+c-1 bar diagonal, circular matrix on arbitrary diagonal, it may be all full null matrix, also may be all identical permutation matrix, also may a part be full null matrix, remainder is identical permutation matrix, if the circular matrix on kth bar diagonal is all full null matrix, then they are all to b × b rank unit matrix I ring shift right s
kthe result of=∞ position, otherwise the permutation matrix on this diagonal is all to b × b rank unit matrix I ring shift right s
k∈ 0,1 ..., the result of b-1} position, wherein, 1≤k≤t+c-1, if identify the full null matrix in H with " 0 ", with " 1 " mark permutation matrix, so H just can be expressed as basic matrix H
bASE, at H
bASEtop increase the full null matrix on (t-1) × t rank, be extended to the binary matrix on (t+c-1) × t rank, on this basis, to the H after expansion
bASEthe circulation of jth row on move j-1 position, wherein, 2≤j≤t, deletes all full zero row of bottom of matrix after circulation moves, by H
bASEbecome extended matrix H
e, for 3 kinds of different code check QC-LDPC codes in DTMB, H
ebeing 62 × t rank, is one section with b bit, and the decode results v of receiving terminal is divided into t section, i.e. v=(v
1, v
2..., v
t), it is characterized in that, described calibration equipment comprises with lower component:
Look-up table ROM, stores 62 × t rank extended matrix H by column
ein binary data, 3 kinds of code check QC-LDPC codes share this look-up table ROM, and its width is 62 bits, and the degree of depth is 3 × t, and look-up table ROM is the H of η according to code check η and row j bit rate output
ejth row 62 bit, wherein, 1≤j≤t;
Ring shift left device C
1~ C
62, as 0≤s
kduring <b, ring shift left device C
kto decoding section v
jring shift left s
kposition, works as s
kduring=∞, ring shift left device C
knot to decoding section v
jring shift left but it is directly exported, wherein, 1≤j≤t, 1≤k≤62, s
k∈ ∞, 0,1 ..., b-1}, as k=62, ring shift left device C
koutput and multiplexer M
kbe connected, as 1≤k<62, ring shift left device C
koutput and b bit XOR gate X
kbe connected;
B bit XOR gate X
1~ X
61, b bit XOR gate X
kto ring shift left device C
koutput rusults and b bit register R
k+1content carry out mould 2 and add, and send into multiplexer M
k, wherein, 1≤k≤61;
Multiplexer M
1~ M
62, multiplexer M
kinput alternatives according to the kth bit that look-up table ROM exports to 2, selection result sends into b bit register R
k, wherein, 1≤k≤62, as k=62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect full null vector, otherwise, multiplexer M
kselect ring shift left device C
koutput rusults, as 1≤k<62, if look-up table ROM export kth bit be 0, then multiplexer M
kselect b bit register R
k+1content, otherwise, multiplexer M
kselect b bit XOR gate X
koutput rusults.
2. the method for calibration of QC-LDPC code in a DTMB, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is DigitalTelevisionTerrestrialMultimediaBroadcasting, DTMB standard have employed the QC-LDPC code of 3 kinds of different code checks, 3 kinds of different code check η are 0.4,0.6,0.8 respectively, check matrix H is the array be made up of c × t b × b rank circular matrix, arbitrary circular matrix H
i,jbe full null matrix or be permutation matrix, wherein, 1≤i≤c, 1≤j≤t, for these 3 kinds different code check QC-LDPC codes, all has t=59 and b=127, and the parameter c that 3 kinds of different code checks are corresponding is 35,23,11 respectively, works as H
i,jwhen being permutation matrix, it can be considered b × b rank unit matrix I ring shift right s
i,jthe result of position, wherein, 0≤s
i,j<b, works as H
i,jwhen being full null matrix, it is denoted as to b × b rank unit matrix I ring shift right s
i,jthe result of=∞ position, i.e. I
∞=0, check matrix H has t+c-1 bar diagonal, circular matrix on arbitrary diagonal, it may be all full null matrix, also may be all identical permutation matrix, also may a part be full null matrix, remainder is identical permutation matrix, if the circular matrix on kth bar diagonal is all full null matrix, then they are all to b × b rank unit matrix I ring shift right s
kthe result of=∞ position, otherwise the permutation matrix on this diagonal is all to b × b rank unit matrix I ring shift right s
k∈ 0,1 ..., the result of b-1} position, wherein, 1≤k≤t+c-1, if identify the full null matrix in H with " 0 ", with " 1 " mark permutation matrix, so H just can be expressed as basic matrix H
bASE, at H
bASEtop increase the full null matrix on (t-1) × t rank, be extended to the binary matrix on (t+c-1) × t rank, on this basis, to the H after expansion
bASEthe circulation of jth row on move j-1 position, wherein, 2≤j≤t, deletes all full zero row of bottom of matrix after circulation moves, by H
bASEbecome extended matrix H
e, for 3 kinds of different code check QC-LDPC codes in DTMB, H
ebeing 62 × t rank, is one section with b bit, and the decode results v of receiving terminal is divided into t section, i.e. v=(v
1, v
2..., v
t), it is characterized in that, described method of calibration comprises the following steps:
1st step, resets all b bit register R
1~ R
62;
2nd step, input decoding section v
j, look-up table ROM is the H of η according to code check η and row j bit rate output
ejth row 62 bit, wherein, 1≤j≤t;
3rd step, as 0≤s
kduring <b, ring shift left device C
kto decoding section v
jring shift left s
kposition, and work as s
kduring=∞, ring shift left device C
knot to decoding section v
jring shift left but it is directly exported, as k=62, ring shift left device C
koutput and multiplexer M
kbe connected, and as 1≤k<62, ring shift left device C
koutput and b bit XOR gate X
kbe connected, wherein, 1≤k≤62, s
k∈ ∞, 0,1 ..., b-1};
4th step, b bit XOR gate X
kto ring shift left device C
koutput rusults and b bit register R
k+1content carry out mould 2 and add, and send into multiplexer M
k;
5th step, multiplexer M
kinput alternatives according to the kth bit that look-up table ROM exports to 2, selection result sends into b bit register R
k, as k=62, if the kth bit that look-up table ROM exports is 0, then multiplexer M
kselect full null vector, otherwise, multiplexer M
kselect ring shift left device C
koutput rusults, as 1≤k<62, if look-up table ROM export kth bit be 0, then multiplexer M
kselect b bit register R
k+1content, otherwise, multiplexer M
kselect b bit XOR gate X
koutput rusults;
6th step, with 1 for step-length increases progressively the value changing j, repeats 2nd ~ 5 step t-1 time, until whole decode results v inputs complete, now, if b is bit register R
1~ R
tcontent be all zero, then decode results is correct, otherwise, decode results mistake.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911335A (en) * | 2015-12-22 | 2017-06-30 | 北京忆芯科技有限公司 | Ldpc encoder |
-
2016
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911335A (en) * | 2015-12-22 | 2017-06-30 | 北京忆芯科技有限公司 | Ldpc encoder |
| CN106911335B (en) * | 2015-12-22 | 2021-12-28 | 厦门旌存半导体技术有限公司 | LDPC encoder |
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